TUSB6010BZQE, TUSB6010BIZQE www.ti.com www.ti.com SLLA269 – OCTOBER 2007 USB2.0 High Speed (HS) On-the-Go (OTG) Dual Role Controller • • • USB 2.0 HS OTG Dual Role Controller Core – Act as a USB 2.0 HS Peripheral – Act as a USB 2.0 HS Embedded Host Controller – Act as a USB 2.0 HS OTG Device – Supports Session Request Protocol (SRP) – Supports Host Negotiation Protocol (HNP) Integrated USB 2.0 OTG PHY NOR FLASH - Like External Host Interface • • • • Configurable for up to 15 transmit endpoints and up to 15 receive endpoints – 16 kilobyte RAM for USB endpoint FIFO shared by USB IN/OUT endpoints – Configurable FIFOs, including the option of dynamic FIFO sizing – Support for external DMA access to FIFOs Power Management Module – Ultra low power Idle mode for battery conscious applications – Support for External Charge Pump TUSB6010BZQE/TUSB6010BIZQE are RoHS compliant. 80 Terminal BGA Microstar Junior Package DESCRIPTION The TUSB6010B is a USB 2.0 HS Dual Role USB Controller designed for seamless interface to an external Host processor through the NOR FLASH-like interface. The TUSB6010B can be used to enable the processor to implement any one of three genral types of USB devices. It can be implemented as a USB high-speed peripheral (or target), as a USB high-speed, single-port, embedded host controller, or as a USB high-speed OTG device. Software on the application processor will be required to implement the chosen type of USB device. The NOR FLASH-like interface is a multiplexed, 16-bit interface with support for burst and single read/write access. It can operate in both synchronous and asynchronous modes. The Power Management Module provides external USB OTG Charge Pump control through the power control/status interface. The Power Management Module provides a seamless interface to the TPS65030 Power Management IC for USB-OTG. The device also has eight user configurable general purpose I/0 interface pins. The GPIO can be configured as an interrupt or wakeup source. Some GPIO have secondary NOR-flash DMA Request functionality. The device is fully compliant with the Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB Specification Rev. 1.3. The ESD protection level is 2KV HBM (JESD22-A114D), 500V CDM (JESD22-C101C). NOTE: This product is intended for high-volume handset applications only. Contact [email protected] for more information. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated PRODUCT PREVIEW FEATURES 1 TUSB6010BZQE, TUSB6010BIZQE www.ti.com SLLA269 – OCTOBER 2007 Device Power States TUSB6010 has three device states typically entered under normal operation: • RESET • IDLE • NORMAL (ACTIVE) RESET State The device shall be in RESET state when the RSTn input signal is driven low. In the RESET state: • All output ports are tri-stated or initialized to inactive state • All bi-directional ports are configured as Inputs • All registers are set to their reset value • PHY Macro is enabled and its reference clock output is active Device always enters RESET state asynchronously, but exit the state synchronously. System reset de-assertion is always synchronized with active system clock. Upon asserted system reset, device requires active system clock to exit RESET state. IDLE State PRODUCT PREVIEW Device enters the IDLE state when External Host sets DevIdle bit in the Device Power Management register. In the IDLE State, the device power consumption should not exceed 100 μA, including companion Power Management device (TPS65030). In IDLE state: • All output signals are driven to state with minimum IO current leakage (pull-up/pull-downs are controllable through Pull-up/Pull-Down Control registers) • All controllable bi-directional pins are placed into minimum current leakage state • All registers and memories retain the content and any read/write registers access is disabled • All clock sources are disabled • PHY Macro is suspended: – Low power VBUS sense comparator is enabled and all regular VBUS comparators are disabled to minimize current consumption. – ID Detection circuitry is enabled – Remaining analog circuitry is disabled Device stays in the IDLE state until a valid wake-up event occurs and transitions into the NORMAL (ACTIVE) State. If system reset is asserted (RSTn) device transitions to RESET state. NORMAL (ACTIVE) State A transition to the Normal state is required for normal device operation. All circuitry is enabled. In the Normal state: • All I/O are enabled. • All registers and memories are accessible • Clock sources are enabled • PHY Macro is enabled – Session End VBUS detect circuitry shall be enabled – VBUS detection circuitry shall be enabled – ID Detection circuitry shall enabled 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TUSB6010BZQE, TUSB6010BIZQE TUSB6010BZQE, TUSB6010BIZQE www.ti.com SLLA269 – OCTOBER 2007 Application Diagram PRODUCT PREVIEW Typical USB application utilizing the TPS65030 Power Management Device and TUSB6010. External Host connects to the NOR Interface and System Control Interface. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB6010BZQE, TUSB6010BIZQE 3 TUSB6010BZQE, TUSB6010BIZQE www.ti.com SLLA269 – OCTOBER 2007 3.3 V 1.5 V TUSB6010 1.5 V DP/DM USB 2.0 PHY Macro ID 5V VBus OTG Analog PLL UTMI+ Level3 3.3 V CLKIN 8 bit @ 60 MHz USB 2.0 Dual Role OTG Controller IP Core VBUSP Master & Slave 32/16 bit @ sys_clk USB EP Buffer RAM clk60 (16K x 8) DMA Controller RSTn Power/Reset/Clock Management SLEEP DMAReq [5:0] Central Resource Switch sys_clk (PRCM) CLK 32 bit @ sys_clk PRODUCT PREVIEW GPIO GPIO 1.8 V IO Power Distribution 1.5 V Digital Core Power Distribution DFT & Debug VBUSP2VBUS Slave bridge SCSn VBUSP Slave 32 bit @ sys_clk VBUSP Master 32 bit @ sys_clk ACSn NOR FLASH Interface AddData [15:0] ADVn (Ext Host Interface) Interrupt Controller OEn WEn RDY IO Control INT Figure 1. Device Block Diagram 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TUSB6010BZQE, TUSB6010BIZQE PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TUSB6010BIZQER Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR ZQE 80 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB6010BIZQER BGA MICROSTAR JUNIOR ZQE 80 2500 340.5 333.0 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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