TI TUSB6020ZQE

TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
•
•
USB On-the-Go (OTG) Controller Core
– Use Mentor Graphics USB 2.0 OTG Core
– Dual-Role Controller Can Operate Either as
a Function Controller for a USB Peripheral
or as the Host/Peripheral in Point-to-Point
or Multi-Point Communications With Other
USB Functions
– Compliant With the USB 2.0 Standard for
High-Speed (480-Mbps) Functions and
With the OTG Supplement to the USB 2.0
Specification
– Supports OTG Communications With One
or More High-, Full-, or Low-Speed Devices
– Supports Session Request Protocol (SRP)
and Host Negotiation Protocol (HNP)
– Supports Suspend-and-Resume Signaling
– Configurable for up to 15 Transmit
Endpoints and up to 15 Receive Endpoints
– Configurable FIFOs, Including the Option
of Dynamic FIFO Sizing
– 16k-Byte RAM for USB Endpoint FIFO
Shared by USB In/Out Endpoints
– Support for External Direct Memory
Access (DMA) to FIFOs
– Soft Connect/Disconnect Option
– Performs All Transaction Scheduling in
Hardware
Integrated USB 2.0 OTG PHY
– Fully Compliant With USB 2.0 Standard
and USB 2.0 Transceiver Macrocell
Interface (UTMI) Revision 1.05
– Optimized One-Port Operation at Low
Speed (1.5 Mbps), Full Speed (12 Mbps),
and High Speed (480 Mbps)
– Support for External Charge Pump
– Supports UTMI+3 Level 3 (Host and OTG
Devices, High/Full/Low Speed and
Preamble Packet)
– Protection Circuitry to Withstand Possible
VBUS Short
•
•
•
•
– Use 19.200-MHz, 24.000-MHz, or
48.000-MHz Reference Clock Input as a
Crystal or External Clock Driver
– At-Speed Built-In Self Test (BIST) With
Internal Asynchronous Capability Through
Loopback
– On-Chip Integrated Accurate 45-Ω
High-Speed Termination, 1.5-kΩ Pullup,
and 15-kΩ Pulldown Resistors
– On-Chip Phase-Locked Loop (PLL) to
Reduce Noise on the High-Speed Clocks
– Active Power Consumption Less Than
100 mW
VLYNQ 2.0 Interface to External Host
Controller
– High-Speed (150-MHz) Point-to-Point Serial
Interface for Direct Connection to Other
VLYNQ Interface
– Supports 4X RX and 4X TX Lines
– Memory-Mapped Master/Slave
– Hardware Flow Control Internal Loopback
Mode
– Multichannel DMA Controller
– Integrated List Processor Capable of
Parsing Communications Port
Programming Interface (CPPI)
3.0-Compliant Buffer Descriptors
System Control Module
– Controls Clock and Reset Generation and
Distribution
– Controls and Observes Device Power
States
– Controls Test and Debug Modes
– Supports External Power Management
VBUS Switched Central Resource
– Supports Two VBUSP Master and Three
VBUSP Slave Interfaces
High-Performance 80-Pin
MicroStar BGA™/MicroStar Junior™
ZQE Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar BGA, MicroStar Junior, MicroStar BGA are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
DESCRIPTION/ORDERING INFORMATION
The TUSB6020 is a USB 2.0 high-speed, on-the-go (OTG) dual-role controller designed for a seamless interface
to the VLYNQ serial interface, and is ideal for a wide range of applications. The USB OTG dual-role controller
can operate either as a function controller for a USB peripheral or as the host/peripheral in point-to-point or
multi-point communications with other functions. The integrated USB 2.0 PHY provides one-port operation at low
speed (1.5 Mbps), full speed (12 Mbps), and high speed (480 Mbps). TUSB6020 is configured as an interrupt or
wake-up source, and some GPIOs have secondary functions dedicated to the USB 2.0 operation. The VLYNQ
serial interface is a low pin count, high-speed, point-to-point interface.
The device is fully compliant with Universal Serial Bus Specification Revision 2.0 and On-The-Go Supplement to
the USB Specification Revision 1.2.
The device operates from –40°C to 85°C free air temperature.
ORDERING INFORMATION (1) (2)
TA
0°C to 70°C
(1)
(2)
PACKAGE
MicroStar BGA™ – ZQE
ORDERABLE PART NUMBER
Reel of 360
TUSB6020ZQE
TOP-SIDE MARKING
PREVIEW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
PRODUCT PREVIEW
XI/CLKIN
DPVDM
ID
5 V VBus
3.3 V
1.5 V
3.3 V
1.5 V
USB 2.0
PHY Macro
OTG Analog
PLL
UTMI+ Level 3
BLOCK DIAGRAM
VBUSF
8 bit
@ 60 MHz
USB 2.0 Dual Role OTG
Controller IP Core
USB EP Buffer RAM
(16k x 8)
clk60
RSTn
SLEEP
Master and Slave
32/16 bit @ sys_clk
Power/Reset/Clock
Management
(PRCM)
VBUS
sys_clk
Central
Resource
Switch
Master and Slave
32 bit @ sys_clk
VLYNQ_CLK
VLYNQ
Interface
(Ext Host Interface)
VLYNQ_CRUN
VLYNQ_TX [3:0]
VLYNQ_RXD[3:0]
VBUSP Slave
32 bit @ sys_clk
GPIO
GPIO
DFT and
Debug
VBUSP2VBUS
Slave Bridge
32 bit @ sys_clk
Interrupt
Controller
1.8 V
IO Power
Distribution
1.5 V
2
Digital Core
Power Distribution
IO
Controller
INT
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
TERMINAL FUNCTIONS
TYPE
I/O
RESET
STATE
G2
LVCMOS
O
0
Switch enable for 1.5-V LDO for VBAT/VBUS switch
G3
LVCMOS
O
0
Switch enable for 3.3-V CP for VBAT/VBUS switch
CLKIN
A5
LVCMOS
failsafe
I
In
System clock in. Connect directly to ground if not used.
CPEN
H2
LVCMOS
O
0
5-V charge pump enable
DM
E2
USB
I/O
–
USB differential pair
NAME
NO.
1.5V_SWEN
3.3V_SWEN
DP
DESCRIPTION
D1
LVCMOS
I/O
–
USB differential pair
A8, B7,
B8, B9,
C6, C7,
C8, D6,
D8, E7,
G4, J5
–
–
–
Ground
GPIO0
H4
LVCMOS
I/O
In with pullup
GPIO 0
GPIO1
D5
LVCMOS
I/O
In with pullup
GPIO 1
GPIO2
B6
LVCMOS
I/O
In with pullup
GPIO 2
GPIO3
E6
LVCMOS
I/O
In with pullup
GPIO 3
GPIO4
C4
LVCMOS
I/O
In with pullup
GPIO 4
GPIO5
C9
LVCMOS
I
In with pullup
GPIO 5
GPIO6
F5
LVCMOS
I/O
In with pullup
GPIO 6. Input clock source select at reset. GPIO6 = HIGH,
CLKIN is reference clock. GPIO6 = LOW, XI is reference
clock.
GPIO7
B2
LVCMOS
I/O
In with pullup
GPIO 7. Must be pulled low for proper operation
ID
F2
USB
I
–
Indicates default master for OTG. For more information, see
On-the-Go Supplement to the USB Specification, Revision 1.2
R1
C2
Bias
I
–
High-precision external resistor used for calibration.
(R1 value: 10 K ±1%)
RSTn
H1
LVCMOS
I
In with pullup
RSVD
G5, H5,
J4, F6
–
–
–
Reserved
SLEEP
H3
LVCMOS
O
0
OTG sleep
TEST
D4
LVCMOS
I
–
Test mode. Under normal operation, this signal should be tied
directly to GND.
VBUS
F3
USB
I
–
Charged, discharged, and monitored for OTG host negotiation
protocol and session request protocol. External charge pump
provides up to 100 mA.
VDD15
A1, A9,
B3, C5,
D7, J3
Supply
–
–
Digital core power supply, 1.5 V
VDD18
A7, B5,
E8, J1
Supply
–
–
I/O power supply, 1.8 V
VDDA1P5
E3
Supply
–
–
1.5-V analog supply
VDDA3P3
C1
Supply
–
–
3.3-V analog supply
VDDCM1P5
D2
Supply
–
–
1.5-V PLL supply
VDDD1P5
F1
Supply
–
–
1.5-V digital supply
VDDS3P3
F8, G6,
J9
Supply
–
–
VLYNQ supply, 3.3 V
F9
LVCMOS
I
In with pullup
VLYNQ clock
VLYNQ_CRUN
E9
LVCMOS
open drain
I/O
In with pullup
VLYNQ clock run
VLYNQ_RXD0
H7
LVCMOS
I
In with pullup
VLYNQ receive data bit 0
VLYNQ_RXD1
J7
LVCMOS
I
In with pullup
VLYNQ receive data bit 1
GND
VLYNQ_CLK
PRODUCT PREVIEW
TERMINAL
Reset active low
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
TYPE
I/O
RESET
STATE
H6
LVCMOS
I
In with pullup
VLYNQ receive data bit 2
J6
LVCMOS
I
In with pullup
VLYNQ receive data bit 3
VLYNQ_TXD0
H9
LVCMOS
O
In with pullup
VLYNQ transmit data bit 0
VLYNQ_TXD1
G9
LVCMOS
O
In with pullup
VLYNQ transmit data bit 1
VLYNQ_TXD2
H8
LVCMOS
O
In with pullup
VLYNQ transmit data bit 2
VLYNQ_TXD3
F7
LVCMOS
O
In with pullup
VLYNQ transmit data bit 3. Ground. 1.5-V analog ground.
3.3-V analog ground. 1.5-V PLL ground. 1.5-V digital ground.
Ground reference for the reference circuits. Crystal input.
Should be left unconnected if not used. Crystal output.
A2, A6,
B4, D9,
E5, G1,
G7, G8,
J2, J8
Supply
–
–
Ground
VSSA1P5
E1
Supply
–
–
1.5-V analog ground
VSSA3P3
E4
Supply
–
–
3.3-V analog ground
VSSCM1P5
D3
Supply
–
–
1.5-V PLL ground
VSSD1P5
F4
Supply
–
–
1.5-V digital ground
VSSREF
B1
Supply
–
–
Ground reference for the reference circuits
XI
A4
Crystal
I
In
Crystal input. Should be left unconnected if not used.
XO
A3
Crystal
O
In
Crystal output. Should be left unconnected if not used.
NAME
NO.
VLYNQ_RXD2
VLYNQ_RXD3
VSS
PRODUCT PREVIEW
4
DESCRIPTION
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VDDS
Supply voltage
VI
Input voltage range
VO
Output voltage range
VDD
Core supply voltage
IIK
Input clamp current
IOK
Output clamp current
Tstg
Storage temperature range
(1)
MIN
MAX
–0.5
4.2
V
3.3-V LVCMOS
–0.5
VDDS +0.5
V
3.3-V LVCMOS
–0.5
VDDS +0.5
–0.5
2.1
mA
±20
mA
±20
mA
150
°C
–65
UNIT
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
3
3.3
3.6
mA
1.35
1.5
1.65
mA
VDDS
Supply voltage
VDD
Core supply voltage
VI
Input voltage range
LVCMOS – VLYNQ interface
0
VDDS
V
VO
Output voltage range
LVCMOS – VLYNQ interface
0
VDDS
V
VIH
High-level input voltage
LVCMOS – VLYNQ interface
0.7 × VDDS
VIL
Low-level input voltage
LVCMOS – VLYNQ interface
0
0.3 × VDDS
μA
TA
Operating temperature
0
70
μA
TJ
Operating junction temperature range
0
(1)
PRODUCT PREVIEW
PARAMETER
(1)
V
μA
Applies to both digital core supply voltage, DVDD, and analog supply voltage, AVDD.
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
TUSB6020 VLYNQ IINTERFACE
Electrical Characteristics
TJ = 25°C, VDD = 1.5 V ±5%, VDDS = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOL
Low-level input current
LVCMOS
VDDS = 3.3 V, VDD = 1.5 V
8
mA
IOH
High-level input current
LVCMOS
VDDS = 3.3 V, VDD = 1.5 V
–8
mA
IO = –100 μA
VDDS – 0.2
IO = IOH
0.8 × VDDS
VOH
High-level output voltage LVCMOS
V
VOL
Low-level output voltage
LVCMOS
Vhys
Hysteresis
LVCMOS
VI = VIH
IIH
High-level input current
Receiver only
VI = VI max
±1
μA
IIL
Low-level input current
Receiver only
VI = VI min
±1
μA
IOZ
Output leakage current
(Hi-Z)
Driver only
Driver disabled
±20
μA
MAX
UNIT
IO = 100 μA
0.2
0.22 × VDDS
IO = IOL
0.13 × VDDS
V
V
Electrical Characteristics
PRODUCT PREVIEW
TJ = 25°C, VDD = 1.5 V ±5%, VDDS = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Driver Characteristics
tr
tf
6
Rise time
(time between 10% and 90% swing of
3.3 V)
Fall time
(time between 90% and 10% swing of
3.3 V)
Load: CL = 10 pF
1.68
Load: CL = 50 pF
6.56
Load: CL = 125 pF
15.78
Load: CL = 5 pF
2.09
Load: CL = 5 pF
8.19
Load: CL = 15 pF
19.75
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ns
ns
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
SCPS170C – JANUARY 2007 – REVISED JULY 2007
APPLICATION INFORMATION
Power-Sequencing Guidelines
During powerup, the USB 2.0 OTG PHY macro is not suspended, and the 60-MHz system clock is enabled and
free running.
• The reference clock input is selected between CLKIN and XI based on the sense-on-reset.
• The default system clock is a device reference clock input (CLKIN or XI, depending on sampling GPIO6
during power-up).
• The digital core and PHY reset are synchronized to the system clock.
The Mentor Graphics MUSBMHDRC USB 2.0 dual-role controller powers up as a type-B device (B-Device bit in
the DevCtl register is set), and the OTG session is not enabled (session bit in the DevCtl register is set to 0).
With the session not started, all of the MUSBMHDRC finite state machines are in the idle state.
The TUSB6020 controller is in the normal state.
After the reset ID is deasserted, the device asserts the DevReady interrupt to the external host.
The external host enables IDpullup and the VBUS sense comparator. It reads the Device Status register to
confirm the USB cable connection.
• If no USB cable in attached, IDpullup should be high and VBUS should be low.
• If the type-B USB connector is attached, IDpullup should be high. The VBUS status depends on whether the
type-A device on the other side of the cable is charging VBUS.
• If the type-A USB connector is attached, IDpullup should be low and VBUS should be low. The external host
decides when to charge VBUS.
The external host may decide to place the device into idle state if:
• No USB cable is attached.
• The type-B connector is attached but the type-A device did not charge VBUS.
• The type-A connector is attached but the external host may decide to wait for an SRP request from the
type-B device.
The external host configures wake-up sources before setting the Idle bit. It does the following:
• Enables the IDpullup wake-up source
• Enables the VBUS Sense wake-up source
• Enables the USB resume (LineState) wake-up source
• Enables the external host (NOR FLASH/VLYNQ) wake-up source
• Enables wake-up interrupts
The external host sets the Idle bit. The device starts the transition to the idle state. During transitions from the
normal to the idle state, the device ignores all wake-up events. The device can respond to wake-up events only
when in the idle state.
In the idle state, the device asserts the SLEEP output pin to the companion power-management device to place
it into low power/sleep mode if the PmIdle and DevIdle bits are set in the PRCM Power Management register. In
sleep state, the companion power-management device provides 100 A maximum per power rail (1.5 V and
3.3 V). The power-management device can be put into the sleep state only if the device is placed in the idle
state (DevIdle bit set).
If the application requires the companion power management device to remain in the normal state, the PmIdle
bit will not be set, while the DevIdle bit can be set to place the device into the idle state.
Figure 1 illustrates the power-up sequence.
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PRODUCT PREVIEW
The external host responds to the interrupt. It reads the interrupt status register and decides how to proceed
based on the device’s current status.
TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Vbat
Ext. Pwr. Mgmt: Vio (1.8 V)
TUSB6020: IO Interface Status
TUSB6020: GPIO7 (Host Mode
Select) TPS65030: TEST
IO INTERFACE IS INITIALIZED
IO INTERFACE IS NOT INITIALIZED
Pulled up by TUSB6020 GPIO7 internal pullup resistor (NOR FLASH Mode is selected)
TUSB6020: GPIO6
(Reference Clock Select)
Pulled up by TUSB6020 GPIO6 internal pullup resistor (CLKIN is selected reference clock source)
Ext. Host GPIOn configured as output
Pulled down by Host Processor
internal pulldown resistor
Ext. Host GPIOn
enabled by SW
Ext Host: GPIOn
TPS65030: EN2 (3.3 V, 1.5 V)
TUSB6020: CPEN
TPS65030: EN1 (5 V)
TUSB6020: SWEN
TPS65030: SW_EN (Vbat/Vbus)
TPS65030: Pgood
TUSB6020: RSTn
Pulled high by TUSB6020
internal pullup
TPS65030: Vout3 (1.5 V)
TPS65030: Vout2 (3.3 V)
PRODUCT PREVIEW
TUSB6020: INT
Ext Host: ExtInt/GPIOn
TUSB6020 sets INT low to
indicate device is reday
NOTE: Host mode and reference clock source selection is latched on RSTn rising edge. No external components are required to select NOR flash host mode
and CLKIN as a reference clock source.
Signal state cannot be ensured.
Signal state is stable and valid.
Figure 1. System Power-Up Sequence
DEVICE PEAK POWER CONSUMPTION ESTIMATE
POWER SUPPLY
1.5 V
1.8 V
3.3 V
(1)
RESET STATE
NORMAL STATE
25 mA
110 mA
25 mA if XI is used as reference clock source
18 mA if CLKIN is used as reference clock source
10 mA
60 mA
80 μA
22 mA
In the idle state, device power consumption, including the companion power-management device (TPS65030), should not exceed
100 μA.
INPUT CLOCK REQUIREMENTS
PARAMETER
8
IDLE (1)
VALUE
Normal clock frequency
19.200, 24.000, or 48.000 MHz
Frequency accuracy
±100 ppm
Minimum rise/fall time
5 ns (10% to 90%)
Voltage level
1.8 V
Input clock type
Square wave
Duty cycle
40% to 60%
Input capacitance loading
4 pF
Jitter
–95 dBc at 1 MHz
–120 dBc at 100 MHz
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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
www.ti.com
SCPS170C – JANUARY 2007 – REVISED JULY 2007
CRYSTAL REQUIREMENTS
Frequency
The required frequency of oscillation for the crystal can be 19.200, 24.000, or 48.000 MHz.
Frequency Tolerances
Frequency tolerance is the maximum allowable deviation from the nominal crystal frequency at a specified
temperature, usually 25°C. The recommended frequency tolerance of the crystal over the manufacturing process
is ±50 ppm. The maximum acceptable frequency tolerance of the crystal over the manufacturing process is
±100 ppm.
NOTE
The total system frequency tolerance from the crystal, the load capacitors, the
capacitive load of the board, the capacitive load of the device pins, the variation over
temperature, the variation with age, and the circuitry of the PHY must be less than
±500 ppm. Consequently, the individual tolerance for the crystal must be ≤ ±100 ppm.
The oscillator of the USB device may have difficulty driving a large load capacitance, so crystals that specify
large load capacitances should be avoided. For more information on crystal requirements, see the following
application report from TI: Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices
(literature number SLLA122).
Mechanical Characteristics
The TUSB6020 controller uses an 80-pin MicroStar BGA™ package. The lead-free solder ball composition is
Sn/Ag1.2Cu0.5 (proportions by weight). The substrate plating on the die side where the die bonds to is NiAu.
The substrate finish on the bottom side where the solder balls attach to is bare Cu.
Reflow Conditions
MicroStar BGA™/MicroStarJunior™
Recommended Lead Free Reflow Profile
In the case of Sn/Ag/Cu solder paste
(°C)
Peak temperature
260°C max
260
235
225
200
30 – 60 s
150
90 ± 30 s
1–5 °C/sec
Reflow temperature is defined at package top.
Time
Figure 2. Reflow Conditons
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PRODUCT PREVIEW
Load Capacitance
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
TUSB6020ZQE
PREVIEW
Package
Type
BGA MI
CROSTA
R JUNI
OR
Package
Drawing
ZQE
Pins Package Eco Plan (2)
Qty
80
360
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
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