ADS5444 www.ti.com SLWS162 – AUGUST 2005 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER • FEATURES 13-Bit Resolution 250 MSPS Sample Rate SNR = 68.7 dBc at 100-MHz IF and 250 MSPS SFDR = 71 dBc at 100-MHz IF and 250 MSPS SNR = 67.6 dBc at 230-MHz IF and 250 MSPS SFDR = 78 dBc at 230-MHz IF and 250 MSPS 2.2 VPP Differential Input Voltage Fully Buffered Analog Inputs 5 V Analog Supply Voltage 3.3 V LVDS Compatible Outputs Total Power Dissipation: 2.1 W 2's Complement Output Format TQFP-80 PowerPAD™ Package Industrial Temperature Range = –40°C to 85°C APPLICATIONS • • • • • Test and Measurement Software-Defined Radio Multi-channel Basestation Receivers Basestation TX Digital Predistortion Communications Instrumentation RELATED PRODUCTS • • • ADS5424 - 14-bit, 105 MSPS ADS5423 - 14-bit, 80 MSPS ADS5440 - 13-bit, 210 MSPS DESCRIPTION The ADS5444 is a 13-bit 250 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5444 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over input frequency. AVDD AIN AIN A1 TH1 + TH2 Σ A2 + TH3 ADC1 DAC1 Reference A3 ADC3 − − VREF Σ DVDD ADC2 5 DAC2 5 5 Digital Error Correction CLK CLK Timing OVR OVR DRY DRY D[12:0] GND B0061-01 The ADS5444 is available in an 80-pin TQFP PowerPAD™ package. The ADS5444 is built on state of the art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial temperature range (–40°C to 85°C). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • • • • • • • • • • • • • ADS5444 www.ti.com SLWS162 – AUGUST 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION (1) Product ADS5444 (1) (2) PackageLead Package Designator HTQFP-80 (2) PowerPAD (1) PFP Specified Temperature Range Package Marking –40°C to 85°C ADS5444I Ordering Number Transport Media, Quantity ADS5444IPFP Tray, 96 ADS5444IPFPR Tape and Reel, 1000 For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. Thermal pad size: 6 x 6 array of thermal vias with a maximum thermal pad size of 10 mm x 10 mm ABSOLUTE MAXIMUM RATINGS PRODUCT PREVIEW over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT Supply voltage AVDD to GND 6V DRVDD to GND 5V Analog input to GND –0.3 V to AVDD+0.3 V Clock input to GND –0.3 V to AVDD+0.3 V CLK to CLK ±2.5 Digital data output to GND –0.3 V to DRVDD+0.3 V Operating temperature range –40°C to 85°C Maximum junction temperature 150°C Storage temperature range (1) –65°C to 150°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. THERMAL CHARACTERISTICS (1) PARAMETER θJA θJC (1) 2 TYP UNIT Soldered slug, no airflow TEST CONDITIONS 21.7 °C/W Soldered slug, 250-LFPM airflow 15.4 °C/W 50 °C/W Unsoldered slug, 250-LFPM airflow 43.4 °C/W Bottom of package (heatslug) 2.99 °C/W Unsoldered slug, no airflow Using 36 thermal vias (6 x 6 array). See the Application Section. ADS5444 www.ti.com SLWS162 – AUGUST 2005 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT 4.75 5 5.25 V 3 3.3 3.6 V SUPPLIES AVDD Analog supply voltage DRVDD Output driver supply voltage ANALOG INPUT VCM Differential input range 2.2 VPP Input common mode 2.4 V CLOCK INPUT 1/tC ADCLK input sample rate (sine wave) 250 Clock amplitude, differential sine wave Clock duty cycle TA MSPS 3 Vpp 50% Open free air temperature –40 °C 85 ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN Resolution TYP MAX PRODUCT PREVIEW MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise noted UNIT 13 Bits 2.2 Vpp 1 kΩ ANALOG INPUTS Differential input range Differential input resistance (DC) Differential input capacitance 1.5 Analog input bandwidth pF 1000 MHz INTERNAL REFERENCE VOLTAGE VREF Reference voltage 2.4 V DYNAMIC ACCURACY No missing codes Tested DNL Differential linearity error fIN = 10 MHz INL Integral linearity error fIN = 10 MHz Offset error ±0.9 LSB ±1.5 –5 LSB 5 Offset temperature coefficient mV mV/°C Gain error –5 5 %FS Gain temperature coefficient ∆%/°C PSRR mV/V POWER SUPPLY IAVDD Analog supply current IDRVDD Output buffer supply current 365 mA 76 mA Power dissipation 2.1 W Power-up time 20 ms VIN = full scale, fIN = 70 MHz, FS = 250 MSPS DYNAMIC AC CHARACTERISTICS SNR Signal-to-noise ratio fIN = 10 MHz 69.1 fIN = 70 MHz 68.9 fIN = 100 MHz 68.7 fIN = 170 MHz 68.1 fIN = 230 MHz 67.6 fIN = 300 MHz 66.8 fIN = 400 MHz 66.0 dBc 3 ADS5444 www.ti.com SLWS162 – AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise noted PARAMETER SFDR HD2 PRODUCT PREVIEW HD3 Spurious free dynamic range Second harmonic Third harmonic Worst other harmonic/spur (other than HD2 and HD3) TEST CONDITIONS MIN fIN = 10 MHz 83 fIN = 70 MHz 77 fIN = 100 MHz 71 fIN = 170 MHz 73 fIN = 230 MHz 78 fIN = 300 MHz 70 fIN = 400 MHz 63 fIN = 10 MHz 88 fIN = 70 MHz 82 fIN = 100 MHz 78 fIN = 170 MHz 75 fIN = 230 MHz 78 fIN = 300 MHz 70 fIN = 400 MHz 63 fIN = 10 MHz 83 fIN = 70 MHz 79 fIN = 100 MHz 72 fIN = 170 MHz 76 fIN = 230 MHz 90 fIN = 300 MHz 81 fIN = 400 MHz 68 fIN = 10 MHz 95 fIN = 70 MHz 92 fIN = 100 MHz 83 fIN = 170 MHz 88 fIN = 230 MHz 89 fIN = 300 MHz 87 fIN = 400 MHz SINAD ENOB TYP MAX UNIT dBc dBc dBc dBc 76 fIN = 10 MHz 68.8 fIN = 70 MHz 68.1 fIN = 100 MHz 66.2 fIN = 170 MHz 66.4 fIN = 230 MHz 67.1 fIN = 300 MHz 64.8 fIN = 400 MHz 60.2 dBc Effective number of bits fIN = 70 MHz 11 Bits RMS idle channel noise Inputs tied to common-mode 0.4 LSB DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS Differential output voltage Output offset voltage 4 0.35 1.125 V 1.375 V ADS5444 www.ti.com SLWS162 – AUGUST 2005 TIMING CHARACTERISTICS tA N+3 N AIN N+1 N+2 tCLK tCLKH N N+1 N+2 N+3 tC_DR D[12:0], OVR, OVR N−3 tr N−2 tf N+4 tsu_c N−1 tsu_DR th_c N th_D R PRODUCT PREVIEW CLK, CLK N+4 tCLKL DRY, DRY tDR T0073-01 Figure 1. Timing Diagram TIMING CHARACTERISTICS over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V PARAMETER tA Aperture delay tJ Clock slope independent Aperture uncertainty (jitter) kJ Clock slope jitter factor dependency TEST CONDITIONS MIN TYP MAX UNIT ps fs s/V Latency 4 cycles Clock Input tCLK Clock period 4.0 ns tCLKH Clock pulsewidth high 2.0 ns tCLKL Clock pulsewidth low 2.0 ns 2.08 ns 4.08 ns Clock to DataReady (DRY) tDR Clock rising to DataReady falling tC_DR Clock rising to DataReady rising Clock to DATA, Clock duty cycle = 50% (1) OVR (2) tr Data VOL to Data VOH (rise time) 0.8 ns tf Data VOH to Data VOL (fall time) 0.8 ns tsu_c Data valid to clock (setup time) 2.4 ns th_c Clock to invalid Data (hold time) 5.5 ns DataReady (DRY)/DATA, OVR (2) tsu_DR) Data valid to DRY 1.7 ns th_DR) DRY to invalid Data 1.4 ns (1) (2) tC_DR = tDR + tCLKH for clock duty cycles other than 50% Data is updated with clock rising edge or DRY falling edge. 5 ADS5444 www.ti.com SLWS162 – AUGUST 2005 DEVICE INFORMATION PFP PACKAGE (TOP VIEW) D5 D5 D6 D6 GND DVDD D7 D7 D8 D8 D9 D9 D10 D10 D11 D11 D12 D12 DRY DRY 61 39 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 4 5 6 GND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D4 D4 D3 D3 D2 D2 D1 D1 GND DVDD D0 D0 NC NC NC NC NC NC OVR OVR GND AVDD GND AVDD GND AVDD GND NC GND AVDD GND NC GND AVDD GND AVDD GND AVDD GND AVDD PRODUCT PREVIEW DVDD GND AVDD NC NC VREF GND AVDD GND CLK CLK GND AVDD AVDD GND AIN AIN GND AVDD GND TERMINAL FUNCTIONS TERMINAL NAME AVDD DVDD GND NO. DESCRIPTION 3, 8, 13, 14, 19, 21, 23, 25, 27, 31, 35, 37, Analog power supply 39 1, 51, 66 Output driver power supply 2, 7, 9, 12, 15, 18, 20, 22, 24, 26, 28, 30, 32, Ground 34, 36, 38, 40, 52, 65 VREF 6 Reference voltage CLK 10 Differential input clock (positive). Conversion initiated on rising edge CLK 11 Differential input clock (negative) AIN 16 Differential input signal (positive) AIN 17 Differential input signal (negative) OVR, OVR 6 42, 41 Over range indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. ADS5444 www.ti.com SLWS162 – AUGUST 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL DESCRIPTION NAME NO. D0, D0 50, 49 LVDS digital output pair, least-significant bit (LSB) D1–D6, D1–D6 53–64 LVDS digital output pairs D7–D11, D7–D11 67–76 LVDS digital output pairs D12, D12 78, 77 LVDS digital output pair, most-significant bit (MSB) 80, 79 Data ready LVDS output pair DRY, DRY NC 4, 5, 29, 33, 43–48 No connect DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSB. Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a least squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best fit line, measured in units of LSB. Gain Error The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN– TMAX. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first five harmonics. (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale input amplitude. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). 7 PRODUCT PREVIEW Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. ADS5444 www.ti.com SLWS162 – AUGUST 2005 DEFINITION OF SPECIFICATIONS (continued) (3) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1– f2 or 2f2– f1). IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. PRODUCT PREVIEW 8 ADS5444 www.ti.com SLWS162 – AUGUST 2005 TYPICAL CHARACTERISTICS TA =25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 250 MSPS, 3VPP sinusoidal clock, 50% duty cycle, unless otherwise noted Spectral Performance (FFT For 10-MHz Input Signal) Spectral Performance (FFT For 100-MHz Input Signal) 0 0 SFDR = 83.5 dBc SNR = 69.2 dBc THD = 81.9 dBc SINAD = 69 dBc −40 −20 Amplitude − dB −60 −80 −100 −40 −60 −80 −100 −120 −120 0 10 20 30 40 50 60 70 80 90 100 110 120 0 f − Frequency − MHz 10 20 30 40 50 60 70 80 90 100 110 120 f − Frequency − MHz Figure 2. Figure 3. Spectral Performance (FFT For 230-MHz Input Signal) Spectral Performance (FFT For 300-MHz Input Signal) 0 0 SFDR = 78.4 dBc SNR = 67.5 dBc THD = 77.6 dBc SINAD = 67.1 dBc −20 −40 −60 −80 −100 SFDR = 69.9 dBc SNR = 66.8 dBc THD = 69.4 dBc SINAD = 64.9 dBc −20 Amplitude − dB Amplitude − dB PRODUCT PREVIEW Amplitude − dB −20 SFDR = 70.8 dBc SNR = 68.8 dBc THD = 69.5 dBc SINAD = 66.2 dBc −40 −60 −80 −100 −120 −120 0 10 20 30 40 50 60 70 80 90 100 110 120 f − Frequency − MHz Figure 4. 0 10 20 30 40 50 60 70 80 90 100 110 120 f − Frequency − MHz Figure 5. 9 ADS5444 www.ti.com SLWS162 – AUGUST 2005 APPLICATION INFORMATION Theory of Operation The ADS5444 is a 13 bit, 250 MSPS, monolithic pipeline analog to digital converter. Its bipolar analog core operates from a 5 V supply, while the output uses a 3.3 V supply to provide LVDS compatible outputs. The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of four clock cycles, after which the output data is available as a 13 bit parallel word, coded in binary two's complement format. Input Configuration The analog input for the ADS5444 consists of an analog differential buffer followed by a bipolar track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is set internally through a 500 Ω resistor connected from 2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ. PRODUCT PREVIEW For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings symmetrically between 2.4 +0.55 V and 2.4 -0.55 V. This means that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating the need for any external circuitry for this purpose. The ADS5444 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 6 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is shown in Figure 7). R0 50 Z0 50 AIN 1:1 R 50 AC S ignal Source ADS5444 AIN AD T 1−1W T Figure 6. Converting a Single-Ended Input to a Differential Signal Using RF Transformers 5V VIN −5 V RS 100 Ω + OPA695 − 0.1 µF 1000 µF RIN 1:1 RT 100 Ω RIN AIN CIN ADS5444 AIN R1 400 Ω R2 57.5 Ω AV = 8V/V (18 dB) Figure 7. Using the OPA695 With the ADS5444 Besides the OPA695, Texas Instruments offers a wide selection of single-ended operational amplifiers (including 10 ADS5444 www.ti.com SLWS162 – AUGUST 2005 Application Information (continued) the THS3201, THS3202 and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as Texas Instrument's THS9001, can also be used with an RF transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like the THS4509 (see Figure 8) is a good solution as it minimizes board space and reduces the number of components. In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5444. The 225 Ω resistors and 2.7 pF capacitor between the THS4509 outputs and ADS5444 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (-3 dB). Input termination is accomplished via the 69.8 Ω resistor and 0.22 µF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22 µF capacitor and 49.9 Ω resistor is inserted to ground across the 69.8 Ω resistor and 0.22 µF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348 Ω feedback resistor. See the THS4509 data sheet for further component values to set proper 50 Ω termination for other common gains. From VIN 50 Ω Source 100 Ω 69.8 Ω 348 Ω 13-Bit 210 MSPS +5V 225 Ω 0.22 µF AIN 2.7 pF 100 Ω PRODUCT PREVIEW Since the ADS5444 recommended input common-mode voltage is +2.4 V, the THS4509 is operated from a single power supply input with VS+ = +5 V and VS- = 0 V (ground). This maintains maximum headroom on the internal transistors of the THS4509. ADS5444 225 Ω THS4509 AIN VREF CM 49.9 Ω 0.22 µF 69.8 Ω 49.9 Ω 0.22 µF 0.1 µF 0.1 µF 348 Ω Figure 8. Using the THS4509 With the ADS5444 Clock Inputs The ADS5444 clock input can be driven with either a differential or a single-ended clock input, with little or no difference in performance between the two configurations. In low input frequency applications, where jitter may not be a big concern, the use of a single-ended clock (see Figure 9) could save some cost and board space without any trade-off in performance. When driven in this configuration, it is best to connect CLK to ground with a 0.01 µF capacitor, while CLK is ac-coupled with a 0.01 µF capacitor to the clock source, as shown in Figure 9. Square Wave or Sine Wave CLK 0.01 µF ADS5444 CLK 0.01 µF Figure 9. Single-Ended Clock 11 ADS5444 www.ti.com SLWS162 – AUGUST 2005 Application Information (continued) 0.1 µF Clock Source 1:4 CLK MA3X71600LCT−ND ADS5444 CLK Figure 10. Differential Clock Nevertheless, for jitter sensitive applications, the use of a differential clock has some advantages (as with any other ADCs). The first advantage is that it allows for common-mode noise rejection at the PCB level. A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise on jitter. See Clocking High Speed Data Converters (SLYT075) for more detail. Figure 10 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in cases where this would exceed the absolute maximum ratings, even when using a differential clock. PRODUCT PREVIEW 100 nF MC100EP16DT 100 nF D D CLK Q VBB Q 499 100 nF 100 nF ADS5444 CLK 499 50 Ω 50 Ω 100 nF 113 Ω Figure 11. Differential Clock Using PECL Logic Another possibility is the use of a logic based clock, such as PECL. In this case, the slew rate of the edges will most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a sinusoidal clock may not produce the best results as logic gates may not have been optimized to act as comparators, adding too much jitter while squaring the inputs. The common-mode voltage of the clock inputs is set internally to 2.4 V using 1 kΩ resistors. It is recommended to use an ac coupling, but if for any reason, this scheme is not possible, due to, for instance, asynchronous clocking, the ADS5444 presents a good tolerance to clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty cycle clock signal should be provided. Digital Outputs The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal (DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits. The output format is binary two's complement. The ADS5444 digital outputs are LVDS compatible. 12 www.ti.com ADS5444 SLWS162 – AUGUST 2005 Application Information (continued) Power Supplies The use of low noise power supplies with adequate decoupling is recommended. Linear supplies are the preferred choice versus switched ones, which tend to generate more noise components that can be coupled to the ADS5444. The ADS5444 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the digital outputs supply (DRVDD) we recommend the use of 3.3 V. All the ground pins are marked as GND, although AGND pins and DRGND pins are not tied together inside the package. Layout Information Besides performance oriented rules, special care has to be taken when considering the heat dissipation out of the device. The thermal heat sink should be soldered to the board as described in the PowerPad Package section. PowerPAD PACKAGE The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heatsink. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical Data section. 2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The small size prevents wicking of the solder through the holes. 3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the thermal pad area to provide an additional heat path. 4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the SLMA004 Application Brief PowerPAD Made Easy or the SLMA002 Technical Brief PowerPAD Thermally Enhanced Package. 13 PRODUCT PREVIEW The evaluation board represents a good guideline of how to layout the board to obtain the maximum performance out of the ADS5444. General design rules as the use of multilayer boards, single ground plane for ADC ground connections and local decoupling ceramic chip capacitors should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications where low jitter is required as high IF sampling. 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