Isolated Sigma-Delta Modulator AD7400A Preliminary Technical Data FEATURES GENERAL DESCRIPTION 10 MHz clock rate Second-order modulator 16 bits no missing codes ±2 LSB INL typical at 16 bits 3.5 µV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 18 mA maximum at 5.25 V −40°C to +125°C operating range 16-lead SOIC, 8-lead gull-wing surface mount DIP packages AD7401A, external clock version Safety and regulatory approvals UL recognition 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 891 V peak The AD7400A1 is a second-order, Σ-Δ modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc. iCoupler® technology. The AD7400A operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed CMOS, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. The part contains an on-chip reference. The AD7400A is offered in a 16-lead SOIC and 8-lead gull-wing surface mount DIP and has an operating temperature range of −40°C to +125°C. APPLICATIONS AC motor controls Data acquisition systems A/D + opto-isolator replacements FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7400A VIN+ T/H Σ-∆ ADC UPDATE ENCODE BUF REF CONTROL LOGIC UPDATE ENCODE WATCHDOG DECODE MDAT WATCHDOG MCLKOUT DECODE GND2 GND1 04718-001 VIN– Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD7400A Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications....................................................................................... 1 Terminology .................................................................................... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Circuit Information.................................................................... 13 Revision History ............................................................................... 2 Analog Input ............................................................................... 13 Specifications..................................................................................... 3 Differential Inputs ...................................................................... 14 Timing Specifications .................................................................. 4 Digital Filter ................................................................................ 14 Insulation and Safety-Related Specifications............................ 5 Application Information................................................................ 17 Regulatory Information............................................................... 5 Grounding and Layout .............................................................. 17 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics .............................................................................. 6 Evaluating the AD7400A Performance ................................... 17 Absolute Maximum Ratings............................................................ 7 Outline Dimensions ....................................................................... 18 ESD Caution.................................................................................. 7 Ordering Guide ....................... Error! Bookmark not defined. Insulation Lifetime ..................................................................... 17 Pin Configuration and Function Descriptions............................. 8 REVISION HISTORY Rev. PrA | Page 2 of 19 Preliminary Technical Data AD7400A SPECIFICATIONS VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = −200V to +200mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX, fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.1 Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Offset Drift vs. Temperature3 Offset Drift vs. VDD1 Gain Error3 Gain Error Drift vs. Temperature3 Gain Error Drift vs. VDD13 ANALOG INPUT Input Voltage Range Dynamic Input Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-(Noise + Distortion) Ratio (SINAD)3 Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Effective Number of Bits (ENOB)3 Isolation Transient Immunity3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS VDD1 VDD2 IDD14 IDD25 Y Version1, 2 Unit Test Conditions/Comments 16 ±15 ±25 ±0.9 ±0.5 ±50 3.5 1 120 ±1 23 110 Bits min LSB max LSB max LSB max mV max µV typ µV/°C max µV/°C typ µV/V typ mV max µV/°C typ µV/V typ Filter output truncated to 16 bits −40°C to +85°C; ±2 LSB typical >85°C to 105°C Guaranteed no missing codes to 16 bits ±200 ±7 ±0.5 10 mV min/mV max µA max µA typ pF typ For specified performance; full range ±320 mV VIN+ = 400 mV, VIN− = 0 V VIN+ = VIN− = 0 V 70 65 79 71 −88 −88 11.5 25 30 dB min dB min dB typ dB min dB typ dB typ Bits kV/µs min kV/µs typ VDD2 − 0.1 0.4 V min V max IO = −200 µA IO = +200 µA 4.5/5.25 3/5.5 12 6 4 V min/V max V min/V max mA max mA max mA max VDD1 = 5.25 V VDD2 = 5.5 V VDD2 = 3.3 V 1 Temperature range is −40°C to +125°C except where specified. All voltages are relative to their respective ground. See the Terminology section. 4 See Figure 15. 5 See Figure 16. 2 3 Rev. PrA | Page 3 of 19 TA = 25°C −40°C to +105°C −40°C to +105°C VIN+ = 35 Hz, 400 mV p-p sine −40°C to +85°C >85°C to 105°C −40°C to +105°C AD7400A Preliminary Technical Data TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1 Table 2. Parameter fMCLKOUT2 t13 t23 t3 t4 Limit at TMIN, TMAX 10 9/11 40 10 0.4 × tMCLKOUT 0.4 × tMCLKOUT Unit MHz typ MHz min/MHz max ns max ns min ns min ns min Description Master clock output frequency Master clock output frequency Data access time after MCLK rising edge Data hold time after MCLK rising edge Master clock low time Master clock high time 1 Sample tested during initial release to ensure compliance. Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 2 200µA +1.6V CL 25pF 200µA 04718-002 TO OUTPUT PIN IOL IOH Figure 2. Load Circuit for Digital Output Timing Specifications t4 t1 t2 MDAT Figure 3. Data Timing Rev. PrA | Page 4 of 19 t3 04718-003 MCLKOUT Preliminary Technical Data AD7400A INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Input-to-Output Withstand Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 3750 min 7.46 min Unit V mm Minimum External Tracking (Creepage) L(I02) 8.1 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110, 1/89, Table 1) REGULATORY INFORMATION Table 4. UL1 Recognized Under 1577 Component Recognition Program1 3750 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 630 Vrms maximum working voltage File 205078 VDE2 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012 Basic insulation, 891 V peak Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 Reinforced insulation, 891 V peak File 2471900-4880-0001 In accordance with UL 1577, each AD7400A is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 7.5 µA). In accordance with DIN EN 60747-5-2, each AD7400A is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection limit = 5 pC). Rev. PrA | Page 5 of 19 AD7400A Preliminary Technical Data DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, Table 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature Side 1 Current Side 2 Current INSULATION RESISTANCE AT TS, VIO = 500 V 250 SIDE #2 200 150 SIDE #1 100 50 50 100 150 CASE TEMPERATURE (°C) 200 04718-026 SAFETY-LIMITING CURRENT (mA) 300 0 Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. PrA | Page 6 of 19 Characteristic Unit VIORM I–IV I–II I–II 40/105/21 2 891 V peak 1671 V peak 1426 V peak 1069 V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VPR 350 0 Symbol Preliminary Technical Data AD7400A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 6. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature SOIC Package θJA Thermal Impedance θJC Thermal Impedance Resistance (Input-to-Output), RI-O Capacitance (Input-to-Output), CI-O2 Pb-Free Temperature, Soldering Reflow ESD 1 2 Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VDD1 + 0.3 V −0.3 V to VDD2 + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C 89.2°C/W 55.6°C/W 1012 Ω 1.7 pF typ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 260 (+0)°C 1.5 kV Transient currents of up to 100 mA do not cause SCR to latch up. f = 1 MHz. Max 565 Unit VPK Constraint 50-year minimum lifetime 891 VPK 891 V Maximum CSA/VDE approved working voltage Maximum CSA/VDE approved working voltage Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Rev. PrA | Page 7 of 19 AD7400A Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 VIN+ 2 16 GND2 AD7400A 15 NC VIN– 3 TOP VIEW 14 VDD2 (Not to Scale) 13 MCLKOUT NC 4 NC 5 12 NC NC 6 11 MDAT GND1 8 1 VIN+ 2 VIN- 3 GND1 4 AD7400A 8 VDD2 7 MCLKIN TOP VIEW 6 MDAT (Not to Scale) 5 GND2 NC = NO CONNECT Figure 6 Pin Configuration (NS-8) 10 NC 9 GND2 NC = NO CONNECT 04718-004 VDD1 7 VDD1 Figure 5. Pin Configuration (RW-16) Table 8. Pin Function Descriptions Mnemonic VDD1 VIN+ VIN− NC GND1 GND2 MDAT MCLKOUT VDD2 Description Supply Voltage, 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7400A and is relative to GND1. Positive Analog Input. Specified range of ±200 mV. Negative Analog Input. Normally connected to GND1. No Connect. Ground 1. This is the ground reference point for all circuitry on the isolated side. Ground 2. This is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKOUT output and valid on the following MCLKOUT rising edge. Master Clock Logic Output. 10 MHz typical. The bit stream from the modulator is valid on the rising edge of MCLKOUT. Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Rev. PrA | Page 8 of 19 Preliminary Technical Data AD7400A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using 20 kHz brickwall filter, unless otherwise noted. –90 100 200mV p-p SINEWAVE ON VDD1 NO DECOUPLING VDD1 = VDD2 = 4.5V TO 5.25V 90 80 –70 70 –60 SINAD (dB) 60 PSRR (dB) VDD1 = VDD2 = 5V –80 50 40 –50 –40 –30 30 –20 20 0 100 200 300 400 500 600 700 800 900 0 0.195 1000 04718-008 0 –10 04718-005 10 0.215 0.275 0.295 0.315 Figure 10. SINAD vs. VIN Figure 7. PSRR vs. Supply Ripple Frequency Without Supply Decoupling (1 MHz Filter Used) –90 0.5 –80 0.4 VIN+ = –200mV TO +200mV VIN– = 0V 0.3 DNL ERROR (LSB) VDD1 = VDD2 = 4.5V –60 –50 –40 VDD1 = VDD2 = 5.25V VDD1 = VDD2 = 5V –30 0.2 0.1 0 –0.1 –0.2 –10 –0.3 04718-006 –20 0 500 1000 1500 2000 2500 3000 3500 –0.4 4000 04718-009 –70 SINAD (dB) 0.255 ± INPUT AMPLITUDE (V) SUPPLY RIPPLE FREQUENCY (kHz) 0 0.235 0 10000 20000 0.8 0 8192 POINT FFT fIN = 35Hz SINAD = 79.6991dB THD = –92.6722dB DECIMATION BY 256 –40 40000 50000 60000 Figure 11. Typical DNL, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) Figure 8. SINAD vs. Analog Input Frequency for Various Supply Voltages –20 30000 CODE INPUT FREQUENCY (Hz) VIN+ = –200mV TO +200mV VIN– = 0V 0.6 0.4 INL ERROR (LSB) –60 dB –80 –100 –120 0.2 0 –0.2 –140 0 2 4 6 8 10 12 14 FREQUENCY (kHz) 16 18 20 Figure 9. Typical FFT, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) –0.4 –0.6 04718-010 –180 04718-007 –160 0 10000 20000 30000 CODE 40000 50000 Figure 12. Typical INL, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) Rev. PrA | Page 9 of 19 60000 AD7400A Preliminary Technical Data 100 0.0036 50 IDD2 @ +85°C 0.0035 0 0.0034 IDD2 (A) VDD1 = VDD2 = 5V –50 –100 IDD2 @ –40°C 0.0033 0.0032 VDD1 = VDD2 = 5.25V 04718-014 0.34 0.30 0.26 0.22 0.18 0.14 0.10 0.06 0.02 –0.02 –0.06 –0.10 –0.14 –0.18 –0.22 TEMPERATURE (°C) –0.26 0.0030 5 15 25 35 45 55 65 75 85 95 105 –0.30 –200 –45 –35 –25 –15 –5 0.0031 –0.34 –150 04718-011 OFFSET (µV) VDD1 = VDD2 = 5V IDD2 @ +25°C VDD1 = VDD2 = 4.5V VIN DC INPUT VOLTAGE (V) Figure 16. IDD2 vs. VIN at Various Temperatures Figure 13. Offset Drift vs. Temperature for Various Supply Voltages 9 0.20 VDD1 = VDD2 = 4.5V TO 5.25V 0.15 6 0.10 VDD1 = VDD2 = 5V IIN (µA) GAIN (%) 3 VDD1 = VDD2 = 4.5V 0.05 0 –0.05 0 –3 –0.10 0.30 0.25 0.20 0.15 0.10 0.05 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 TEMPERATURE (°C) 0.35 04718-012 –9 15 25 35 45 55 65 75 85 95 105 –0.35 5 0 –0.20 –45 –35 –25 –15 –5 04718-015 –6 VDD1 = VDD2 = 5.25V –0.15 VIN+ DC INPUT (V) Figure 17. IIN vs. VIN+ DC Input Figure 14 . Gain Error Drift vs. Temperature for Various Supply Voltages 0.0099 0 VDD1 = VDD2 = 5V 0.0098 –10 0.0097 TA = +85°C 0.0096 –20 TA = +25°C –30 CMRR (dB) 0.0094 TA = –40°C 0.0093 0.0092 –40 –50 –60 –70 0.30 0.26 0.22 0.18 0.14 0.10 0.06 0.02 –0.02 –0.06 –0.10 –0.14 –0.18 –0.22 –0.26 –0.30 0.0089 VIN DC INPUT VOLTAGE (V) –80 04718-016 0.0090 0.34 04718-013 0.0091 –0.34 IDD1 (A) 0.0095 –90 –100 0.1 1 10 100 1000 RIPPLE FREQUENCY (kHz) Figure 18. CMRR vs. Common-Mode Ripple Frequency Figure 15. IDD1 vs. VIN at Various Temperatures Rev. PrA | Page 10 of 19 10000 Preliminary Technical Data AD7400A 11.0 1.0 BANDWIDTH = 100kHz 10.8 0.8 10.6 10.0 9.8 VDD1 = VDD2 = 5.25V 9.6 04718-024 VDD1 = VDD2 = 5V 95 TEMPERATURE (°C) VIN DC INPUT (V) Figure 19. RMS Noise Voltage vs. VIN DC Input Figure 20. MCLKOUT vs. Temperature for Various Supplies Rev. PrA | Page 11 of 19 105 85 75 65 55 45 35 25 –5 –15 9.0 –25 9.2 –45 04718-017 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 0 9.4 –35 0.2 5 0.4 VDD1 = VDD2 = 4.5V 10.2 15 MCLKOUT (MHz) 0.6 –0.30 NOISE (mV) 10.4 AD7400A Preliminary Technical Data TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit level, and specified positive full scale, +200 mV (VIN+ − VIN−), Code 53,248 for the 16-bit level. Offset Error Offset is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error This includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-(Noise + Distortion) Ratio (SINAD) This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD − 1.76)/6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7400A, it is defined as THD(dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±200 mV frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency fS as CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not converter linearity. PSRR is the maximum change in the specified full-scale (±200 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 7). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.) Rev. PrA | Page 12 of 19 Preliminary Technical Data AD7400A THEORY OF OPERATION CIRCUIT INFORMATION The AD7400A isolated Σ-Δ modulator converts an analog input signal into a high speed (10 MHz typ), single-bit data stream; the time average of the modulator’s single-bit data is directly proportional to the input signal. Figure 23 shows a typical application circuit where the AD7400A is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an N-bit word. ANALOG INPUT The differential analog input of the AD7400A is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKOUT) provides the clock signal for the conversion process as well as the output data-framing clock. This clock source is internal on the AD7400A. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 21). A differential input of 320 mV results in a stream of ideally all ones. This is the absolute full-scale range of the AD7400A, while 200 mV is the specified full-scale range, as shown in Table 9. Table 9. Analog Input Range Analog Input Full-Scale Range Positive Full Scale Positive Specified Input Range Zero Negative Specified Input Range Negative Full Scale Voltage Input +640 mV +320 mV +200 mV 0 mV −200 mV −320 mV To reconstruct the original information, this output needs to be digitally filtered and decimated. A Sinc3 filter is recommended because this is one order higher than that of the AD7400A modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 39 kHz, assuming a 10 MHz internal clock frequency. Figure 22 shows the transfer function of the AD7400A relative to the 16-bit output. 65535 MODULATOR OUTPUT +FS ANALOG INPUT 53248 ANALOG INPUT SPECIFIED RANGE ADC CODE 04718-019 –FS ANALOG INPUT Figure 21. Analog Input vs. Modulator Output 0 –320mV –200mV +200mV +320mV 04718-020 12288 A differential signal of 0 V results (ideally) in a stream of ones and zeros at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of ones and zeros that are high 81.25% of the time. A differential input of −200 mV produces a stream of ones and zeros that are high 18.75% of the time. ANALOG INPUT Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED 5V + INPUT CURRENT NONISOLATED 5V/3V VDD1 AD7400 VIN+ Σ-∆ MOD/ ENCODER VDD2 VDD SINC3 FILTER DECODER VIN– MDAT MDAT MCLKOUT MCLK CS SCLK SDAT RSHUNT GND1 ENCODER GND2 Figure 23. Typical Application Circuit Rev. PrA | Page 13 of 19 GND 04718-018 DECODER AD7400A Preliminary Technical Data DIFFERENTIAL INPUTS DIGITAL FILTER The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 24. A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKOUT cycle and settle to the required accuracy within the next half cycle. A Sinc3 filter is recommended for use with the AD7400A. This filter can be implemented on an FPGA or a DSP. The following Verilog code provides an example of a Sinc3 filter implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code can possibly be compiled for another FPGA, such as an Altera® device. Note that the data is read on the negative clock edge in this case; although, it can be read on the positive edge, if preferred. Figure 29 shows the effect of using different decimation rates with various filter types. φA VIN– 1kΩ MCLKOUT φB 2pF φA 2pF /*`Data is read on negative clk edge*/ module DEC256SINC24B(mdata1, mclk1, reset, DATA); input mclk1; input reset; input mdata1; filtered*/ φB φA φB φA φB 04718-027 VIN+ 1kΩ /*used to clk filter*/ /*used to reset filter*/ /*ip data to be output [15:0] DATA; Figure 24. Analog Input Equivalent Circuit Since the AD7400A samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7400A. integer location; integer info_file; /*filtered op*/ reg [23:0] ip_data1; reg [23:0] acc1; reg [23:0] acc2; When a capacitive load is switched onto the output of an op amp, the amplitude momentarily drops. The op amp tries to correct the situation and, in the process, hits its slew rate limit. This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7400A. The external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; reg [23:0] diff2; reg [23:0] diff3; reg [23:0] diff1_d; reg [23:0] diff2_d; reg [15:0] DATA; The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 25. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. The series resistor again isolates any op amp from the current spikes created during the sampling process. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. reg [7:0] word_count; R C VIN– AD7400A R 04718-028 VIN+ reg word_clk; reg init; Figure 25. Differential Input RC Network Rev. PrA | Page 14 of 19 Preliminary Technical Data AD7400A /*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 0; to a -1 for 2's comp */ else ip_data1 <= 1; Z = one sample delay WORD_CLK = output word rate */ /* change from a 0 /*ACCUMULATOR (INTEGRATOR) Perform the accumulation (IIR) at the speed of the modulator. MCLKOUT ACC2+ Z + ACC3 Z + 04718-021 Z + Figure 26. Accumulator else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end Z = one sample delay MCLKOUT = modulators conversion bit rate */ always @ (negedge mclk1 or posedge reset) if (reset) begin /*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin /*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end /*DECIMATION STAGE (MCLKOUT/ WORD_CLK) */ always @ (posedge mclk1 or posedge reset) if (reset) word_count <= 0; else word_count <= word_count + 1; always @ (word_count) word_clk <= word_count[7]; /*DIFFERENTIATOR ( including decimation stage) Perform the differentiation stage (FIR) at a lower speed. + ACC3 DIFF1 + – + Z–1 DIFF3 – Z–1 04718-022 Z–1 DIFF2 – WORD_CLK Figure 27. Differentiator /* Clock the Sinc output into an output register WORD_CLK DIFF3 DATA 04718-023 ACC1+ IP_DATA1 always @ (posedge word_clk or posedge reset) if(reset) begin acc3_d2 <= 0; diff1_d <= 0; diff2_d <= 0; diff1 <= 0; diff2 <= 0; diff3 <= 0; end Figure 28. Clocking Sinc Output into an Output Register WORD_CLK = output word rate */ always @ (posedge word_clk) begin DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= end endmodule Rev. PrA | Page 15 of 19 diff3[23]; diff3[22]; diff3[21]; diff3[20]; diff3[19]; diff3[18]; diff3[17]; diff3[16]; diff3[15]; diff3[14]; diff3[13]; diff3[12]; diff3[11]; diff3[10]; diff3[9]; diff3[8]; AD7400A Preliminary Technical Data 90 SINC3 80 70 SINC2 50 40 SINC1 30 20 10 0 04718-025 SNR (dB) 60 1 10 100 1k DECIMATION RATE Figure 29. SNR vs. Decimation Rate for Different Filter Types Rev. PrA | Page 16 of 19 Preliminary Technical Data AD7400A APPLICATION INFORMATION GROUNDING AND LAYOUT Supply decoupling with a value of 100 nF is strongly recommended on both VDD1 and VDD2. Decoupling on one or both VDD1 pins does not significantly affect performance. In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Any decoupling used should be placed as close to the supply pins as possible. Series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Beware of mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift. These tests subjected populations of devices to continuous cross-isolation voltages. To accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. The time to failure values of these units were recorded and used to calculate acceleration factors. These factors were then used to calculate the time to failure under normal operating conditions. The values shown in Table 7 are the lesser of the following two values: • The value that ensures at least a 50-year lifetime of continuous use. • The maximum CSA/VDE approved working voltage. It should also be noted that the lifetime of the AD7400A varies according to the waveform type imposed across the isolation barrier. The iCoupler insulation structure is stressed differently depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and Figure 32 illustrate the different isolation voltage waveforms. RATED PEAK VOLTAGE 0V Figure 30. Bipolar AC Waveform RATED PEAK VOLTAGE 04718-030 A simple standalone AD7400A evaluation board is available with split ground planes and a board split beneath the AD7400A package to ensure isolation. This board allows access to each pin on the device for evaluation purposes. External supplies and all other circuitry (such as a digital filter) must be provided by the user. 04718-029 EVALUATING THE AD7400A PERFORMANCE 0V All insulation structures, subjected to sufficient time and/or voltage, are vulnerable to breakdown. In addition to the testing performed by the regulatory agencies, Analog Devices has carried out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7400A. Figure 31. Unipolar AC Waveform RATED PEAK VOLTAGE 04718-031 INSULATION LIFETIME 0V Figure 32. DC Waveform Rev. PrA | Page 17 of 19 AD7400A Preliminary Technical Data OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 8 0.51 (0.0201) 0.31 (0.0122) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 112906-B COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) 9.90 (0.390) 9.65 (0.380) 9.40 (0.370) 5 1 4 MOLDED PIN 1 INDICATOR 6.60 (0.260) 6.35 (0.250) 6.10 (0.240) 9.90 (0.390) 9.65 (0.380) 9.40 (0.370) 1.40 (0.056) 1.08 (0.043) 0.76 (0.003) 2.54 (0.100) BSC 4.19 (0.165) MAX 7.87 (0.310) 7.62 (0.300) 7.37 (0.290) 0.255 (0.075) 0.010 (0.003) 0.64 (0.025) 0.51 (0.020) 0.38 (0.015) 1.19 (0.047) MAX 1.78 (0.070) MAX LEAD COPLANARIT Y 0.102 (0.004) MAX 0.885 (0.035) 0.635 (0.025) 0.385 (0.015) CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCHES DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34 8-Lead Dual In Line Gull-wing Surface Mount Package [PDIP_SMD] (NS-8) Dimensions shown in millimeters and (inches) Rev. PrA | Page 18 of 19 12° NOM 070207-A 8 Preliminary Technical Data Model AD7400AYRWZ1 AD7400AYRWZREELError! Bookmark not defined. AD7400AYRWZREEL7Error! Bookmark not defined. AD7400AYNSZError! AD7400A Temperature Range −40°C to +125°C −40°C to +125°C Package Description 16-Lead Standard Small Outline Package (SOIC_W) 16-Lead Standard Small Outline Package (SOIC_W) Package Option RW-16 RW-16 −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16 −40°C to +125°C 8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD) NS-8 −40°C to +125°C 8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD) NS-8 −40°C to +125°C 8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD) NS-8 Bookmark not defined. AD7400AYNSZREELError! Bookmark not defined. AD7400AYNSZREEL7Error! Bookmark not defined. EVAL-AD7400AEBZError! Standalone Evaluation Board Bookmark not defined. 1 Z = Pb-free part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07077-0-1/08(PrA) Rev. PrA | Page 19 of 19