TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 16-CHANNEL CONSTANT-CURRENT LED SINK DRIVERS Check for Samples: TLC5926-Q1 TLC5927-Q1 FEATURES 1 • • • • • • • • Qualified for Automotive Applications 16 Constant-Current Output Channels Output Current Adjusted By External Resistor Constant Output Current Range: 5 mA to 120 mA Constant Output Current Invariant to Load Voltage Change Open Load, Shorted Load, and Overtemperature Detection 256-Step Programmable Global Current Gain Excellent Output Current Accuracy: – Between Channels: < ±6% (Max), 10 mA to 50 mA – Between ICs: < ±6% (Max), 10 mA to 50 mA • • • • • 30-MHz Clock Frequency Schmitt-Trigger Input 3.3-V or 5-V Supply Voltage Thermal Shutdown for Overtemperature Protection ESD Performance: 2-kV HBM APPLICATIONS • • • • • General LED Lighting Applications LED Display Systems LED Signage Automotive LED Lighting White Goods DESCRIPTION/ORDERING INFORMATION The TLC5926/TLC5927 is designed for LED displays and LED lighting applications with open-load, shorted-load, and overtemperature detection, and constant-current control. The TLC5926/TLC5927 contains a 16-bit shift register and data latches, which convert serial input data into parallel output format. At the TLC5926/TLC5927 output stage, 16 regulated-current ports provide uniform and constant current for driving LEDs within a wide range of VF (Forward Voltage) variations. Used in systems designed for LED display applications (e.g., LED panels), TLC5926/TLC5927 provides great flexibility and device performance. Users can adjust the output current from 5 mA to 120 mA through an external resistor, Rext, which gives flexibility in controlling the light intensity of LEDs. TLC5926/TLC5927 is designed for up to 17 V at the output port. The high clock frequency, 30 MHz, also satisfies the system requirements of high-volume data transmission. The TLC5926/TLC5927 provides a Special Mode in which two functions are included, Error Detection and Current Gain Control. In the TLC5926/TLC5927 there are two operation modes and three phases: Normal Mode phase, Mode Switching transition phase, and Special mode phase. The signal on the multiple-function pin OE(ED2) is monitored, and when a one-clock-wide short pulse appears on OE(ED2), TLC5926/TLC5927 enters the Mode Switching phase. At this time, the voltage level on LE(ED1) determines the next mode into which the TLC5926/TLC5927 switches. In the Normal Mode phase, the serial data is transferred into TLC5926/TLC5927 via SDI, shifted in the shift register, and transferred out via SDO. LE(ED1) can latch the serial data in the shift register to the output latch. OE(ED2) enables the output drivers to sink current. In the Special Mode phase, the low-voltage-level signal OE(ED2) can enable output channels and detect the status of the output current, to tell if the driving current level is enough or not. The detected error status is loaded into the 16-bit shift register and shifted out via SDO, along with the CLK signal. The system controller can read the error status to determine whether or not the LEDs are properly lit. In the Special Mode phase, TLC5926/TLC5927 also allows users to adjust the output current level by setting a runtime-programmable Configuration Code. The code is sent into TLC5926/TLC5927 via SDI. The positive pulse of LE(ED1) latches the code in the shift register into a built-in 8-bit configuration latch, instead of the output latch. The code affects the voltage at R-EXT and controls the output-current regulator. The output current can be adjusted finely by a gain ranging from 1/12 to 127/128 in 256 steps. Therefore, the current skew between ICs can be compensated within less than 1%, and this feature is suitable for white balancing in LED color-display panels. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com Table 1. ORDERING INFORMATION (1) TA PACKAGE –40°C to 125°C (1) (2) PowerPAD™ – PWP (2) ORDERABLE PART NUMBER Reel of 2000 TOP-SIDE MARKING TLC5926QPWPRQ1 TLC5926Q TLC5927QPWPRQ1 TLC5927Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. BLOCK DIAGRAM OUT0 R-EXT OUT1 OUT14 OUT15 I/O REGULATOR VDD 8 OUTPUT DRIVER and ERROR DETECTION OE(ED2) CONTROL LOGIC 16 16 16-BIT OUTPUT LATCH LE(ED1) CONFIGURATION LATCHES 16 CLK 8 SDI 16-BIT SHIFT REGISTER SDO 16 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 PWP PACKAGE (TOP VIEW) GND SDI CLK LE(ED1) OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 1 24 2 23 3 22 4 5 21 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VDD R-EXT SDO OE(ED2) OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 NOTE: The exposed thermal pad should be connected to ground in all applications. Pin Descriptions NAME DESCRIPTION CLK Clock input for data shift on rising edge GND Ground for control logic and current sink LE(ED1) Data strobe input Serial data is transferred to the respective latch when LE(ED1) is high. The data is latched when LE(ED1) goes low. Also, a control signal input for an Error Detection mode and Current Adjust mode (See Timing Diagram). LE(ED1) has an internal pulldown. OE(ED2) Output enable. When OE (ED2)(active) is low, the output drivers are enabled; when OE(ED2) is high, all output drivers are turned OFF (blanked). Also, a control signal input for an Error Detection mode and Current Adjust mode (See Timing Diagram). OE(ED2) has an internal pullup. OUT0–OUT15 R-EXT Constant-current output Input pin used to connect an external resistor for setting up all output currents SDI Serial-data input to the Shift register SDO Serial-data output to the following SDI of next driver IC or to the microcontroller VDD Supply voltage Exposed Thermal Pad Connect to GND. The thermal pad should be soldered to ground in all applications. Table 2. Diagnostic Features OPEN-LOAD DETECTION SHORT TO GND DETECTION TLC5926 x x TLC5927 x x DEVICE (1) (1) SHORT TO VLED DETECTION x The device has one single error register for all these conditions (one error bit per channel) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 3 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com Timing Diagrams 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK OE(ED2) 1 LE(ED1) 0 SDI off OUT0 on off OUT1 on off OUT2 on off OUT3 on off OUT15 on SDO Don't care Figure 1. Normal Mode Table 3. Truth Table in Normal Mode CLK LE(ED1) OE(ED2) SDI OUT0...OUT15 SDO ↑ H L Dn Dn...Dn – 7...Dn – 15 Dn – 15 ↑ L L Dn + 1 No change Dn – 14 ↑ H L Dn + 2 Dn + 2...Dn – 5...Dn – 13 Dn – 13 ↓ X L Dn + 3 Dn + 2...Dn – 5...Dn – 13 Dn – 13 ↓ X H Dn + 3 off Dn – 13 The signal sequence shown in Figure 2 makes the TLC5926/TLC5927 enter Current Adjust and Error Detection mode. 1 2 3 4 5 OE(ED2) 1 0 1 1 1 LE(ED1) 0 0 0 1 0 CLK Figure 2. Switching to Special Mode 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 In the Current Adjust mode, sending the positive pulse of LE(ED1), the content of the shift register (a current adjust code) is written to the 16-bit configuration latch (see Figure 3). 0 1 2 3 4 12 13 14 15 CLK OE(ED2) 1 LE(ED1) 0 16-bit configuration code SDI Figure 3. Writing Configuration Code When the TLC5926/TLC5927 is in the error detection mode, the signal sequence shown in Figure 4 enables a system controller to read error status codes through SDO. 1 2 3 CLK >2 µs OE(ED2) 1 LE(ED1) 0 SDO Error status code Figure 4. Reading Error Status Code The signal sequence shown in Figure 5 makes TLC5926/TLC5927 resume the Normal mode. Switching to Normal mode resets all internal Error Status registers. OE (ED2) always enables the output port, whether the TLC5926/TLC5927 enters current adjust mode or not. 1 2 3 4 5 OE(ED2) 1 0 1 1 1 LE(ED1) 0 0 0 0 0 CLK Figure 5. Switching to Normal Mode Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 5 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX 0 7 V Input voltage –0.4 VDD + 0.4 V Output voltage –0.5 20 V 120 mA 1920 mA –40 125 °C –40 150 °C –55 150 °C 2 kV VDD Supply voltage VI VO IOUT Output current IGND GND terminal current TA Free-air operating temperature range TJ Operating junction temperature range Tstg Storage temperature range ESD Electrostatic-discharge capability V(HBMESD) (100 pF, 1.5 kΩ) (1) UNIT Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POWER DISSIPATION AND THERMAL IMPEDANCE MIN 2.3 Mounted on JEDEC 4-layer board (JESD 51-5), No airflow, TA = 25°C, TJ = 125°C 2.9 PD Power dissipation (1) θJA Thermal impedance, junction to free air (1) θJP Thermal impedance, junction to pad (1) 6 MAX Mounted on JEDEC 4-layer board (JESD 51-7), No airflow, TA = 25°C, TJ = 125°C Mounted on JEDEC 1-layer board (JESD 51-3), No airflow 63.9 Mounted on JEDEC 4-layer board (JESD 51-7), No airflow 42.7 Mounted on JEDEC 4-layer board (JESD 51-5), No airflow 34.5 2.0 UNIT W °C/W °C/W The exposed thermal pad should be connected to ground in all applications. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VDD Supply voltage VO Supply voltage to the output pins MIN MAX 3 5.5 V 17 V OUT0–OUT15 VO ≥ 0.6 V 5 UNIT IO Output current DC test circuit IOH High-level output current SDO IOL Low-level output current SDO VIH High-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0.7 × VDD VDD V VIL Low-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0 0.3 × VDD V VO ≥ 1 V 120 mA –1 mA 1 mA RECOMMENDED TIMING VDD = 3 V to 5.5 V (unless otherwise noted) TEST CONDITIONS MIN MAX UNIT tw(L) LE(ED1) pulse duration Normal mode 20 ns tw(CLK) CLK pulse duration Normal mode 20 ns tw(OE) OE(ED2) pulse duration Normal mode 1000 ns tsu(D) Setup time for SDI Normal mode 7 ns th(D) Hold time for SDI Normal mode 3 ns tsu(L) Setup time for LE(ED1) Normal mode 18 ns th(L) Hold time for LE(ED1) Normal mode 18 ns tw(CLK) CLK pulse duration Error Detection mode 20 ns tw(ED2) OE(ED2) pulse duration Error Detection mode 2000 ns tsu(ED1) Setup time for LE(ED1) Error Detection mode 7 ns th(ED1) Hold time for LE(ED1) Error Detection mode 10 ns tsu(ED2) Setup time for OE(ED2) Error Detection mode 7 ns th(ED2) Hold time for OE(ED2) Error Detection mode 10 ns fCLK Clock frequency Cascade operation, VDD = 3 V to 5.5 V 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 MHz 7 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VO Supply voltage to the output pins IO Output current VIH High-level input voltage 0.7 × VDD VDD VIL Low-level input voltage GND 0.3 × VDD 17 VO ≥ 0.6 V TLC5926, VOH = 17 V Ileak 5 VO ≥ 1 V Output leakage current TLC5927, VOH = 17 V 120 TJ = 25°C UNIT V mA V 0.5 TJ = 125°C 1 TJ = 25°C 0.5 TJ = 125°C μA 5 VOH High-level output voltage SDO, IOL = –1 mA VOL Low-level output voltage SDO, IOH = 1 mA Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 Output current error, die-to-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6 % Output current error, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6 % Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 Output current error, die-to-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6 % Output current error, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6 % IO(1) IO(2) VDD – 0.4 V 0.4 26 V mA 52 mA IOUT vs VOUT Output current vs VO = 1 V to 3 V, IO = 26 mA output voltage regulation IOUT vs VDD Output current vs supply voltage VDD = 3 V to 5.5 V, IO = 26 mA/120 mA Pullup resistance OE(ED2) 250 500 800 kΩ Pulldown resistance LE(ED1) 250 500 800 kΩ 150 175 200 °C ±0.1 %/V ±1 Tsd Overtemperature shutdown (1) Thys Restart temperature hysteresis IOUT,Th Threshold current for open error detection VOUT,TTh Trigger threshold voltage for short-error detection IOUT,target = 5 mA to 120 mA (TLC5927 only) 2.3 VOUT, RTh Return threshold voltage for short-error detection (TLC5927 only) 1.9 IDD (1) 8 Supply current IOUT,target = 5 mA to 120 mA IOUT,target = 5 mA to 120 mA 15 °C 0.5 × Itarget % 2.6 3.2 V V OUT0–OUT15 = off, Rext = Open, OE = VIH 10 OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH 14 OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH 18 OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH 20 OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL 14 OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL 18 OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL 20 mA Specified by design Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VO Supply voltage to the output pins IO Output current VIH High-level input voltage 0.7 × VDD VDD VIL Low-level input voltage GND 0.3 × VDD 17 VO ≥ 0.6 V TLC5926, VOH = 17 V Ileak 5 VO ≥ 1 V Output leakage current TLC5927, VOH = 17 V 120 TJ = 25°C UNIT V mA V 0.5 TJ = 125°C 1 TJ = 25°C 0.5 TJ = 125°C μA 5 VOH High-level output voltage SDO, IOL = –1 mA VOL Low-level output voltage SDO, IOH = 1 mA Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 Output current error, die-to-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6 % Output current error, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6 % Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 Output current error, die-to-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6 % Output current error, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6 % IO(1) IO(2) VDD – 0.4 V 0.4 26 V mA 52 mA IOUT vs VOUT Output current vs VO = 1 V to 3 V, IO = 26 mA output voltage regulation IOUT vs VDD Output current vs supply voltage VDD = 3 V to 5.5 V, IO = 26 mA/120 mA Pullup resistance OE(ED2) 250 500 800 kΩ Pulldown resistance LE(ED1) 250 500 800 kΩ 150 175 200 °C ±0.1 %/V ±1 Tsd Overtemperature shutdown (1) Thys Restart temperature hysteresis IOUT,Th Threshold current for open error detection VOUT,TTh Trigger threshold voltage for short-error detection IOUT,target = 5 mA to 120 mA (TLC5927 only) 2.3 VOUT, RTh Return threshold voltage for short-error detection (TLC5927 only) 1.9 IDD (1) Supply current IOUT,target = 5 mA to 120 mA IOUT,target = 5 mA to 120 mA 15 °C 0.5 × Itarget % 2.6 3.2 V V OUT0–OUT15 = off, Rext = Open, OE = VIH 11 OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH 17 OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH 18 OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH 25 OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL 17 OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL 18 OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL 25 mA Specified by design Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 9 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com SWITCHING CHARACTERISTICS VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) MIN TYP MAX UNIT tPLH1 Low-to-high propagation delay time, CLK to OUTn PARAMETER TEST CONDITIONS 35 65 105 ns tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 35 65 105 ns tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 35 65 105 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 20 45 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 200 300 470 ns tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 200 300 470 ns tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 200 300 470 ns tPHL4 High-to-low propagation delay time, CLK to SDO 20 40 ns tw(CLK) Pulse duration, CLK tw(L) Pulse duration LE(ED1) tw(OE) Pulse duration, OE(ED2) tw(ED2) Pulse duration, OE(ED2) in Error Detection mode th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) th(D) VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 20 ns 20 ns 1000 ns 2 μs 10 ns Hold time, SDI 5 ns tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 7 ns th(L) Hold time, LE(ED1), Normal mode 18 ns tsu(L) Setup time, LE(ED1), Normal mode 18 tr Rise time, CLK (1) (1) ns 500 ns tf Fall time, CLK 500 ns tor Rise time, outputs (off) 245 ns tof Rise time, outputs (on) 600 ns fCLK Clock frequency 30 MHz (1) 10 Cascade operation If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 SWITCHING CHARACTERISTICS VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) MIN TYP MAX tPLH1 Low-to-high propagation delay time, CLK to OUTn PARAMETER TEST CONDITIONS 27 65 95 ns tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 27 65 95 ns tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 27 65 95 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 20 30 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 180 300 445 ns tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 180 300 445 ns tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 180 300 445 ns tPHL4 High-to-low propagation delay time, CLK to SDO 20 30 ns tw(CLK) Pulse duration, CLK tw(L) Pulse duration LE(ED1) tw(OE) Pulse duration, OE(ED2) tw(ED2) Pulse duration, OE(ED2) in Error Detection mode th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) th(D) VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 UNIT 20 ns 20 ns 1000 ns 2 μs 10 ns Hold time, SDI 3 ns tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 4 ns th(L) Hold time, LE(ED1), Normal mode 15 ns tsu(L) Setup time, LE(ED1), Normal mode 15 tr Rise time, CLK (1) (1) ns 500 ns tf Fall time, CLK 500 ns tor Rise time, outputs (off) 245 ns tof Rise time, outputs (on) 570 ns fCLK Clock frequency 30 MHz (1) Cascade operation If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 11 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION IDD VDD OE(ED2) IIH, IIL IOUT OUT0 CLK LE(ED1) OUT15 SDI VIH, VIL R-EXT GND SDO Iref Figure 6. Test Circuit for Electrical Characteristics IDD IOUT VDD VIH, VIL OE(ED2) CLK LE(ED1) Function Generator OUT0 OUT15 RL CL SDI Logic input waveform VIH = VDD VIL = 0V R-EXT Iref GND SDO CL VL Figure 7. Test Circuit for Switching Characteristics 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) tw(CLK) CLK 50% tsu(D) SDI 50% 50% th(D) 50% 50% tPLH4, tPHL4 50% SDO tw(L) 50% LE(ED1) tsu(L) th(L) OE Low OE(ED2) LOW tPLH2, tPHL2 Output off OUTn 50% Output on tPLH1, tPHL1 tw(OE) HIGH 50% OE Pulsed OE(ED2) 50% tPLH3 tPHL3 Output off 90% OUTn 90% 50% 50% 10% tof 10% tor Figure 8. Normal Mode Timing Waveforms Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 13 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) tw(CLK) 50% CLK tsu(ED2) OE(ED2) th(ED2) 50% tsu(ED1) LE(ED1) th(ED1) 50% 2 CLK Figure 9. Switching to Special Mode Timing Waveforms CLK OE(ED2) 50% 50% tw(ED2) Figure 10. Reading Error Status Code Timing Waveforms 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 APPLICATION INFORMATION Operating Principles Constant Current In LED display applications, TLC5926/TLC5927 provides nearly no current variations from channel to channel and from IC to IC. While IOUT ≤ 50 mA, the maximum current skew between channels is less than ±6% and between ICs is less than ±6%. Adjusting Output Current TLC5926/TLC5927 scales up the reference current, Iref, set by the external resistor Rext to sink a current, Iout, at each output port. Users can follow the below formulas to calculate the target output current IOUT,target in the saturation region: VR-EXT = 1.26 V × VG Iref = VR-EXT/Rext, if another end of the external resistor Rext is connected to ground. IOUT,target = Iref × 15 × 3CM – 1 Where Rext is the resistance of the external resistor connected to the R-EXT terminal, and VR-EXT is the voltage of R-EXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code. The Current Multiplier (CM) determines that the ratio IOUT,target/Iref is 15 or 5. After power on, the default value of VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio IOUT,target/Iref = 15. Based on the default VG and CM. VR-EXT = 1.26 V × 127/128 = 1.25 V IOUT,target = (1.25 V/Rext) × 15 Therefore, the default current is approximately 52 mA at 360 Ω and 26 mA at 720 Ω. The default relationship after power on between IOUT,target and Rext is shown in Figure 11. 140 IOUT – mA 120 100 80 40 0 0 500 1000 1500 2000 2500 3000 3500 4000 Rext – W Figure 11. Default Relationship Curve Between IOUT,target and Rext Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 15 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com Operation Phases Operation Mode Switching In order to switch between its two modes, TLC5926/TLC5927 monitors the signal OE(ED2). When a one-clock-wide pulse of OE(ED2) appears, TLC5926/TLC5927 enters the two-clock-period transition phase, the Mode Switching phase. After power on, the default operation mode is the Normal Mode (see Figure 12). Switching to Special Mode 1 2 3 Switching to Normal Mode 4 5 1 CLK 2 3 4 5 CLK OE(ED2) 1 0 1 1 1 OE(ED2) 1 0 1 1 1 LE(ED1) 0 0 0 1 0 LE(ED1) 0 0 0 0 0 Actual Mode Phase (Normal or Special) Mode Switching Special Mode Actual Mode Phase (Normal or Special) Mode Switching Normal Mode Figure 12. Mode Switching As shown in Figure 12, once a one-clock-wide short pulse (101) of OE(ED2) appears, TLC5926/TLC5927 enters the Mode Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high, TLC5926/TLC5927 switches to Special mode; otherwise, it switches to Normal mode. The signal LE(ED1) between the third and the fifth rising edges of CLK cannot latch any data. Its level is used only to determine into which mode to switch. However, the short pulse of OE(ED2) can still enable the output ports. During mode switching, the serial data can still be transferred through SDI and shifted out from SDO. NOTES: 1. The signal sequence for the mode switching may be used frequently to ensure that the TLC5926/TLC5927 is in the proper mode. 2. The 1 and 0 on the LE(ED1) signal are sampled at the rising edge of CLK. The X means its level does not affect the result of mode switching mechanism. 3. After power on, the default operation mode is Normal mode. Normal Mode Phase Serial data is transferred into TLC5926/TLC5927 via SDI, shifted in the Shift Register, and output via SDO. LE(ED1) can latch the serial data in the Shift Register to the Output Latch. OE(ED2) enables the output drivers to sink current. These functions differ only as described in Operation Mode Switching, in which case, a short pulse triggers TLC5926/TLC5927 to switch the operation mode. However, as long as LE(ED1) is high in the Mode Switching phase, TLC5926/TLC5927 remains in the Normal mode, as if no mode switching occurred. Special Mode Phase In the Special mode, as long as OE(ED2) is not low, the serial data is shifted to the Shift Register via SDI and shifted out via SDO, as in the Normal mode. However, there are two differences between the Special Mode and the Normal Mode, as shown in the following sections. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 Reading Error Status Code in Special Mode When OE(ED2) is pulled low while in Special mode, error detection and load error status codes are loaded into the Shift Register, in addition to enabling output ports to sink current. Figure 13 shows the timing sequence for error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must be sampled at the voltage low signal OE(ED2). Immediately after the second 0 is sampled, the data input source of the Shift Register changes to the 16-bit parallel Error Status Code register, instead of from the serial data on SDI. Normally, the error status codes are generated at least 2 μs after the falling edge of OE(ED2). The occurrence of the third or later 0 saves the detected error status codes into the Shift Register. Therefore, when OE(ED2) is low, the serial data cannot be shifted into TLC5926/TLC5927 via SDI. When OE(ED2) is pulled high, the data input source of the Shift Register is changed back to SDI. At the same time, the output ports are disabled and the error detection is completed. Then, the error status codes saved in the Shift Register can be shifted out via SDO bit-by-bit along with CLK, as well as the new serial data can be shifted into TLC5926/TLC5927 via SDI. While in Special mode, the TLC5926/TLC5927 cannot simultaneously transfer serial data and detect LED load error status. 1 2 3 CLK >2 µs OE(ED2) 1 0 0 0 0 0 1 1 1 1 LE(ED1) 0 0 0 0 0 0 0 0 0 0 Error Status Code SDO Bit 15 Bit 14 Bit 13 Bit 12 Data source of shift register Error Detection SDI SDI Figure 13. Reading Error Status Code Writing Configuration Code in Special Mode When in Special mode, the active high signal LE(ED1) latches the serial data in the Shift Register to the Configuration Latch, instead of the Output Latch. The latched serial data is used as the Configuration Code. The code is stored until power off or the Configuration Latch is rewritten. As shown in Figure 14, the timing for writing the Configuration Code is the same as the timing in the Normal Mode to latching output channel data. Both the Configuration Code and Error Status Code are transferred in the common 16-bit Shift Register. Users must pay attention to the sequence of error detection and current adjustment to avoid the Configuration Code being overwritten by Error Status Code. 0 1 2 3 4 12 13 14 15 Bit 3 Bit 2 Bit 1 Bit 0 CLK OE(ED2) 1 LE(ED1) 0 SDI Bit 15 Bit 14 Bit 13 Bit 12 16-Bit Configuration Code Figure 14. Writing Configuration Code Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 17 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com Open-Circuit Detection Principle The LED Open-Circuit Detection compares the effective current level IOUT with the open load detection threshold current IOUT,Th. If IOUT is below the IOUT,Th threshold, the TLC5926/TLC5927 detects an open-load condition. This error status can be read as an error status code in the Special mode. For open-circuit error detection, a channel must be on. Table 4. Open-Circuit Detection STATE OF OUTPUT PORT Off On (1) CONDITION OF OUTPUT CURRENT ERROR STATUS CODE MEANING IOUT = 0 mA 0 Detection not possible IOUT < IOUT,Th (1) 0 Open circuit IOUT ≥ IOUT,Th (1) 1 Normal IOUT,Th = 0.5 × IOUT,target (typical) Short-Circuit Detection Principle (TLC5927 Only) The LED short-circuit detection compares the effective voltage level VOUT with the shorted-load detection threshold voltages VOUT,TTh and VOUT,RTh. If VOUT is above the VOUT,TTh threshold, the TLC5927 detects a shorted-load condition. If the VOUT is below VOUT,RTh threshold, no error is detected and the error bit is reset. This error status can be read as an error status code in the Special mode. For short-circuit error detection, a channel must be on. Table 5. Short-Circuit Detection STATE OF OUTPUT PORT CONDITION OF OUTPUT VOLTAGE ERROR STATUS CODE MEANING Off IOUT = 0 mA 0 Detection not possible VOUT ≥ VOUT,TTh 0 Short circuit VOUT < VOUT,RTh 1 Normal On Overtemperature Detection and Shutdown The TLC5926/TLC5927 is equipped with a global overtemperature sensor and 16 individual, channel-specific overtemperature sensors. • When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status is stored in the internal Error Status register of every channel. After shutdown, the channels automatically restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as the error status code in the Special mode. • When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut down, and the error status is stored only in the internal Error Status register of the affected channel. After shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as error status code in the Special mode. For channel-specific overtemperature error detection, a channel must be on. The error status code is reset when the TLC5926/TLC5927 returns to Normal mode. 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 TLC5926-Q1 TLC5927-Q1 www.ti.com ......................................................................................................................................................................................... SLVS973 – SEPTEMBER 2009 Table 6. Overtemperature Detection (1) (1) STATE OF OUTPUT PORT CONDITION ERROR STATUS CODE Off IOUT = 0 mA 0 MEANING On On → all channels Off Tj < Tj,trip global 1 Normal Tj > Tj,trip global All error status bits = 0 Global overtemperature On On → Off Tj < Tj,trip channel n 1 Normal Tj > Tj,trip channel n Channel n error status bit = 0 Channel n overtemperature The global shutdown threshold temperature is approximately 170°C. 16-Bit Configuration Code and Current Gain Bit definition of the Configuration Code in the Configuration Latch is shown in Table 7. Table 7. Bit Definition of 8-Bit Configuration Code Meaning Default Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8–15 CM HC CC0 CC1 CC2 CC3 CC4 CC5 Don't care 1 1 1 1 1 1 1 1 X Bit 7 is first sent into TLC5926/TLC5927 via SDI. Bits 1 to 7 {HC, CC[0:5]} determine the voltage gain (VG) that affects the voltage at R-EXT and indirectly affects the reference current, Iref, flowing through the external resistor at R-EXT. Bit 0 is the Current Multiplier (CM) that determines the ratio IOUT,target/Iref. Each combination of VG and CM gives a specific Current Gain (CG). • VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as: VG = (1 + HC) × (1 + D/64) / 4 D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20 Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage gain VG into 128 steps and two sub-bands: Low voltage sub-band (HC = 0): VG = 1/4 ~ 127/256, linearly divided into 64 steps High voltage sub-band (HC = 1): VG = 1/2 ~ 127/128, linearly divided into 64 steps • CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range. High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA. Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA • CG: The total Current Gain is defined as the following. VR-EXT = 1.26 V × VG Iref = VR-EXT/Rext, if the external resistor, Rext, is connected to ground. IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG CG = VG × 3CM – 1 Therefore, CG = (1/12) to (127/128) divided into 256 steps. Examples • Configuration Code {CM, HC, CC[0:5]} = {1,1,111111} VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992 • Configuration Code = {1,1,000000} VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5 • Configuration Code = {0,0,000000} VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12 After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 15. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 19 TLC5926-Q1 TLC5927-Q1 SLVS973 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com 1.00 CM = 1 (High Current Multiplier) CM = 0 (Low Current Multiplier) Current Gain (CG) 0.75 HC = 0 (Low Voltage SubBand) 0.50 HC = 1 (High Voltage SubBand) HC = 0 (Low Voltage SubBand) HC = 1 (High Voltage SubBand) 0.25 {1,1,110000} {1,1,100000} {1,1,010000} {1,1,000000} {1,0,110000} {1,0,100000} {1,0,010000} {1,0,000000} {0,1,110000} {0,1,100000} {0,1,010000} {0,1,000000} {0,0,110000} {0,0,100000} {0,0,010000} {0,0,000000} 0.00 Configuration Code (CM, HC, CC[0:5]) in Binary Format Figure 15. Current Gain vs Configuration Code 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5926-Q1 TLC5927-Q1 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5926QPWPRQ1 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLC5927QPWPRQ1 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TLC5926-Q1, TLC5927-Q1 : • Catalog: TLC5926, TLC5927 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC5927QPWPRQ1 Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 24 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5927QPWPRQ1 HTSSOP PWP 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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