PRELIMINARY DATA SHEET 256MB Unbuffered DDR SDRAM DIMM EBD25UC8AAFA-6B (32M words × 64 bits, 1 Rank) Features The EBD25UC8AAFA-6B is 32M words × 64 bits, 1 rank Double Data Rate (DDR) SDRAM unbuffered module, mounting 8 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. • 184-pin socket type dual in line memory module (DIMM) PCB height: 31.75mm Lead pitch: 1.27mm • 2.5V power supply • Data rate: 333Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval • 2 variations of refresh Auto refresh Self refresh L EO Description t uc od Pr Document No. E0390E10 (Ver. 1.0) Date Published June 2003 (K) Japan URL: http://www.elpida.com This product became EOL in June, 2004. Elpida Memory, Inc. 2003 EBD25UC8AAFA-6B Ordering Information Part number Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) Package Contact pad Mounted devices EBD25UC8AAFA-6B 333 DDR333B (2.5-3-3) Gold M2S56D30ATP-60 184-pin DIMM Pin Configurations Front side 1 pin 52 pin 53 pin EO 93 pin 92 pin 144 pin 145 pin 184 pin Back side Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 47 NC 93 VSS 139 VSS 2 DQ0 48 A0 94 DQ4 140 NC 3 VSS 49 NC 95 DQ5 141 A10 4 DQ1 50 VSS 96 VDD 142 NC 5 DQS0 51 NC 97 DM0/DQS9 143 VDD 6 DQ2 52 BA1 98 DQ6 144 NC 7 VDD 53 DQ32 99 DQ7 145 VSS 8 DQ3 54 VDD 100 VSS 146 DQ36 9 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 12 DQ8 58 13 DQ9 59 14 DQS1 60 15 VDD 61 DQ40 16 CK1 62 VDD L Pin No. Pr DQ34 103 NC 149 DM4/DQS13 VSS 104 VDD 150 DQ38 BA0 105 DQ12 151 DQ39 DQ35 106 DQ13 152 VSS 63 /WE VSS 64 DQ41 19 DQ10 65 /CAS 20 DQ11 66 VSS 21 CKE0 67 DQS5 22 VDD 68 DM1/DQS10 153 DQ44 108 VDD 154 /RAS 109 DQ14 155 DQ45 110 DQ15 156 VDD 111 NC 157 /CS0 112 VDD 158 NC 113 NC 159 DM5/DQS14 DQ42 114 DQ20 160 VSS 161 DQ46 162 DQ47 t uc /CK1 18 od 17 107 23 DQ16 69 DQ43 115 A12 24 DQ17 70 VDD 116 VSS 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDD 27 A9 73 DQ49 119 DM2/DQS11 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 /CK2 121 DQ22 167 NC 30 VDD 76 CK2 122 A8 168 VDD Preliminary Data Sheet E0390E10 (Ver. 1.0) 2 EBD25UC8AAFA-6B Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 31 DQ19 77 VDD 123 DQ23 169 DM6/DQS15 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDD 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VDDID 128 VDD 174 DQ60 37 A4 83 DQ56 129 DM3/DQS12 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16 40 DQ27 86 DQS7 132 VSS 178 DQ62 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 NC 180 VDD 43 A1 89 VSS 135 NC 181 SA0 44 NC 90 NC 136 VDD 182 SA1 45 NC 91 SDA 137 CK0 183 SA2 46 VDD 92 SCL 138 /CK0 184 VDDSPD L EO 41 t uc od Pr Preliminary Data Sheet E0390E10 (Ver. 1.0) 3 EBD25UC8AAFA-6B Pin Description Pin name Function A0 to A12 Address input Row address Column address BA0, BA1 Bank select address DQ0 to DQ63 Data input/output /RAS Row address strobe command /CAS Column address strobe command A0 to A12 A0 to A9 Write enable /CS0 Chip select CKE0 Clock enable CK0 to CK2 Clock input /CK0 to /CK2 Differential clock input DQS0 to DQS7 Input and output data strobe DM0 to DM7/DQS9 to DQS16 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0 to SA2 Serial address input VDD VDDSPD VREF VSS NC Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag Pr VDDID L EO /WE No connection t uc od Preliminary Data Sheet E0390E10 (Ver. 1.0) 4 EBD25UC8AAFA-6B Serial PD Matrix Byte No. 0 1 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 bytes 0 0 0 0 1 0 0 0 08H 256 bytes 2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM 3 Number of row address 0 0 0 0 1 1 0 1 0DH 13 Number of column address 0 0 0 0 1 0 1 0 0AH 10 5 Number of DIMM ranks 0 0 0 0 0 0 0 1 01H 1 6 Module data width 0 1 0 0 0 0 0 0 40H 64 7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2 9 DDR SDRAM cycle time, CL = 2.5 0 1 1 0 0 0 0 0 60H 6.0ns*1 10 SDRAM access from clock (tAC) 0 1 1 1 0 0 0 0 70H 0.70ns*1 11 DIMM configuration type 0 0 0 0 0 0 0 0 00H None. 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.6µs 13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H ×8 14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None. 0 0 0 0 0 0 0 1 01H 1 CLK 0 0 0 0 1 1 1 0 0EH 2,4,8 0 0 0 0 0 1 0 0 04H 4 EO 4 16 17 19 20 Pr 18 SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency L 15 0 0 0 1 1 0 0 0CH 2, 2.5 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 1 0 02H 1 1 0 0 0 0 0 20H Differential Clock 21 SDRAM module attributes 0 0 22 SDRAM device attributes: General 1 1 23 Minimum clock cycle time at CL = 2 0 1 24 Maximum data access time (tAC) from 0 clock at CL = 2 1 0 0 25 to 26 od 0 0 0 0 0 0 C0H VDD ± 0.2V 1 1 0 1 0 1 75H 7.5ns*1 1 1 0 0 0 0 70H 0.70ns*1 0 0 0 0 0 0 00H 0 0 1 0 0 0 48H 18ns 1 1 0 0 0 0 30H 12ns 0 0 48H 18ns 1 0 2AH 42ns 0 0 40H 256M bytes 0 0 80H 0.80ns*1 0 0 80H 0.80ns*1 0 1 45H 0.45ns*1 27 Minimum row precharge time (tRP) 0 1 28 Minimum row active to row active delay (tRRD) 0 0 29 Minimum /RAS to /CAS delay (tRCD) 0 1 0 0 1 0 30 Minimum active to precharge time (tRAS) 0 0 1 0 1 0 31 Module rank density 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 32 33 34 Address and command setup time 1 before clock (tIS) Address and command hold time after 1 clock (tIH) Data input setup time before clock 0 (tDS) Preliminary Data Sheet E0390E10 (Ver. 1.0) 5 t uc 0 EBD25UC8AAFA-6B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 35 Data input hold time after clock (tDH) 0 1 0 0 0 1 0 1 45H 0.45ns*1 36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use 41 Active command period (tRC) 0 0 1 1 1 1 0 0 3CH 60ns*1 42 Auto refresh to active/ Auto refresh command cycle (tRFC) 0 1 0 0 1 0 0 0 48H 72ns*1 43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 1 1 0 0 3CH 15ns*1 44 Dout to DQS skew 0 0 1 0 1 1 0 1 2DH 0.45ns*1 45 Data hold skew (tQHS) 0 1 0 1 0 1 0 1 55H 0.55ns*1 46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use 62 SPD Revision 0 0 0 0 0 0 0 0 00H EO Checksum for bytes 0 to 62 0 0 1 0 0 0 1 0 22H 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory 67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location × × × × × × × × ×× (ASCII-8bit code) 73 Module part number 0 1 0 0 0 1 0 1 45H E 74 Module part number 0 1 0 0 0 0 1 0 42H B 75 Module part number 0 1 0 0 0 1 0 0 44H D 76 Module part number 0 0 1 1 0 0 1 0 32H 2 77 Module part number 0 0 1 1 0 1 0 1 35H 5 78 Module part number 0 1 0 1 0 1 0 1 55H U L 63 Module part number 80 Module part number 81 Module part number 82 Module part number 83 Module part number 84 Module part number 0 1 0 0 0 0 1 1 43H C 0 0 1 1 1 0 0 0 38H 8 0 1 0 0 0 0 0 1 41H A 0 1 0 0 0 0 0 1 41H A 0 1 0 0 0 1 1 0 46H F 0 1 0 0 0 0 0 1 41H A 85 Module part number 0 0 86 Module part number 0 0 87 Module part number 0 1 88 to 90 Module part number 0 0 91 Revision code 0 0 92 Revision code 0 0 Manufacturing date × × 94 Manufacturing date × × 95 to 98 Module serial number 99 to 127 Manufacture specific data 1 0 1 1 0 1 2DH — 1 1 0 1 1 0 36H 6 0 0 0 0 1 0 42H B 1 0 0 0 0 0 20H (Space) 1 1 0 0 0 0 30H Initial 1 0 0 0 0 0 20H × × × × × × × × × × ×× × × ×× Note: 1. These specifications are defined based on component specification, not module. Preliminary Data Sheet E0390E10 (Ver. 1.0) 6 (Space) Year code (HEX) Week code (HEX) t uc 93 od Pr 79 EBD25UC8AAFA-6B Block Diagram /CS0 RS RS DM0/DQS9 DQS0 8 RS DQ0 to DQ7 DQS /CS DQ U1 DM RS RS DM1/DQS10 DQS1 8 RS DQ8 to DQ15 DQS /CS DM DQ U11 RS RS DM2/DQS11 DQS2 8 RS DQ16 to DQ23 DQS /CS DQ U3 DM RS RS DM3/DQS12 8 RS DQ24 to DQ31 DQS /CS DQ U13 DM RS RS DM4/DQS13 DQS4 8 RS DQ32 to DQ39 DQS /CS DM DQ U14 RS RS DM5/DQS14 DQS5 8 RS DQ40 to DQ47 DQS /CS DQ U6 DM RS RS DM6/DQS15 DQS6 L EO DQS3 8 RS DQ48 to DQ55 DQS /CS DM DQ U16 RS RS DM7/DQS16 DQS7 8 DQ56 to DQ63 RS DQS /CS DQ U8 DM Pr 5.1Ω A0 to A12 * U1, U3, U6, U8, U11, U13, U14, U16 : 256M bits DDR SDRAM U20: 2k bits EEPROM RS: 22Ω VDD U1, U3, U6, U8, U11, U13, U14, U16 VSS U1, U3, U6, U8, U11, U13, U14, U16 VDDID Clock wiring /RAS /RAS (U1, U3, U6, U8, U11, U13, U14, U16) 5.1Ω /CAS /CAS (U1, U3, U6, U8, U11, U13, U14, U16) 5.1Ω /WE /WE (U1, U3, U6, U8, U11, U13, U14, U16) CKE0 CKE (U1, U3, U6, U8, U11, U13, U14, U16) od open BA0, BA1 (U1, U3, U6, U8, U11, U13, U14, U16) 5.1Ω U1, U3, U6, U8, U11, U13, U14, U16 VREF A0 to A12 (U1, U3, U6, U8, U11, U13, U14, U16) 5.1Ω BA0, BA1 Serial PD Clock input DDR SDRAMS CK0, /CK0 2DRAM loads CK1, /CK1 3DRAM loads CK2, /CK2 3DRAM loads Note: Wire per Clock loading table/Wiring diagrams. SCL SCL SDA SDA U20 A0 A1 A2 t uc SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. Preliminary Data Sheet E0390E10 (Ver. 1.0) 7 EBD25UC8AAFA-6B Logical Clock Net Structure 6DRAM loads CLK 5DRAM loads DRAM1 DRAM2 R = 120Ω DRAM1 R = 120Ω DRAM3 DRAM2 DRAM3 DIMM connector DIMM connector DRAM4 Capacitance DRAM5 DRAM5 DRAM6 DRAM6 /CLK EO 4DRAM loads 3DRAM loads DRAM1 DRAM2 R = 120Ω R = 120Ω Capacitance DIMM connector L 2DRAM loads Capacitance Capacitance DRAM5 DRAM5 DRAM6 Capacitance 1DRAM loads DRAM1 Capacitance Pr Capacitance R = 120Ω Capacitance DIMM connector Capacitance DRAM3 DIMM connector R = 120Ω DRAM1 Capacitance DRAM3 DIMM connector Capacitance Capacitance DRAM5 od Capacitance Capacitance t uc Preliminary Data Sheet E0390E10 (Ver. 1.0) 8 EBD25UC8AAFA-6B Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT –0.5 to +3.6 V Supply voltage relative to VSS VDD –0.5 to +3.6 V Short circuit output current IOS 50 mA Power dissipation PD 8 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –40 to +100 °C Note 1 EO Notes: 1. DDR SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification) Parameter Symbol Min Typ Max Unit Notes Supply voltage VDD,VDDQ 2.3 2.5 2.7 V 1 L 0 0 0 V VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2 Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3 VIN (DC) –0.3 — VDDQ + 0.3 V 4 VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V VID (DC) 0.36 — VDDQ + 0.6 Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs V 5, 6 VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. t uc od Notes: 1. 2. 3. 4. 5. 6. Pr VSS Input reference voltage Preliminary Data Sheet E0390E10 (Ver. 1.0) 9 EBD25UC8AAFA-6B DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Grade max. Unit Test condition CKE ≥ VIH, tRC = tRC (min.) CKE ≥ VIH, BL = 4, CL = 2.5, tRC = tRC (min.) Operating current (ACTV-PRE) IDD0 800 mA Operating current (ACTV-READ-PRE) IDD1 960 mA Idle power down standby current IDD2P 80 mA CKE ≤ VIL Floating idle Standby current Active power down standby current Notes 1, 2, 9 1, 2, 5 4 IDD2F 280 mA CKE ≥ VIH, /CS ≥ VIH 4, 5 DQ, DQS, DM = VREF IDD3P 160 mA CKE ≤ VIL IDD3N 440 mA IDD4R 1520 mA IDD4W 1520 mA Auto refresh current IDD5 1200 mA Self refresh current IDD6 24 mA Operating current (4 banks interleaving) IDD7A 2320 mA Active standby current EO Operating current (Burst read operation) Operating current (Burst write operation) BL = 4 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6 5, 6, 7 L These IDD data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. 4 banks active. Only one bank is running at tRC = tRC (min.) The IDD data on this table are measured with regard to tCK = tCK (min.) in general. Command/Address transition once per one every two clock cycles. Pr Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 2.5 CKE ≥ VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Input ≥ VDD – 0.2 V Input ≤ 0.2 V 3 DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Symbol min. Input leakage current ILI –16 Output leakage current ILO –5 Output high current IOH –16.8 Output low current IOL 16.8 Note: 1. DDR SDRAM component specification. max. Unit Test condition 16 µA VDD ≥ VIN ≥ VSS 5 µA VDD ≥ VOUT ≥ VSS — mA VOUT = VTT + 0.84V 1 — mA VOUT = VTT – 0.84V 1 Notes t uc od Parameter Preliminary Data Sheet E0390E10 (Ver. 1.0) 10 EBD25UC8AAFA-6B Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Input capacitance CI1 Address, /RAS, /CAS, /WE, /CS, CKE 75 pF Input capacitance CI2 CK, /CK 60 pF Data and DQS input/output capacitance CO DQ, DQS 15 pF Notes AC Characteristics (TA = 0 to +70°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM Componen Specification) Parameter EO Clock cycle time (CL = 2) Symbol min. max Unit tCK 7.5 15 ns tCK 6 15 ns CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 tCK CK half period tHP min (tCH, tCL) — tCK DQ output access time from CK, /CK tAC –0.70 0.70 ns DQS output access time from CK, /CK tDQSCK –0.60 0.60 ns DQS to DQ skew tDQSQ — 0.45 ns L (CL = 2.5) Notes DQ/DQS output hold time from DQS tQH tHP – 0.55 — ns Data-out high-impedance time from CK, /CK tHZ –0.70 0.70 ns 1 Data-out low-impedance time from CK, /CK tLZ –0.70 0.70 ns 1 Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width tRPRE 0.9 1.1 tCK tRPST 0.4 0.6 tCK tDS 0.45 — ns tDH 0.45 — ns tDIPW 1.75 — ns tWPRES 0 — ns od Write preamble setup time Pr Read preamble Write preamble tWPRE 0.25 — tCK Write postamble tWPST 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 tCK tDSS 0.2 — tCK DQS falling edge hold time from CK tDSH 0.2 — tCK DQS input high pulse width tDQSH 0.35 — tCK DQS input low pulse width tDQSL 0.35 Address and control input setup time tIS 0.8 Address and control input hold time tIH 0.8 Mode register set command cycle time tMRD 12 Active to Precharge command period tRAS 42 Active to Active/Auto refresh command period tRC 60 Auto refresh to Active/Auto refresh command period tRFC 72 Active to Read/Write delay tRCD 18 Precharge to active command period tRP 18 Preliminary Data Sheet E0390E10 (Ver. 1.0) 11 2 t uc DQS falling edge to CK setup time 3 — tCK — ns 6 — ns 6 — ns 120000 ns — ns — ns — ns — ns EBD25UC8AAFA-6B Parameter Symbol min. max Unit Active to active command period tRRD 12 — ns Write recovery time tWR 15 — ns Auto precharge write recovery and precharge time tDAL 35 — ns Internal write to Read command delay tWTR 1 — tCK Exit self refresh to non-read command tXSNR 75 ns Exit self refresh to read command tXSRD 200 tCK Exit power down to any non-read command tXPNR 1 tCK Exit precharge power down to read command tXPRD 1 tCK 5 Average periodic refresh interval tREF — 7.8 µs 4 Notes: 1 Notes 2. 3. 4. 5. 6. L EO tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic Low. If a previous write was in progress, DQS could be High, Low, or transitioning from High to Low at this time, depending on tDQSS. A maximum of eight auto refresh commands can be posted to any given DDR SDRAM device. tXPRD should be 200 tCK in the condition of the unstable CK operation during the power down mode. For command/address and CK and /CK slew rate ≥ 1.0V/ns. t uc od Pr Preliminary Data Sheet E0390E10 (Ver. 1.0) 12 EBD25UC8AAFA-6B Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. EO /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. L A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. [Bank Select Signal Table] Bank 0 BA0 BA1 L L H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. L od Bank 1 Pr BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) H H t uc CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input). Preliminary Data Sheet E0390E10 (Ver. 1.0) 13 EBD25UC8AAFA-6B DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins) 2.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. EO Detailed Operation Part and Timing Waveforms Refer to M2S56D20/30/40ATP datasheet. L t uc od Pr Preliminary Data Sheet E0390E10 (Ver. 1.0) 14 EBD25UC8AAFA-6B Physical Outline Unit: mm 3.18max 4.00 min (DATUM -A-) (64.48) 2.30 Component area (Front) 1 92 EO B 64.77 A 1.27 ± 0.10 49.53 133.35 128.95 2.50 ± 0.20 31.75 3.00 Detail B (DATUM -A-) 1.27 6.62 2.175 R 0.90 od 0.20 ± 0.15 4.00 Detail A (Back) Pr R 2.00 184 17.80 L 93 10.00 2 – φ 2.50 1.00 ± 0.05 3.80 6.35 1.80 ± 0.10 ECA-TS2-0094-01 t uc Preliminary Data Sheet E0390E10 (Ver. 1.0) 15 EBD25UC8AAFA-6B CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 EO NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES L Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES 3 od Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES t uc Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0390E10 (Ver. 1.0) 16 EBD25UC8AAFA-6B The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. M01E0107 t uc od Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0390E10 (Ver. 1.0) 17