DATA SHEET 4GB Registered DDR3 SDRAM DIMM EBJ42HE8BAFA (512M words × 72 bits, 4 Ranks) Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 4 ranks • Mounting 36 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.5mm (max.) Lead pitch: 1.0mm Lead-free (RoHS compliant) • Power supply: VDD = 1.5V ± 0.075V • Data rate: 1066Mbps/800Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_15 • Burst lengths (BL): 8 and 4 with Burst Chop (BC) • /CAS Latency (CL): 6, 7, 8 • /CAS write latency (CWL): 5, 6 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • On-Die-Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT • Multi Purpose Register (MPR) for temperature read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • /RESET pin for Power-up sequence and reset function • SRT range: Normal/extended Auto/manual self-refresh • Programmable Output driver impedance control • 1 piece of registering clock driver and 1 piece of serial EEPROM (256 bytes EEPROM) for Presence Detect (PD). • Class B temperature sensor functionality with EEPROM Note: Warranty void if removed DIMM heat spreader. Document No. E1412E20 (Ver. 2.0) Date Published December 2008 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008 EBJ42HE8BAFA Ordering Information Part number Data rate Mbps(max.) Component 1 JEDEC speed bin* (CL-tRCD-tRP) EBJ42HE8BAFA-AE-E 1066 DDR3-1066F (7-7-7) EBJ42HE8BAFA-8C-E 800 DDR3-800E (6-6-6) Note: 1. Module /CAS latency = component CL + 1. Data Sheet E1412E20 (Ver. 2.0) 2 Package 240-pin DIMM (lead-free) Contact pad Gold Mounted devices EDJ1108BASE-DG-E EDJ1108BASE-DJ-E EDJ1108BASE-AE-E EDJ1108BASE-DG-E EDJ1108BASE-DJ-E EDJ1108BASE-AE-E EDJ1108BASE-AG-E EDJ1108BASE-8A-E EDJ1108BASE-8C-E EBJ42HE8BAFA Pin Configurations Front side 1 pin 121 pin 48 pin 49 pin 120 pin 168 pin 169 pin 240 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREFDQ 61 A2 121 VSS 181 A1 2 VSS 62 VDD 122 DQ4 182 VDD 3 DQ0 63 CK1 123 DQ5 183 VDD 4 DQ1 64 /CK1 124 VSS 184 CK0 5 VSS 65 VDD 125 DM0/TDQS9 185 /CK0 6 /DQS0 66 VDD 126 NU/ /TDQS9 186 VDD 7 DQS0 67 VREFCA 127 VSS 187 /EVENT 8 VSS 68 Par_In 128 DQ6 188 A0 9 DQ2 69 VDD 129 DQ7 189 VDD 10 DQ3 70 A10(AP) 130 VSS 190 BA1 11 VSS 71 BA0 131 DQ12 191 VDD 12 DQ8 72 VDD 132 DQ13 192 /RAS 13 DQ9 73 /WE 133 VSS 193 /CS0 14 VSS 74 /CAS 134 DM1/TDQS10 194 VDD 15 /DQS1 75 VDD 135 NU/ /TDQS10 195 ODT0 16 DQS1 76 /CS1 136 VSS 196 A13 17 VSS 77 ODT1 137 DQ14 197 VDD 18 DQ10 78 VDD 138 DQ15 198 /CS3 19 DQ11 79 /CS2 139 VSS 199 VSS 20 VSS 80 VSS 140 DQ20 200 DQ36 21 DQ16 81 DQ32 141 DQ21 201 DQ37 22 DQ17 82 DQ33 142 VSS 202 VSS 23 VSS 83 VSS 143 DM2/TDQS11 203 DM4/TDQS13 24 /DQS2 84 /DQS4 144 NU/ /TDQS11 204 NU/ /TDQS13 25 DQS2 85 DQS4 145 VSS 205 VSS 26 VSS 86 VSS 146 DQ22 206 DQ38 27 DQ18 87 DQ34 147 DQ23 207 DQ39 28 DQ19 88 DQ35 148 VSS 208 VSS 29 VSS 89 VSS 149 DQ28 209 DQ44 30 DQ24 90 DQ40 150 DQ29 210 DQ45 31 DQ25 91 DQ41 151 VSS 211 VSS 32 VSS 92 VSS 152 DM3/TDQS12 212 DM5/TDQS14 33 /DQS3 93 /DQS5 153 NU/ /TDQS12 213 NU/ /TDQS14 34 DQS3 94 DQS5 154 VSS 214 VSS 35 VSS 95 VSS 155 DQ30 215 DQ46 36 DQ26 96 DQ42 156 DQ31 216 DQ47 Data Sheet E1412E20 (Ver. 2.0) 3 EBJ42HE8BAFA Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 37 DQ27 97 DQ43 157 VSS 217 VSS 38 VSS 98 VSS 158 CB4 218 DQ52 39 CB0 99 DQ48 159 CB5 219 DQ53 40 CB1 100 DQ49 160 VSS 220 VSS 41 VSS 101 VSS 161 DM8/TDQS17 221 DM6/TDQS15 42 /DQS8 102 /DQS6 162 NU/ /TDQS17 222 NU/ /TDQS15 43 DQS8 103 DQS6 163 VSS 223 VSS 44 VSS 104 VSS 164 CB6 224 DQ54 45 CB2 105 DQ50 165 CB7 225 DQ55 46 CB3 106 DQ51 166 VSS 226 VSS 47 VSS 107 VSS 167 NC 227 DQ60 48 VTT 108 DQ56 168 /RESET 228 DQ61 49 VTT 109 DQ57 169 CKE1 229 VSS 50 CKE0 110 VSS 170 VDD 230 DM7/TDQS16 51 VDD 111 /DQS7 171 A15 231 NU/ /TDQS16 52 BA2 112 DQS7 172 A14 232 VSS 53 /Err_Out 113 VSS 173 VDD 233 DQ62 54 VDD 114 DQ58 174 A12 234 DQ63 55 A11 115 DQ59 175 A9 235 VSS 56 A7 116 VSS 176 VDD 236 VDDSPD 57 VDD 117 SA0 177 A8 237 SA1 58 A5 118 SCL 178 A6 238 SDA 59 A4 119 SA2 179 VDD 239 VSS 60 VDD 120 VTT 180 A3 240 VTT Data Sheet E1412E20 (Ver. 2.0) 4 EBJ42HE8BAFA Pin Description Pin name Function A0 to A15 Address input Row address Column address A10 (AP) Auto precharge A0 to A13 A0 to A9 A12 (/BC) Burst chop BA0, BA1, BA2 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0 to /CS3 Chip select CKE0, CKE1 Clock enable CK0, CK1 Clock input /CK0, /CK1 Differential clock input DQS0 to DQS8, /DQS0 to /DQS8 Input and output data strobe TDQS9 to TDQS17, /TDQS9 to /TDQS17 Termination data strobe DM0 to DM8 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0, SA1, SA2 Serial address input VDD Power for internal circuit VDDSPD Power for serial EEPROM VREFCA Reference voltage for CA VREFDQ Reference voltage for DQ VSS Ground VTT Termination Voltage /RESET Set DRAM to known state ODT0, ODT1 ODT control Par_In Parity bit for the Address and Control bus /Err_Out Parity error found on the Address and Control bus /Event Temperature event pin NC No connection NU Not usable Data Sheet E1412E20 (Ver. 2.0) 5 EBJ42HE8BAFA Serial PD Matrix Byte No. Function described 0 Number of serial PD bytes written/SPD device size/CRC coverage Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 1 0 1 176/256/0-116 0 0 0 1 0 92H 1 SPD revision 0 0 0 1 0 0 0 0 10H Revision 1.0 2 Key byte/DRAM device type 0 0 0 0 1 0 1 1 0BH DDR3 SDRAM 3 Key byte/module type 0 0 0 0 0 0 0 1 01H Registered 4 SDRAM density and banks 0 0 0 0 0 0 1 0 02H 1G bits, 8 banks 5 SDRAM addressing 0 0 0 1 0 0 0 1 11H 14 rows, 10 columns 6 Module nominal voltage, VDD 0 0 0 0 0 0 0 0 00H 1.5V 7 Module organization 0 0 0 1 1 0 0 1 19H 4 ranks/×8 bits 8 Module memory bus width 0 0 0 0 1 0 1 1 0BH 72 bits/ECC 9 Fine timebase (FTB) dividend/divisor 0 1 0 1 0 0 1 0 52H 5/2 10 Medium timebase (MTB) dividend 0 0 0 0 0 0 0 1 01H 1 11 Medium timebase (MTB) divisor 0 0 0 0 1 0 0 0 08H 8 12 SDRAM minimum cycle time (tCK (min.)) -AE 0 0 0 0 1 1 1 1 0FH 1.875ns 0 0 0 1 0 1 0 0 14H 2.5ns -8C 13 Reserved 0 0 0 0 0 0 0 0 00H — 14 SDRAM /CAS latencies supported, LSB -AE 0 0 0 1 1 1 0 0 1CH CL = 6, 7, 8 0 0 0 0 0 1 0 0 04H CL = 6 15 SDRAM /CAS latencies supported, MSB 0 0 0 0 0 0 0 0 00H — 16 SDRAM minimum /CAS latencies time (tAA (min.)) -AE 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 1 1 0 0 0 78H 15ns -8C -8C 17 SDRAM write recovery time (tWR) 0 1 1 1 1 0 0 0 78H 15ns 18 SDRAM minimum /RAS to /CAS delay (tRCD) -AE 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 1 1 0 0 0 78H 15ns 19 SDRAM minimum row active to row active delay (tRRD) 0 -AE 0 1 1 1 1 0 0 3CH 7.5ns 0 1 0 1 0 0 0 0 50H 10ns 20 SDRAM minimum row precharge time (tRP) -AE 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 1 1 0 0 0 78H 15ns 0 0 0 1 0 0 0 1 11H 0 1 0 1 1 0 0 2CH 37.5ns 0 0 1 0 1 0 1 95H 50.625ns 1 0 1 0 0 1 0 0 A4H 52.5ns 0 1 1 1 0 0 0 0 70H 110ns -8C -8C -8C 21 22 23 SDRAM upper nibbles for tRAS and tRC SDRAM minimum active to precharge time 0 (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB 1 -AE -8C 24 SDRAM minimum refresh recovery time delay (tRFC), LSB Data Sheet E1412E20 (Ver. 2.0) 6 EBJ42HE8BAFA Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal write to read command delay (tWTR) SDRAM minimum internal read to precharge command delay (tRTP) 0 0 0 0 0 0 1 1 03H 110ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 1 1 1 1 0 0 3CH 7.5ns 28 Upper nibble for tFAW 0 0 0 0 0 0 0 1 01H 37.5ns 29 Minimum four activate window delay time (tFAW) -AE 0 0 1 0 1 1 0 0 2CH 37.5ns 0 1 0 0 0 0 0 0 40H 40ns 30 SDRAM output drivers supported 1 0 0 0 0 0 1 1 83H DLL-off, RZQ/6, 7 31 SDRAM refresh options 1 0 0 0 0 0 0 1 81H PASR/2X refresh rate at +85°C to +95°C 32 Module thermal sensor 1 0 0 0 0 0 0 0 80H Incorporated 33 SDRAM device type 0 0 0 0 0 0 0 0 00H Standard 25 26 27 -8C 34 to 59 Reserved 0 0 0 0 0 0 0 0 00H — 60 Module nominal height 0 0 0 1 0 0 0 0 10H 30 < height ≤ 31mm 61 Module maximum thickness 0 0 1 1 0 0 1 1 33H 62 Reference raw card used 0 0 0 0 0 1 1 1 07H Raw card H 63 DIMM module attributes 0 0 0 0 1 0 0 1 09H 2row/1register 64 Heat spreader solution 1 0 0 0 0 0 0 0 80H Incorporated 65 Register vender ID (LSB) (Inphi) 0 0 0 0 0 1 0 0 04H Naming bank = 5 1 0 0 0 0 0 0 0 80H Naming bank = 1 66 Register vender ID (MSB) (Inphi) 1 0 1 1 0 0 1 1 B3H Actual ID 1 0 0 1 0 1 1 1 97H 67 Register revision (Inphi) 0 0 0 0 0 0 1 1 03H 0 0 0 1 1 1 0 1 1DH Rev.3.1 68 Register type 0 0 0 0 0 0 0 0 00H SSTE32882 69 Register control word function (RC0, 1) 0 0 0 0 0 0 0 0 00H Default 70 Register control word function (RC2, 3) 0 1 0 1 0 0 0 0 50H Default 71 Register control word function (RC4, 5) 0 1 0 1 0 1 0 1 55H Default 72 Register control word function (RC6, 7) 0 0 0 0 0 0 0 0 00H Default 73 Register control word function (RC8, 9) 0 0 0 0 0 0 0 0 00H Default 74 Register control word function (RC10, 11) 0 0 0 0 0 0 0 0 00H Default 75 Register control word function (RC12, 13) 0 0 0 0 0 0 0 0 00H Default 76 Register control word function (RC14, 15) 0 0 0 0 0 0 0 0 00H Default 77 to 116 Module specific section 0 0 0 0 0 0 0 00H — (TI) (TI) (TI) 0 Data Sheet E1412E20 (Ver. 2.0) 7 Rev.4 EBJ42HE8BAFA Byte No. Function described 117 118 Module ID: manufacturer’s JEDEC ID code, LSB Module ID: manufacturer’s JEDEC ID code, MSB Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 0 0 0 0 0 0 1 0 02H Elpida Memory 1 1 1 1 1 1 1 0 FEH Elpida Memory 119 Module ID: manufacturing location × × × × × × × × ×× 120 Module ID: manufacturing date × × × × × × × × ×× Year code (BCD) 121 Module ID: manufacturing date × × × × × × × × ×× Week code (BCD) 122 to 125 Module ID: module serial number × × × × × × × × ×× 126 Cyclical redundancy code (CRC) -AE (Inphi) 1 0 0 1 0 0 1 0 92H 0 0 0 0 1 1 0 1 0DH -8C (Inphi) 0 0 0 0 1 0 1 0 0AH (TI) 1 0 0 1 0 1 0 1 95H 0 0 0 1 0 0 1 1 13H (TI) 127 Cyclical redundancy code (CRC) -AE (Inphi) (TI) -8C (Inphi) (TI) 0 1 1 0 1 1 1 0 6EH 0 1 0 0 1 0 1 0 4AH 0 0 1 1 0 1 1 1 37H 128 Module part number 0 1 0 0 0 1 0 1 45H E 129 Module part number 0 1 0 0 0 0 1 0 42H B 130 Module part number 0 1 0 0 1 0 1 0 4AH J 131 Module part number 0 0 1 1 0 1 0 0 34H 4 132 Module part number 0 0 1 1 0 0 1 0 32H 2 133 Module part number 0 1 0 0 1 0 0 0 48H H 134 Module part number 0 1 0 0 0 1 0 1 45H E 135 Module part number 0 0 1 1 1 0 0 0 38H 8 136 Module part number 0 1 0 0 0 0 1 0 42H B 137 Module part number 0 1 0 0 0 0 0 1 41H A 138 Module part number 0 1 0 0 0 1 1 0 46H F 139 Module part number 0 1 0 0 0 0 0 1 41H A 140 Module part number 0 0 1 0 1 1 0 1 2DH — 141 Module part number -AE 0 1 0 0 0 0 0 1 41H A 0 0 1 1 1 0 0 0 38H 8 142 Module part number -AE 0 1 0 0 0 1 0 1 45H E 0 1 0 0 0 0 1 1 43H C 143 Module part number 0 0 1 0 1 1 0 1 2DH — 144 Module part number 0 1 0 0 0 1 0 1 45H E -8C -8C Data Sheet E1412E20 (Ver. 2.0) 8 EBJ42HE8BAFA Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 145 0 1 0 (Space) Module part number 0 0 0 0 0 20H 146 Module revision code 0 0 1 1 0 0 0 0 30H Initial 147 Module revision code 0 0 1 0 0 0 0 0 20H (Space) 0 0 0 0 0 0 1 0 02H Elpida Memory 1 1 1 1 1 1 1 0 FEH Elpida Memory 0 0 0 0 0 0 0 0 00H 148 149 150 to 175 176 to 255 SDRAM manufacturer’s JEDEC ID code, LSB SDRAM manufacturer’s JEDEC ID code, MSB Manufacturer's specific data Open for customer use Data Sheet E1412E20 (Ver. 2.0) 9 EBJ42HE8BAFA 3 PCK1_A /PCK1_A RCKE1_A VDD /RCS3 /RCS2 PCK1_A /PCK1_A RCKE0_A RODT1_A PCK0_A /PCK0_A RCKE1_A VDD Data Sheet E1412E20 (Ver. 2.0) 10 /CS Command CK /CK CKE ODT Address BA ODT Address BA /CS Command CK /CK CKE DQS /DQS D28 /CS Command CK /CK CKE ODT Rs5 ODT Address BA /TDQS DQ0 to DQ7 ZQ TDQS D27 ZQ VTT Address BA TDQS VTT Address BA /DQS D29 /CS Command CK /CK CKE ODT DQS ODT Address BA /CS Command CK /CK CKE Rs5 Rs5 Rs5 /TDQS DQ0 to DQ7 ZQ /TDQS DQ0 to DQ7 VTT Rs4 Block Diagram (1) TDQS ODT Address BA /CS Command CK /CK CKE VTT D30 Rs3 VTT /DQS Rs3 VTT /TDQS DQ0 to DQ7 ZQ DQS D18 ZQ D35 TDQS ODT Address BA /CS Command CK /CK CKE Rs5 TDQS Rs4 ODT Address BA /CS Command CK /CK CKE Rs5 ODT Address BA /DQS /TDQS DQ0 to DQ7 ZQ /DQS D19 ZQ DQS D9 ODT Address BA /CS Command CK /CK CKE /CS Command CK /CK CKE ODT Address BA TDQS Rs5 Rs3 Rs3 Rs3 Rs3 Rs3 /DQS TDQS DQ0 to DQ7 VTT VTT D10 ZQ DQS D0 /TDQS DQ0 to DQ7 /TDQS DQ0 to DQ7 ZQ DQS Rs5 /TDQS 8 RS1 DQ0 DQ0 to DQ7 to DQ7 ZQ TDQS Rs3 Rs5 TDQS /DQS Rs3 RS1 /DQS Rs5 /TDQS9 RS1 DQS DQS TDQS D20 Rs3 DM0/TDQS9 RS1 ZQ /TDQS DQ0 to DQ7 ZQ /CS Command CK /CK CKE /DQS0 RS1 D1 TDQS D11 TDQS /TDQS DQ0 to DQ7 /CS Command CK /CK CKE DQS0 /DQS /DQS /DQS D21 Rs3 /TDQS RS1 DQ0 DQ8 to DQ15 8 to DQ7 DQS DQS Rs5 Rs5 TDQS /TDQS DQ0 to DQ7 ZQ /TDQS DQ0 to DQ7 ZQ Rs3 /DQS TDQS ODT Address BA RS1 Rs5 /TDQS10 RS1 DQS /DQS ODT Address BA DM1/TDQS10 RS1 /CS Command CK /CK CKE /DQS1 RS1 DQS D2 Rs5 DQS1 ZQ Rs5 /TDQS 8 RS1 DQ0 DQ16 to DQ23 to DQ7 ZQ /TDQS11 /RCS1 Rs5 TDQS D12 DQS D26 TDQS Rs5 RS1 /DQS /DQS ODT Address BA RS1 DQS ODT Address BA DM2/TDQS11 RS1 /CS Command CK /CK CKE /DQS2 RS1 /TDQS DQ0 to DQ7 D3 Rs5 DQS2 TDQS DQS ODT Address BA /TDQS 8 RS1 DQ0 DQ24 to DQ31 to DQ7 ZQ /DQS ODT Address BA TDQS DQS D17 /CS Command CK /CK CKE RS1 /DQS /TDQS DQ0 to DQ7 ZQ Rs3 /TDQS12 RS1 DQS /TDQS DQ0 to DQ7 ZQ /CS Command CK /CK CKE DM3/TDQS12 RS1 /DQS TDQS /CS Command CK /CK CKE /DQS3 RS1 D8 DQ0 to DQ7 ZQ DQS TDQS /CS Command CK /CK CKE DQS3 /DQS Rs3 RS1 /TDQS DQS Rs5 8 Rs5 CB0 to CB7 TDQS ODT Address BA RS1 /TDQS17 /DQS ODT Address BA RS1 DM8/TDQS17 DQS /CS Command CK /CK CKE RS1 /DQS8 17 /CS Command CK /CK CKE RS1 DQS8 R[Address, BA]_A RCKE0_A RODT0_A /RCS0 Rcommand_A PCK0_A /PCK0_A Block Diagram 3 /RCS3 PCK1_B /PCK1_B RCKE1_B VDD PCK1_B /PCK1_B RCKE0_B RODT1_B /RCS2 PCK0_B /PCK0_B RCKE0_B VDD Data Sheet E1412E20 (Ver. 2.0) 11 /DQS TDQS D34 Rs3 VTT DQ0 to DQ7 ZQ VTT VTT ODT Address BA Address BA DQS D33 /CS Command CK /CK CKE ODT Rs5 ODT Address BA /TDQS DQ0 to DQ7 ZQ ODT Address BA /CS Command CK /CK CKE TDQS Rs5 VTT Rs4 Block Diagram (2) D32 /TDQS Rs3 VTT /CS Command CK /CK CKE Rs5 /DQS D25 DQ0 to DQ7 ZQ Rs3 VTT Rs4 /TDQS DQ0 to DQ7 ZQ DQS /TDQS D16 D31 TDQS D24 TDQS /CS Command CK /CK CKE ODT Address BA ODT Address BA ODT Address BA /DQS Rs5 Rs5 /DQS /TDQS DQ0 to DQ7 ZQ DQS ODT Address BA /CS Command CK /CK CKE /TDQS DQ0 to DQ7 ZQ DQS TDQS Rs3 VTT VTT DQ0 to DQ7 ZQ /CS Command CK /CK CKE Rs5 ODT Address BA D15 TDQS D7 /CS Command CK /CK CKE /CS Command CK /CK CKE ODT Address BA TDQS /TDQS DQ0 to DQ7 ZQ Rs3 /DQS Rs3 ODT Address BA /DQS Rs5 RS1 /TDQS DQ0 to DQ7 ZQ DQS /TDQS Rs3 8 Rs5 DQ56 to DQ63 TDQS Rs3 RS1 /TDQS16 /DQS Rs3 RS1 DM7/TDQS16 DQS /CS Command CK /CK CKE RS1 /DQS7 /RCS1 D6 Rs3 RS1 DQS7 TDQS DQS /DQS D23 /CS Command CK /CK CKE /TDQS 8 RS1 DQ0 to DQ7 ZQ /DQS /TDQS DQ0 to DQ7 ZQ Rs3 RS1 Rs5 DQ48 to DQ55 TDQS DQS Rs5 /TDQS15 /DQS D14 DQS D22 TDQS Rs3 RS1 DM6/TDQS15 DQS /TDQS DQ0 to DQ7 ZQ /DQS Rs5 /DQS6 TDQS DQS Rs5 RS1 ZQ D13 ODT Address BA RS1 DQS6 /DQS D5 DQ0 to DQ7 /TDQS DQ0 to DQ7 ZQ ODT Address BA RS1 /TDQS /TDQS DQ0 to DQ7 ZQ Rs3 8 Rs5 DQ40 to DQ47 TDQS /DQS TDQS DQS Rs5 RS1 /TDQS14 /DQS ODT Address BA RS1 DM5/TDQS14 DQS ODT Address BA /DQS5 /CS Command CK /CK CKE RS1 DQS TDQS /CS Command CK /CK CKE D4 /CS Command CK /CK CKE RS1 DQS5 /DQS /CS Command CK /CK CKE /TDQS 8 RS1 DQ0 to DQ7 ZQ Rs5 DQ32 to DQ39 RS1 TDQS DQS Rs5 /TDQS13 /DQS /CS Command CK /CK CKE RS1 DM4/TDQS13 DQS Rs3 /DQS4 ODT Address BA RS1 17 /CS Command CK /CK CKE RS1 DQS4 R[Address, BA]_B RCKE0_B RODT0_B /RCS0 Rcommand_B PCK1_B /PCK1_B EBJ42HE8BAFA EBJ42HE8BAFA /CS0 /CS1 /CS2 /CS3 BA Address Rs2 /RCS0 -> /CS: SDRAMs D0 to D8 Rs2 1:2 /RCS1 -> /CS: SDRAMs D9 to D17 Rs2 /RCS2 -> /CS: SDRAMs D18 to D26 Rs2 /RCS3 -> /CS: SDRAMs D27 to D35 RBA_A -> BA0 to BA2: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 RBA_B -> BA0 to BA2: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 Rs2 Rs2 RAddress_A -> A0 to A13: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 RAddress_B -> A0 to A13: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 Rcommand_A -> /RAS, /CAS, /WE: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 Rcommand_B -> /RAS, /CAS, /WE: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 Rs2 Command CKE0 CKE1 ODT0 ODT1 Rs2 RCKE0_A -> CKE: SDRAMs D0 to D3, D8, D18 to D21, D26 RCKE0_B -> CKE: SDRAMs D4 to D7, D22 to D25 R E G I S T E R Rs2 Rs2 Rs2 RODT0_A -> ODT: SDRAMs D0 to D3, D8 RODT0_B-> ODT: SDRAMs D4 to D7 / RODT1_A -> ODT: SDRAMs D18 to D21, D26 RODT1_B -> ODT: SDRAMs D22 to D25 P L L PCK0_A -> CK: SDRAMs D0 to D3, D8 to D12, D17 PCK0_B -> CK: SDRAMs D4 to D7, D13 to D16 PCK1_A -> CK: SDRAMs D18 to D21, D26 to D30, D35 PCK1_B -> CK: SDRAMs D22 to D25, D31 to D34 Rs4 CK0 RCKE1_A -> CKE: SDRAMs D9 to D12, D17, D27 to D30, D35 RCKE1_B -> CKE: SDRAMs D13 to D16, D31 to D34 /PCK0_A -> CK: SDRAMs D0 to D3, D8 to D12, D17 /PCK0_B -> CK: SDRAMs D4 to D7, D13 to D16 /CK0 Par_In Rs2 /RESET Note: 1. DQ wiring may be changed within a byte. /PCK1_A -> CK: SDRAMs D18 to D21, D26 to D30, D35 /PCK1_B -> CK: SDRAMs D22 to D25, D31 to D34 /Err_Out /RESET * D0 to D35: 1G bits DDR3 SDRAM Address, BA: A0 to A15, BA0 to BA2 Command: /RAS, /CAS, /WE U1: 256 bytes EEPROM Rs1: 15Ω Rs2: 22Ω Rs3: 47Ω Rs4: 120Ω Rs5: 240Ω Register: SSTE32882 /RESET: SDRAMs D0 to D35 RS 4 CK1 /CK1 VTT VDDSPD VREFCA VREFDQ VDD VSS Terminated at near card edge SPD SDRAMs (D0 to D35) SDRAMs (D0 to D35) SDRAMs (D0 to D35) SCL SCL SA0 A0 SDRAMs (D0 to D35), SPD SA1 SA2 A1 A2 /EVENT Serial PD SDA SDA U1 D10 D11 D12 D17 D13 D14 D15 D16 VTT D27 D27 D28 D29 D30 D35 D31 D32 D33 D34 VTT VTT D18 D19 D20 D21 D26 D22 D23 D24 D25 VTT D0 D1 D2 D3 D8 D4 D5 D6 D7 VTT Register Address, command and control line Block Diagram (3) Data Sheet E1412E20 (Ver. 2.0) 12 VTT VTT D9 VTT /EVENT EBJ42HE8BAFA Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Notes Power supply voltage VDD −0.4 to +1.975 V 1, 3, 4 Input voltage VIN −0.4 to +1.975 V 1, 4 Output voltage VOUT −0.4 to +1.975 V 1, 4 Reference voltage VREFCA −0.4 to 0.6 × VDD V 3, 4 Reference voltage for DQ VREFDQ −0.4 to 0.6 × VDDQ V 3, 4 1, 2, 4 Storage temperature Tstg −55 to +100 °C Power dissipation PD 9 W Short circuit output current IOUT 50 mA 1, 4 Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 × VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4. DDR3 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC 0 to +95 °C 1, 2, 3 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). Data Sheet E1412E20 (Ver. 2.0) 13 EBJ42HE8BAFA Recommended DC Operating Conditions (TC = 0°C to +85°C) Parameter Symbol min. typ. max. Unit Notes Supply voltage VDD, VDDQ 1.425 1.5 1.575 V 1, 2, 3 VSS 0 0 0 V 1 3.6 VDDSPD 3.0 3.3 Input reference voltage VREFCA (DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 4, 5 Input reference voltage for DQ VREFDQ (DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 4, 5 Termination voltage VTT VDDQ/2 – TBD TBD V Notes: 1. 2. 3. 4. VDDQ/2 + TBD V DDR3 SDRAM component specification. Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx ±15 mV). 5. For reference: approx. VDD/2 ±15 mV. Data Sheet E1412E20 (Ver. 2.0) 14 EBJ42HE8BAFA DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.5V ± 0.075V, VSS = 0V) Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Symbol IDD0 IDD1 IDD2PF Precharge power-down standby current IDD2PS Precharge quiet standby current IDD2Q Precharge standby current IDD2N Active power-down current (Always fast exit) IDD3P Active standby current IDD3N Operating current (Burst read operating) Operating current (Burst write operating) IDD4R IDD4W Burst refresh current IDD5B Self-refresh current normal temperature range IDD6 All bank interleave read current IDD7R Data rate (Mbps) max. 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 1066 800 2260 2040 2470 2260 1520 1400 1320 1230 2020 1820 2020 1820 1470 1360 2050 1820 2970 2320 3140 2510 3910 3740 1066 800 Data Sheet E1412E20 (Ver. 2.0) 15 Unit Notes mA mA mA Fast PD Exit mA Slow PD Exit mA mA mA mA mA mA mA 1300 mA 3820 3490 mA EBJ42HE8BAFA AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. Parameter DDR3-1066 DDR3-800 7-7-7 6-6-6 Unit CL (IDD) 7 6 tCK tCK min.(IDD) 1.875 2.5 ns tRCD min. (IDD) 13.13 15 ns tRC min. (IDD) 50.63 52.5 ns tRAS min.(IDD) 37.5 37.5 ns tRP min. (IDD) 13.13 15 ns tFAW (IDD) 37.5 40 ns tRRD (IDD) 7.5 10 ns tRFC (IDD) 110 110 ns DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) (DDR3 SDRAM Component Specification) Parameter Symbol Value Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO 5 µA DDQ ≥ VOUT ≥ VSS Data Sheet E1412E20 (Ver. 2.0) 16 Unit Notes EBJ42HE8BAFA Pin Functions CK, /CK (input pin) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A15 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table] Address (A0 to A13) Row address (RA) Column address (CA) AX0 to AX13 AY0 to AY9 Notes A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12 (/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine if a mode register is to be accessed during a MRS cycle. [Bank Select Signal Table] BA0 BA1 BA2 Bank 0 L L L Bank 1 H L L Bank 2 L H L Bank 3 H H L Bank 4 L L H Bank 5 H L H Bank 6 L H H Bank 7 H H H Remark: H: VIH. L: VIL. Data Sheet E1412E20 (Ver. 2.0) 17 EBJ42HE8BAFA CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DQ and CB (input and output pins) Bi-directional data bus. DQS and /DQS (input and output pin) Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during READs and WRITEs. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. DM (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a write access. DM is sampled on both edges of DQS. For ×8 configuration, the function of DM or TDQS, /TDQS is enabled by mode register A11 setting in MR1. TDQS, /TDQS (output pins) TDQS and /TDQS is applicable for ×8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM will enable the same termination resistance function on TDQS, /TDQS that is applied to DQS, /DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and /TDQS is not used. ×4/×16 configuration must be disabled the TDQS function via mode register A11 = 0 in MR1. VDD (power supply pins) 1.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 3.3V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. VTT (power supply pin) Termination supply. VREFDQ (power supply) Reference voltage for DQ. VREFCA (power supply) Reference voltage for CA. SCL (input pin) Clock input for serial PD. Data Sheet E1412E20 (Ver. 2.0) 18 EBJ42HE8BAFA SDA (input and output pins) Data input/output for serial PD. SA (input pin) Serial address input. /RESET (input pin) /RESET is negative active signal (active low) and is referred to GND. Par_In (input pin) Parity bit for the Address and Control bus. /Err_Out (output pin) Parity error found on the Address and Control bus. /Event (output pin) Temperature alert output. Detailed Operation Part, Electrical Characteristics and Timing Waveforms Refer to the EDJ1104BASE, EDJ1108BASE, EDJ1116BASE datasheet (E1128E). DIMM /CAS latency = component CL + 1 for registered type. Data Sheet E1412E20 (Ver. 2.0) 19 EBJ42HE8BAFA Physical Outline Unit: mm Front side 8.50 max (DATUM -A-) 4.00 min (Front) 1 120 B A 47.00 1.27 ± 0.10 71.00 133.35 (Back) 30.50 max 240 17.30 121 9.50 Back side C ± ± ± ± ± ECA-TS2-0245-02 Data Sheet E1412E20 (Ver. 2.0) 20 EBJ42HE8BAFA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E1412E20 (Ver. 2.0) 21 EBJ42HE8BAFA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0706 Data Sheet E1412E20 (Ver. 2.0) 22