PRELIMINARY DATA SHEET 1GB DDR3 SDRAM SO-DIMM EBJ10UE8BDS0 (128M words × 64 bits, 1 Rank) Specifications Features • Density: 1GB • Organization 128M words × 64 bits, 1 rank • Mounting 8 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 30.0mm Lead pitch: 0.6mm Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD = 1.5V ± 0.075V • Data rate: 1600Mbps/1333Mbps/1066Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_15 • Burst lengths (BL): 8 and 4 with Burst Chop (BC) • /CAS Latency (CL): 6, 7, 8, 9, 10, 11 • /CAS write latency (CWL): 5, 6, 7, 8 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • On-Die-Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT • Multi Purpose Register (MPR) for temperature read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • /RESET pin for Power-up sequence and reset function • SRT range: Normal/extended • Programmable Output driver impedance control Document No. E1512E10 (Ver. 1.0) Date Published June 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2009 EBJ10UE8BDS0 Ordering Information Part number Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) EBJ10UE8BDS0-GN-F 1600 DDR3-1600K (11-11-11) EBJ10UE8BDS0-DJ-F 1333 DDR3-1333H (9-9-9) EBJ10UE8BDS0-AE-F 1066 DDR3-1066F (7-7-7) Package Preliminary Data Sheet E1512E10 (Ver. 1.0) 2 Contact pad 204-pin SO-DIMM Gold (lead-free and halogen-free) Mounted devices EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-DJ-F EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-DJ-F EDJ1108BDSE-AE-F EBJ10UE8BDS0 Pin Configurations Front side 1 pin 71 pin 73 pin 203 pin 2 pin 72 pin 74 pin 204 pin Back side Front side Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREFDQ 103 /CK0 2 VSS 104 /CK1 3 VSS 105 VDD 4 DQ4 106 VDD 5 DQ0 107 A10 (AP) 6 DQ5 108 BA1 7 DQ1 109 BA0 8 VSS 110 /RAS 9 VSS 111 VDD 10 /DQS0 112 VDD 11 DM0 113 /WE 12 DQS0 114 /CS0 13 VSS 115 /CAS 14 VSS 116 ODT0 15 DQ2 117 VDD 16 DQ6 118 VDD 17 DQ3 119 A13 18 DQ7 120 NC 19 VSS 121 NC 20 VSS 122 NC 21 DQ8 123 VDD 22 DQ12 124 VDD 23 DQ9 125 NC 24 DQ13 126 VREFCA 25 VSS 127 VSS 26 VSS 128 VSS 27 /DQS1 129 DQ32 28 DM1 130 DQ36 29 DQS1 131 DQ33 30 /RESET 132 DQ37 31 VSS 133 VSS 32 VSS 134 VSS 33 DQ10 135 /DQS4 34 DQ14 136 DM4 35 DQ11 137 DQS4 36 DQ15 138 VSS 37 VSS 139 VSS 38 VSS 140 DQ38 39 DQ16 141 DQ34 40 DQ20 142 DQ39 41 DQ17 143 DQ35 42 DQ21 144 VSS 43 VSS 145 VSS 44 VSS 146 DQ44 45 /DQS2 147 DQ40 46 DM2 148 DQ45 47 DQS2 149 DQ41 48 VSS 150 VSS 49 VSS 151 VSS 50 DQ22 152 /DQS5 51 DQ18 153 DM5 52 DQ23 154 DQS5 53 DQ19 155 VSS 54 VSS 156 VSS 55 VSS 157 DQ42 56 DQ28 158 DQ46 57 DQ24 159 DQ43 58 DQ29 160 DQ47 59 DQ25 161 VSS 60 VSS 162 VSS 61 VSS 163 DQ48 62 /DQS3 164 DQ52 63 DM3 165 DQ49 64 DQS3 166 DQ53 65 VSS 167 VSS 66 VSS 168 VSS 67 DQ26 169 /DQS6 68 DQ30 170 DM6 Preliminary Data Sheet E1512E10 (Ver. 1.0) 3 EBJ10UE8BDS0 Front side Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 69 DQ27 171 DQS6 70 DQ31 172 VSS 71 VSS 173 VSS 72 VSS 174 DQ54 73 CKE0 175 DQ50 74 NC 176 DQ55 75 VDD 177 DQ51 76 VDD 178 VSS 77 NC 179 VSS 78 NC 180 DQ60 79 BA2 181 DQ56 80 NC 182 DQ61 81 VDD 183 DQ57 82 VDD 184 VSS 83 A12 (/BC) 185 VSS 84 A11 186 /DQS7 85 A9 187 DM7 86 A7 188 DQS7 87 VDD 189 VSS 88 VDD 190 VSS 89 A8 191 DQ58 90 A6 192 DQ62 91 A5 193 DQ59 92 A4 194 DQ63 93 VDD 195 VSS 94 VDD 196 VSS 95 A3 197 SA0 96 A2 198 NC 97 A1 199 VDDSPD 98 A0 200 SDA 99 VDD 201 SA1 100 VDD 202 SCL 101 CK0 203 VTT 102 CK1 204 VTT Preliminary Data Sheet E1512E10 (Ver. 1.0) 4 EBJ10UE8BDS0 Pin Description Pin name Function A0 to A13 Address input Row address Column address A10 (AP) Auto precharge A0 to A13 A0 to A9 A12 (/BC) Burst chop BA0, BA1, BA2 Bank select address DQ0 to DQ63 Data input/output /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0 Chip select CKE0 Clock enable CK0, CK1 Clock input /CK0, /CK1 Differential clock input DQS0 to DQS7, /DQS0 to /DQS7 Input and output data strobe DM0 to DM7 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0, SA1 Serial address input VDD Power for internal circuit VDDSPD Power for serial EEPROM VREFCA Reference voltage for CA VREFDQ Reference voltage for DQ VSS Ground VTT I/O termination supply for SDRAM /RESET Set DRAM to known state ODT0 ODT control NC No connection Preliminary Data Sheet E1512E10 (Ver. 1.0) 5 EBJ10UE8BDS0 Serial PD Matrix Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 1 0 0 1 0 0 1 1 93H 256/256/0-116 -DJ, -AE 1 0 0 1 0 0 1 0 92H 176/256/0-116 SPD revision 0 0 0 1 0 0 0 0 10H Revision 1.0 2 Key byte/DRAM device type 0 0 0 0 1 0 1 1 0BH DDR3 SDRAM 3 Key byte/module type 0 0 0 0 0 0 1 1 03H SO-DIMM 4 SDRAM density and banks 0 0 0 0 0 0 1 0 02H 1G bits, 8 banks 5 SDRAM addressing 0 0 0 1 0 0 0 1 11H 14 rows, 10 columns 6 Module nominal voltage, VDD 0 0 0 0 0 0 0 0 00H 1.5V 7 Module organization 0 0 0 0 0 0 0 1 01H 1 rank/×8 bits 8 Module memory bus width 0 0 0 0 0 0 1 1 03H 64 bits/non-ECC 9 Fine timebase (FTB) dividend/divisor 0 1 0 1 0 0 1 0 52H 5/2 10 Medium timebase (MTB) dividend 0 0 0 0 0 0 0 1 01H 1 11 Medium timebase (MTB) divisor 0 0 0 0 1 0 0 0 08H 8 12 SDRAM minimum cycle time (tCK (min.)) -GN 0 0 0 0 1 0 1 0 0AH 1.25ns 0 0 0 0 1 1 0 0 0CH 1.5ns Byte No. Function described 0 1 Number of serial PD bytes written/SPD device size/CRC coverage -GN -DJ 0 0 0 0 1 1 1 1 0FH 1.875ns 13 Reserved -AE 0 0 0 0 0 0 0 0 00H — 14 SDRAM /CAS latencies supported, LSB -GN 1 0 1 1 1 1 0 0 BCH CL = 6, 7, 8, 9, 11 -DJ 0 0 1 1 1 1 0 0 3CH CL = 6, 7, 8, 9 -AE 0 0 0 1 1 1 0 0 1CH CL = 6, 7, 8 15 SDRAM /CAS latencies supported, MSB 0 0 0 0 0 0 0 0 00H — 16 SDRAM minimum /CAS latencies time (tAA (min.)) 0 1 1 0 1 0 0 1 69H 13.125ns SDRAM write recovery time (tWR (min)) 0 1 1 1 1 0 0 0 78H 15ns 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 0 0 0 0 30H 6ns 17 18 19 SDRAM minimum /RAS to /CAS delay 0 (tRCD) SDRAM minimum row active to row active delay (tRRD) 0 -GN, -DJ 0 0 1 1 1 1 0 0 3CH 7.5ns SDRAM minimum row precharge time (tRP) -AE 0 1 1 0 1 0 0 1 69H 13.125ns 21 SDRAM upper nibbles for tRAS and tRC 0 0 0 1 0 0 0 1 11H 22 SDRAM minimum active to precharge time (tRAS), LSB 0 -GN 0 0 1 1 0 0 0 18H 35ns 20 -DJ 0 0 1 0 0 0 0 0 20H 36ns -AE 0 0 1 0 1 1 0 0 2CH 37.5ns Preliminary Data Sheet E1512E10 (Ver. 1.0) 6 EBJ10UE8BDS0 Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 1 0 0 0 0 0 0 1 81H 48.125ns -DJ 1 0 0 0 1 0 0 1 89H 49.125ns -AE 1 0 0 1 0 1 0 1 95H 50.625ns 0 1 1 1 0 0 0 0 70H 110ns 0 0 0 0 0 0 1 1 03H 110ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 0 0 0 0 0 0 00H 30.0ns 0 0 0 0 0 0 0 1 01H 37.5ns 1 1 1 1 0 0 0 0 F0H 30.0ns Byte No. Function described 23 24 25 26 27 28 SDRAM minimum active to active /autorefresh time (tRC), LSB -GN SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal write to read command delay (tWTR) SDRAM minimum internal read to precharge command delay (tRTP) Upper nibble for tFAW -GN, -DJ -AE 29 Minimum four activate window delay time (tFAW) -GN, -DJ 0 0 1 0 1 1 0 0 2CH 37.5ns 30 SDRAM output drivers supported 1 0 0 0 0 0 1 1 83H DLL-off/RZQ/6, 7 31 SDRAM refresh options 1 0 0 0 0 0 0 1 81H PASR/2X refresh rate at +85°C to +95°C 32 Module thermal sensor 0 0 0 0 0 0 0 0 00H Not Incorporated 33 SDRAM device type 0 0 0 0 0 0 0 0 00H Standard -AE 34 to 59 Reserved 0 0 0 0 0 0 0 0 00H — 60 Module nominal height 0 0 0 0 1 1 1 1 0FH 29 < height ≤ 30mm 61 Module maximum thickness 0 0 0 1 0 0 0 1 11H 62 Reference raw card used 0 0 1 0 0 0 0 1 21H Raw Card B1 63 Address mapping from edge connecter to 0 DRAM 0 0 0 0 0 0 0 00H Standard 64 to 116 Module specific section 0 0 0 0 0 0 0 0 00H — 0 0 0 0 0 0 1 0 02H Elpida Memory 1 1 1 1 1 1 1 0 FEH Elpida Memory 117 118 Module ID: manufacturer’s JEDEC ID code, LSB Module ID: manufacturer’s JEDEC ID code, MSB 119 Module ID: manufacturing location × × × × × × × × ×× 120 Module ID: manufacturing date × × × × × × × × ×× Year code (BCD) 121 Module ID: manufacturing date × × × × × × × × ×× Week code (BCD) 122 to 125 Module ID: module serial number × × × × × × × × ×× 126 Cyclical redundancy code (CRC) -GN 0 0 1 1 1 1 0 0 3CH -DJ 1 0 0 1 0 1 0 0 94H -AE 1 1 0 1 0 1 1 0 D6H Preliminary Data Sheet E1512E10 (Ver. 1.0) 7 EBJ10UE8BDS0 Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 1 1 1 1 1 0 1 7DH -DJ 1 1 0 0 1 1 1 0 CEH -AE 0 1 1 0 0 1 1 1 67H Byte No. Function described 127 Cyclical redundancy code (CRC) -GN Comments 128 Module part number 0 1 0 0 0 1 0 1 45H E 129 Module part number 0 1 0 0 0 0 1 0 42H B 130 Module part number 0 1 0 0 1 0 1 0 4AH J 131 Module part number 0 0 1 1 0 0 0 1 31H 1 132 Module part number 0 0 1 1 0 0 0 0 30H 0 133 Module part number 0 1 0 1 0 1 0 1 55H U 134 Module part number 0 1 0 0 0 1 0 1 45H E 135 Module part number 0 0 1 1 1 0 0 0 38H 8 136 Module part number 0 1 0 0 0 0 1 0 42H B 137 Module part number 0 1 0 0 0 1 0 0 44H D 138 Module part number 0 1 0 1 0 0 1 1 53H S 139 Module part number 0 0 1 1 0 0 0 0 30H 0 140 Module part number 0 0 1 0 1 1 0 1 2DH — 141 Module part number -GN 0 1 0 0 0 1 1 1 47H G -DJ 0 1 0 0 0 1 0 0 44H D -AE 0 1 0 0 0 0 0 1 41H A 0 1 0 0 1 1 1 0 4EH N -DJ 0 1 0 0 1 0 1 0 4AH J -AE 0 1 0 0 0 1 0 1 45H E 142 Module part number -GN 143 Module part number 0 0 1 0 1 1 0 1 2DH — 144 Module part number 0 1 0 0 0 1 1 0 46H F 145 Module part number 0 0 1 0 0 0 0 0 20H (Space) 146 Module revision code 0 0 1 1 0 0 0 0 30H Initial 147 Module revision code 0 0 1 0 0 0 0 0 20H (Space) 0 0 0 0 0 0 1 0 02H Elpida Memory 1 1 1 1 1 1 1 0 FEH Elpida Memory 148 149 150 to 175 176 to 254 255 SDRAM manufacturer’s JEDEC ID code, LSB SDRAM manufacturer’s JEDEC ID code, MSB Manufacturer's specific data Intel extreme memory profile -GN -DJ, -AE Refer to SPD for Intel Extreme Memory Profile Section 0 0 0 Open for customer use Preliminary Data Sheet E1512E10 (Ver. 1.0) 8 0 0 0 0 0 00H Not supported EBJ10UE8BDS0 SPD for Intel Extreme Memory Profile (EBJ10UE8BDS0-GN) Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 176 Intel extreme memory profile ID string 0 0 0 0 1 1 0 0 0CH 177 Intel extreme memory profile ID string 0 1 0 0 1 0 1 0 4AH 178 Intel extreme memory profile organization type 0 0 0 0 0 0 1 1 03H Intel extreme memory profile revision 0 0 0 1 0 0 0 1 11H Revision 1.1 0 0 0 0 0 0 0 1 01H 1 0 0 0 0 1 0 0 0 08H 8 0 0 0 0 0 0 0 1 01H 1 0 0 0 0 1 0 0 0 08H 8 0 0 0 0 0 0 0 0 00H 179 180 181 182 183 184 Medium timebase (MTB) dividend for profile 1 Medium timebase (MTB) divisor for profile 1 Medium timebase (MTB) dividend for profile 2 Medium timebase (MTB) divisor for profile 2 Reserved for global byte Comments Intel Extreme Memory Profile ID String Intel Extreme Memory Profile ID String Profile 1: Enabled / Profile 2: Enabled / Profile 1: 1 DIMM per CH / Profile 2: 1 DIMM per CH / [For Profile 1] Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 185 0 0 1 0 1 0 1 0 2AH 1.50V 0 0 0 0 1 0 1 0 0AH DDR3-1600 0 1 1 0 1 0 0 1 69H 13.125ns 1 0 1 1 1 1 0 0 BCH 6, 7, 8, 9, 11 0 0 0 0 0 0 0 0 00H 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 0 1 0 0 1 69H 13.125ns 15ns 186 187 188 189 190 191 192 Module VDD voltage level SDRAM minimum cycle time (tCK (min.)) SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM /CAS latencies supported, LSB (CL MASK) SDRAM /CAS latencies supported, MSB (CL MASK) Minimum CAS write latency time (tCWL(min)) SDRAM minimum row precharge time (tRP) SDRAM minimum /RAS to /CAS delay (tRCD) 193 SDRAM write recovery time (tWR (min)) 0 1 1 1 1 0 0 0 78H 194 SDRAM upper nibbles for tRAS and tRC 0 0 0 1 0 0 0 1 11H 0 0 0 1 1 0 0 0 18H 35ns 1 0 0 0 0 1 1 0 86H 48.75ns 0 0 1 1 1 1 1 1 3FH 7.8µs 0 0 0 0 0 0 0 0 00H 7.8µs 0 1 1 1 0 0 0 0 70H 110ns 0 0 0 0 0 0 1 1 03H 110ns 0 0 1 1 1 1 0 0 3CH 7.5ns 195 196 197 198 199 200 201 SDRAM minimum active to precharge time (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB Maximum average periodic refresh interval (tREFI), LSB Maximum average periodic refresh interval (tREFI), MSB SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal read to precharge command delay (tRTP) Preliminary Data Sheet E1512E10 (Ver. 1.0) 9 EBJ10UE8BDS0 Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 202 SDRAM minimum row active to row active 0 delay (tRRD) 0 1 1 0 0 0 0 30H 6ns 203 Upper nibble for tFAW 0 0 0 0 0 0 0 0 00H 30.0ns 1 1 1 1 0 0 0 0 F0H 30.0ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 204 205 206 207 208 209 Minimum four activate window delay time (tFAW) SDRAM minimum internal write to read command delay (tWTR) Write to read & read to write command turn-around time pull-in Back to back command turn-around time pull-in System address/ command rate (1N or 2N mode) Auto self-refresh performance (sub 1x refresh and IDD6 impacts) Default - No adjustment Default - No adjustment System operates in default mode TBD 210 to 218 Reserved 0 0 0 0 0 0 0 0 00H 219 Vendor personality byte 0 0 0 0 0 0 0 0 00H Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 220 Module VDD voltage level (extreme settings) 0 0 1 0 1 1 0 0 2CH 1.60V 221 SDRAM minimum cycle time (tCK (min)) 0 0 0 0 1 0 1 0 0AH DDR3-1600 222 Minimum CAS latency time (tAA (min)) 0 1 1 0 1 0 0 1 69H 13.125ns 1 0 1 1 1 1 0 0 BCH 6, 7, 8, 9, 11 0 0 0 0 0 0 0 0 00H 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 0 1 0 0 1 69H 13.125ns 0 1 1 0 1 0 0 1 69H 13.125ns 15ns [For Profile 2] Byte No. Function described 223 224 225 226 227 SDRAM /CAS latencies supported, LSB (CL MASK) SDRAM /CAS latencies supported, MSB (CL MASK) Minimum CAS write latency time (tCWL (min)) SDRAM minimum row precharge time (tRP) SDRAM minimum /RAS to /CAS delay (tRCD) 228 SDRAM write recovery time (tWR (min)) 0 1 1 1 1 0 0 0 78H 229 SDRAM upper nibbles for tRAS and tRC 0 0 0 1 0 0 0 1 11H 0 0 0 1 1 0 0 0 18H 35ns 1 0 0 0 0 1 1 0 86H 48.75ns 0 0 1 1 1 1 1 1 3FH 7.8us 0 0 0 0 0 0 0 0 00H 7.8us 0 1 1 1 0 0 0 0 70H 110ns 0 0 0 0 0 0 1 1 03H 110ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 1 1 0 0 0 0 30H 6ns 230 231 232 233 234 235 236 237 SDRAM minimum active to precharge time (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB Maximum average periodic refresh interval (tREFI), LSB Maximum average periodic refresh interval (tREFI), MSB SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal read to precharge command delay (tRTP) SDRAM minimum row active to row active delay (tRRD) Preliminary Data Sheet E1512E10 (Ver. 1.0) 10 EBJ10UE8BDS0 Byte No. Function described Bit7 Bit6 Bit5 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 238 Upper nibble for tFAW Minimum four activate window delay time (tFAW) SDRAM minimum internal write to read command delay (tWTR) Write to read & read to write command turn-around time pull-in Back to back command turn-around time pull-in System address/ command rate (1N or 2N mode) Auto self-refresh performance (sub 1x refresh and IDD6 impacts) 0 0 0 0 0 0 0 0 00H 30.0ns 1 1 1 1 0 0 0 0 F0H 30.0ns 0 0 1 1 1 1 0 0 3CH 7.5ns 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 00H 245 to 253 Reserved 0 0 0 0 0 0 0 0 00H 254 Vendor personality byte 0 0 0 0 0 0 0 0 00H 239 240 241 242 243 244 Preliminary Data Sheet E1512E10 (Ver. 1.0) 11 Default - No adjustment Default - No adjustment System operates in default mode TBD EBJ10UE8BDS0 Block Diagram DM DQ0 to DQ7 /CK CK /CS ODT CKE Address BA Command Rs4 Rs4 /CK Rs4 /CK CK ZQ Rs4 DM7 8 Rs1 DQ56 to DQ63 /CS ODT CKE Address BA Command DQ0 to DQ7 D7 /DQS Rs1 Rs4 DM DQS /DQS7 ZQ ZQ Rs1 Rs1 /CK 8 Rs1 DQ48 to DQ55 /CS ODT CKE Address BA Command /DQS DQ0 to DQ7 /CK D3 DM CK DQS7 DQS Rs1 D6 /DQS DM5 8 Rs1 DQ40 to DQ47 Rs4 ZQ /CK DQ0 to DQ7 Rs1 Rs1 ZQ DQS Rs1 CK DM Rs1 /DQS5 /CS ODT CKE Address BA Command D2 /CS ODT CKE Address BA Command DM4 8 Rs1 DQ32 to DQ39 DQ0 to DQ7 Rs1 /DQS Rs1 DM 8 Rs1 DQS5 DQS /DQS4 DM6 DM3 DQ24 to DQ31 Rs1 Rs1 /DQS6 ZQ ZQ D5 /DQS Rs1 Rs4 DQ0 to DQ7 DQS Rs1 /CK DM DQ0 to DQ7 Rs1 /DQS3 CK DM2 8 Rs1 DQ16 to DQ23 /CS ODT CKE Address BA Command /DQS Rs1 DQS3 D1 DM CK DQS /DQS2 DQS6 DM1 8 Rs1 DQ8 to DQ15 Rs1 Rs1 DQS4 ZQ /CS ODT CKE Address BA Command DQ0 to DQ7 CK DQS2 DM D4 /DQS Rs1 Rs4 DM0 8 Rs1 DQ0 to DQ7 DQS Rs1 /DQS1 /CK /DQS Rs1 DQS1 D0 Rs1 /CS ODT CKE Address BA Command /DQS0 Rs1 DQS CK /CK0 CK0 3 Command 17 Address, BA /CS0 ODT0 CKE0 Rs1 DQS0 Rs2 Rs2 Rs2 Rs2 Rs2 Rs3 Rs3 VTT V2 RS5 /CK1 /RESET VTT VDDSPD VREFCA VREFDQ SCL SA0 A0 SA1 A1 A2 D6 D7 D3 Terminated at near card edge /RESET:SDRAMs (D0 to D7) VDD SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) VSS SDRAMs (D0 to D7), SPD V1 Serial PD SCL V4 V3 D5 VTT V1 D4 CK1 VTT VDD SDA SDA U0 WP * D0 to D7: 1G bits DDR3 SDRAM Address, BA: A0 to A13, BA0 to BA2 Command: /RAS, /CAS, /WE U0: 256 bytes EEPROM Rs1: 15Ω Rs2: 36Ω Rs3: 30Ω Rs4: 240Ω Rs5: 75Ω Preliminary Data Sheet E1512E10 (Ver. 1.0) 12 D0 V2 D1 V3 D2 V4 Address and Control lines Notes : 1. DQ wiring may be changed within a byte. 2. DQ, DQS, /DQS, DM relationships must be maintained as shown. EBJ10UE8BDS0 Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Notes Power supply voltage VDD −0.4 to +1.975 V 1, 3, 4 Input voltage VIN −0.4 to +1.975 V 1, 4 Output voltage VOUT −0.4 to +1.975 V 1, 4 Reference voltage VREFCA −0.4 to 0.6 × VDD V 3, 4 Reference voltage for DQ VREFDQ −0.4 to 0.6 × VDDQ V 3, 4 1, 2, 4 Storage temperature Tstg −55 to +100 °C Power dissipation PD 8 W Short circuit output current IOUT 50 mA 1, 4 Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 × VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4. DDR3 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC 0 to +95 °C 1, 2, 3 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). Preliminary Data Sheet E1512E10 (Ver. 1.0) 13 EBJ10UE8BDS0 Recommended DC Operating Conditions (TC = 0°C to +85°C) Parameter Symbol min. typ. max. Unit Notes Supply voltage VDD, VDDQ 1.425 1.5 1.575 V 1, 2, 3 VSS 0 0 0 V 1 3.6 VDDSPD 3.0 3.3 Input reference voltage VREFCA (DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 4, 5 Input reference voltage for DQ VREFDQ (DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 4, 5 Termination voltage VTT VDDQ/2 – TBD TBD V Notes: 1. 2. 3. 4. VDDQ/2 + TBD V DDR3 SDRAM component specification. Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx ±15 mV). 5. For reference: approx. VDD/2 ±15 mV. Preliminary Data Sheet E1512E10 (Ver. 1.0) 14 EBJ10UE8BDS0 DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.5V ± 0.075V, VSS = 0V) Parameter Symbol Data rate (Mbps) max. Unit Notes Operating current (ACT-PRE) IDD0 1600 1333 1066 840 760 680 mA Operating current (ACT-READ-PRE) IDD1 1600 1333 1066 960 880 800 mA IDD2P1 1600 1333 1066 360 320 280 mA Fast PD Exit IDD2P0 1600 1333 1066 120 112 104 mA Slow PD Exit Precharge standby current IDD2N 1600 1333 1066 520 480 440 mA Precharge standby ODT current IDD2NT 1600 1333 1066 520 480 440 mA Precharge quiet standby current IDD2Q 1600 1333 1066 480 440 400 mA Active power-down current (Always fast exit) IDD3P 1600 1333 1066 360 320 280 mA Active standby current IDD3N 1600 1333 1066 600 520 480 mA Operating current (Burst read operating) IDD4R 1600 1333 1066 1840 1600 1280 mA Operating current (Burst write operating) IDD4W 1600 1333 1066 1920 1680 1360 mA Burst refresh current IDD5B 1600 1333 1066 2240 2160 2080 mA All bank interleave read current IDD7 1600 1333 1066 2800 2480 2160 mA Precharge power-down standby current Self-Refresh Current (TC = 0°C to +85°C, VDD = 1.5V ± 0.075V) Parameter Self-refresh current normal temperature range Self-refresh current extended temperature range Auto self-refresh current (optional) Symbol max. Unit IDD6 80 mA IDD6ET 144 mA IDD6TC mA Preliminary Data Sheet E1512E10 (Ver. 1.0) 15 Notes EBJ10UE8BDS0 Timings used for IDD and IDDQ Measurement-Loop Patterns DDR3-1600 DDR3-1333 DDR3-1066 Parameter 11-11-11 9-9-9 7-7-7 Unit CL 11 9 7 tCK tCK min. 1.25 1.5 1.875 ns nRCD min. 11 9 7 nCK nRC min. 39 33 27 nCK nRAS min. 28 24 20 nCK nRP min. 11 9 7 nCK nFAW 24 20 20 nCK nRRD 5 4 4 nCK nRFC 88 74 59 nCK DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) (DDR3 SDRAM Component Specification) Parameter Symbol Value Unit Notes Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO 5 µA DDQ ≥ VOUT ≥ VSS Preliminary Data Sheet E1512E10 (Ver. 1.0) 16 EBJ10UE8BDS0 Pin Functions CK, /CK (input pin) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A13 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table] Address (A0 to A13) Row address (RA) Column address (CA) AX0 to AX13 AY0 to AY9 Notes A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12 (/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine if a mode register is to be accessed during a MRS cycle. [Bank Select Signal Table] BA0 BA1 BA2 Bank 0 L L L Bank 1 H L L Bank 2 L H L Bank 3 H H L Bank 4 L L H Bank 5 H L H Bank 6 L H H Bank 7 H H H Remark: H: VIH. L: VIL. Preliminary Data Sheet E1512E10 (Ver. 1.0) 17 EBJ10UE8BDS0 CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DQ (input and output pins) Bi-directional data bus. DQS and /DQS (input and output pin) Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during READs and WRITEs. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. DM (input pins) DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS. VDD (power supply pins) 1.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 3.3V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. VTT (power supply pin) I/O termination supply for SDRAM. VREFDQ (power supply) Reference voltage for DQ. VREFCA (power supply) Reference voltage for CA. /RESET (input pin) /RESET is negative active signal (active low) and is referred to GND. Detailed Operation Part, Electrical Characteristics and Timing Waveforms Refer to the EDJ1104BDSE, EDJ1108BDSE datasheet (E1494E). Preliminary Data Sheet E1512E10 (Ver. 1.0) 18 EBJ10UE8BDS0 Physical Outline Unit: mm Front side 21.15 2.00 Min 9.00 3.80 Max (DATUM -A-) 4x Full R 1 203 6.00 4.00 Min Component area (Front) A B 21.00 2.15 2.45 39.00 D 1.00 ± 0.10 67.60 Back side 63.60 2.45 2.15 Component area (Back) 20.00 30.00 4.00 204 2 C (DATUM -A-) Detail A Detail B 0.45 ± 0.03 Detail C FULL R 1.65 3.00 4.00 ± 0.10 0.35 Max 2.55 Min 0.60 1.00 ± 0.10 Detail D Contact pad 0.2 Max 0.35 Max 3.00 1.35 ECA-TS2-0215-01 Preliminary Data Sheet E1512E10 (Ver. 1.0) 19 EBJ10UE8BDS0 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E1512E10 (Ver. 1.0) 20 EBJ10UE8BDS0 The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0706 Preliminary Data Sheet E1512E10 (Ver. 1.0) 21