16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh E0154H10 (Ver. 1.0) (Previous ADE-203-636D (Z)) Jul. 6, 2001 (K) LP EO Description HM5118165 Series The HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II. Features ct du ro • Single 5 V (±10%) • Access time : 50 ns/60 ns/70 ns (max) • Power dissipation Active mode : 1045 mW/935 mW/825 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Refresh cycles 1024 refresh cycles : 16 ms : 128 ms (L-version) • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) • 2CAS-byte control • Battery backup operation (L-version) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EO HM5118165 Series Ordering Information Type No. Access time Package HM5118165J-5 HM5118165J-6 HM5118165J-7 50 ns 60 ns 70 ns 400-mil 42-pin plastic SOJ (CP-42D) HM5118165LJ-5 HM5118165LJ-6 HM5118165LJ-7 50 ns 60 ns 70 ns HM5118165TT-5 HM5118165TT-6 HM5118165TT-7 50 ns 60 ns 70 ns LP HM5118165LTT-5 HM5118165LTT-6 HM5118165LTT-7 400-mil 50-pin plastic TSOP II (TTP-50/44DC) 50 ns 60 ns 70 ns ct du ro Data Sheet E0154H10 2 EO HM5118165 Series Pin Arrangement HM5118165J/LJ Series HM5118165TT/LTT Series 1 42 VSS I/O0 2 41 I/O15 I/O1 3 40 I/O14 I/O2 4 39 I/O13 I/O3 5 38 I/O12 6 37 VSS 7 36 I/O11 8 35 I/O10 9 34 I/O9 10 33 I/O8 11 32 NC 12 31 LCAS 13 30 UCAS 14 29 OE 15 28 A9 16 27 A8 A7 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC 17 26 A1 18 25 A2 19 24 A3 20 23 21 22 A0 VCC (Top view) VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 V SS I/O15 I/O14 I/O13 I/O12 V SS I/O11 I/O10 I/O9 I/O8 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS ro LP VCC A6 A5 A4 VSS Function A0 to A9 Address input — Row/Refresh address A0 to A9 — Column address A0 to A9 I/O0 to I/O15 Data input/Data output RAS Row address strobe UCAS, LCAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection ct Pin name du Pin Description (Top view) Data Sheet E0154H10 3 EO HM5118165 Series Block Diagram A1 Column • • • A9 address buffers Row address buffers OE Column decoder 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array I/O buffers ct du ro • • • WE Timing and control Row decoder to UCAS LCAS LP A0 RAS Data Sheet E0154H10 4 I/O0 to I/O15 EO HM5118165 Series Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open Standby L L H H L Valid Lower byte Read cycle L H L H L Valid Upper byte L L L H L Valid Word D Open Lower byte Early write cycle L L L L H L L H H L LP L L *2 L L H L L* 2 D Open Upper byte L* 2 D Open Word L* 2 H Undefined Lower byte Delayed write cycle L* 2 H Undefined Upper byte 2 H Undefined Word L L L* L L H H to L L to H Valid Lower byte Read-modify-write cycle L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word L H H D D Open Word RAS-only refresh cycle H to L H L D D Open Word CAS-before-RAS refresh cycle or H to L L H D D Open Word Self refresh cycle (L-version) H to L L L D D Open Word L L L H H ro L Open Read cycle (Output disabled) ct du Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Data Sheet E0154H10 5 EO HM5118165 Series Absolute Maximum Ratings Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C –55 to +125 °C Storage temperature LP Parameter Tstg Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Input high voltage Input low voltage Symbol Min Typ Max Unit Notes VCC 4.5 5.0 5.5 V 1, 2 VIH 2.4 — 6.5 V 1 VIL –1.0 — 0.8 V 1 ro Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5118165 Parameter 1, Operating current* * Standby current Symbol Min Max Min Max Min Max Unit Test conditions I CC1 — 200 — 170 — 150 mA t RC = min I CC2 — 2 — 2 — 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z — 150 — I CC2 150 — Data Sheet E0154H10 6 -7 150 µA ct Standby current (L-version) 2 -6 du -5 CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z EO HM5118165 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont.) HM5118165 -5 Parameter 2 RAS-only refresh current* 1 Standby current* -6 Symbol Min Max Min Max Min Max Unit Test conditions I CC3 — 200 — 170 — 150 mA t RC = min I CC5 — 5 5 5 RAS = VIH, UCAS, LCAS = VIL Dout = enable — LP CAS-before-RAS refresh current -7 — mA I CC6 — 190 — 170 — 150 mA t RC = min EDO page mode current*1, * 3 I CC7 — 185 — 165 — 145 mA t HPC = min 4 I CC10 — 500 — 500 — 500 µA CMOS interface Dout = High-Z CBR refresh: tRC = 125 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — 300 — 300 — 300 µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 Output low voltage VOL 0 ro Battery backup current* (Standby with CBR refresh) (L-version) VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA 0.4 0.4 0.4 V Low Iout = 2 mA 0 0 Typ Max Unit Notes — 5 pF 1 CI2 — 7 pF 1 CI/O — 7 pF 1, 2 Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Input capacitance (Address) CI1 Input capacitance (Clocks) Output capacitance (Data-in, Data-out) ct du Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout. Data Sheet E0154H10 7 EO HM5118165 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18, *19, *20 Test Conditions Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) LP • • • • • Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) Parameter HM5118165 -5 -6 -7 Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns t CP 7 — 10 — 13 — ns t RAS 50 10000 60 10000 70 10000 ns 7 10000 10 10000 13 10000 ns 0 — 0 — 0 — ns 7 — 10 — 10 — ns 0 — 0 — 0 — ns 21 7 — 10 — 13 — ns 21 11 37 14 45 14 52 ns 3 12 30 12 35 ns 4 13 — 13 — ns 40 — 45 — ns 23 5 — 5 — ns 22 15 — 18 — ns 5 0 — 0 — ns 6 0 — 0 — ns 6 2 50 2 CAS precharge time RAS pulse width t CAS Row address setup time t ASR Row address hold time t RAH Column address setup time t ASC Column address hold time t CAH RAS to CAS delay time t RCD RAS to column address delay time t RAD 9 25 RAS hold time t RSH 10 — CAS hold time t CSH 35 — CAS to RAS precharge time t CRP 5 — OE to Din delay time t OED 13 — OE delay time from Din t DZO 0 — CAS delay time from Din t DZC 0 — Transition time (rise and fall) tT 2 50 Data Sheet E0154H10 8 Notes ct CAS pulse width du ro Symbol 50 ns 7 EO HM5118165 Series Read Cycle HM5118165 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9 Access time from CAS t CAC — 13 — 15 — 18 ns 9, 10, 17 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 13 — 15 — 18 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns 21 Read command hold time to CAS t RCH 0 — 0 — 0 — ns 12, 22 Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 0 — 0 — 0 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO Output buffer turn-off time t OFF Output buffer turn-off to OE t OEZ CAS to Din delay time t CDD Output data hold time from RAS t OHR Output buffer turn-off to RAS t OFR ro Output buffer turn-off to WE LP Parameter 12 27 — 3 — 3 — ns — 13 — 15 — 15 ns 13, 27 — 13 — 15 — 15 ns 13 13 — 15 — 18 — ns 5 3 — 3 — 3 — ns 27 — 13 — 15 — 15 ns 27 t WEZ — 13 WE to Din delay time t WED 13 — RAS to Din delay time t RDD 13 — RAS next CAS delay time t RNCD 50 — du 3 — 15 — 15 ns 15 — 18 — ns 15 — 18 — ns 60 — 70 — ns ct Data Sheet E0154H10 9 EO HM5118165 Series Write Cycle HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14, 21 Write command hold time t WCH 7 — 10 — 13 — ns 21 Write command pulse width t WP 7 — 10 — 10 — ns LP Write command to RAS lead time t RWL 7 — 10 — 13 — ns Write command to CAS lead time t CWL 7 — 10 — 13 — ns 23 Data-in setup time t DS 0 — 0 — 0 — ns 15, 23 t DH 7 — 10 — 13 — ns 15, 23 Notes Data-in hold time Read-Modify-Write Cycle -5 -6 -7 ro Parameter Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 111 — 135 — 161 — ns RAS to WE delay time t RWD 67 — 79 — 92 — ns 14 CAS to WE delay time t CWD 30 — 34 — 40 — ns 14 Column address to WE delay time t AWD 42 — 49 — 57 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns HM5118165 -5 Parameter Symbol -6 Max CAS setup time (CBR refresh cycle) t CSR 5 — CAS hold time (CBR refresh cycle) t CHR 7 — RAS precharge to CAS hold time 5 — Data Sheet E0154H10 10 -7 Min Max Min Max Unit Notes 5 — 5 — ns 21 10 — 10 — ns 22 5 — 5 — ns 21 ct Min t RPC du Refresh Cycle EO HM5118165 Series EDO Page Mode Cycle HM5118165 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 25 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 28 — 35 — 40 ns 9, 17, 22 RAS hold time from CAS precharge t CPRH 28 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 7 — 10 — 13 — ns CAS to OE setup time t COP 5 — 5 — 5 — ns Read command hold time from CAS precharge t RCHC 28 — 35 — 40 — ns LP Parameter — — 9 EDO Page Mode Read-Modify-Write Cycle ro HM5118165 -5 Parameter Symbol EDO page mode read-modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW -6 -7 Min Max Min Max Min Max Unit 57 — 68 — 79 — ns 45 — 54 — 62 — ns du Refresh Notes 14, 22 Parameter Symbol Max Unit Note Refresh period t REF 16 ms 1024 cycles Refresh period (L-version) t REF 128 ms 1024 cycles ct Data Sheet E0154H10 11 EO HM5118165 Series Self Refresh Mode (L-version) HM5118165L -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 — 100 — 100 — µs 28, 29, 30, 31 RAS precharge time (self refresh) t RPS 90 — 110 — 130 — ns CAS hold time (self refresh) t CHS –50 — –50 — –50 — ns LP Parameter ct du ro Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD ≥ tRAD (max) + tAA (max) – tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. Data Sheet E0154H10 12 EO HM5118165 Series ct du ro LP 20 All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH, t DS and t CSH should be satisfied by both UCAS and LCAS. 24. t CP is determined by the time that both UCAS and LCAS are high. 25. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH , and between t OFR and t OFF. 28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use t RPS instead of tRP. 29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL. Data Sheet E0154H10 13 EO HM5118165 Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. UCAS/LCAS are allowed under the following conditions. However skew between 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. UCAS LCAS WE LP RAS Delayed write Early write RAS UCAS du LCAS ro 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. ct Data Sheet E0154H10 14 EO HM5118165 Series Timing Waveforms*32 Read Cycle t RC t RAS t RP RAS LP t CSH t CRP t RCD t RSH t CAS tT UCAS LCAS t RAD t ASR Address t RAH t ASC t RAL t CAL t CAH Column Row ro t RRH t RCHR t RCS WE t DZC t DZO t OEA OE t WED t CDD t RDD du High-Z Din t RCH t OED t AA ct t OEZ t OHO t OFF t CAC t OH t OFR t OHR t RAC t CLZ t WEZ Dout Dout Data Sheet E0154H10 15 EO HM5118165 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP LP tRCD tRSH tCAS tT UCAS LCAS tASR Address tRAH Row tASC tCAH Column ro tWCS WE tWCH Din Din High-Z* ct Dout tDH du tDS * t WCS Data Sheet E0154H10 16 t WCS (min) EO HM5118165 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP LP t RCD t RSH t CAS tT UCAS LCAS Address t ASR t RAH t ASC Row t CAH Column t CWL ro t RCS WE t DZC t DH du Din t DS t RWL t WP High-Z Din t OEH t OED OE t OEZ t CLZ ct # t DZO High-Z Dout Invalid Dout Data Sheet E0154H10 17 EO HM5118165 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS LCAS t RCD LP UCAS tT t RAH t ASC Row t CAH Column t CWD ro t RCS WE t CRP t RAD t ASR Address t CAS tCWL t AWD t RWL t RWD t WP t DZC t DS du High-Z Din t DH Din t OED t DZO t OEH t OEA OE t OEZ t AA t RAC t OHO Dout Dout t CLZ Data Sheet E0154H10 18 ct t CAC High-Z EO HM5118165 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS LCAS t CRP LP UCAS tT t ASR Address t RPC t CRP t RAH Row t OFR t OFF ct du ! High-Z ro Dout Data Sheet E0154H10 19 EO HM5118165 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS tT LP t RPC t CP t CHR t CRP t CSR t CHR ")# UCAS t CSR t RPC t CP LCAS Address t OFR Dout ro t OFF High-Z ct du Data Sheet E0154H10 20 EO HM5118165 Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RP t RC t RP t RAS t RP RAS tT t CHR LP t RSH t CRP t RCD UCAS LCAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RRH t RCH ro t RCS WE t DZC t WED t CDD t RDD t DZO t OEA OE t CAC t AA t CLZ Dout Dout t OED t OFF t OH t OEZ t WEZ t OHO ct t RAC du High-Z Din t OFR t OHR Data Sheet E0154H10 21 EO HM5118165 Series EDO Page Mode Read Cycle t RP t RNCD RAS tT tASR tRAH tASC Row t HPC t CP t CAS t CP t HPC tCAS tCAS t RCHC t RCH t RCS tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CRP t CPRH t CP t RSH t CAS t RCHR t RCS WE Address t CSH LP UCAS LCAS t HPC t RASP t CAL t RRH t RCH t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC Din High-Z ro tCOL tCOP tOED tDZO OE tCPA tOEA tAA tCAC tCAC tAA tWEZ tOEZ tOHO du Dout tDOH Dout 1 tAA tOEZ tOEA tRAC Dout 2 tOFR tOHR tOEZ tCPA tCPA tAA tCAC Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 ct Data Sheet E0154H10 22 EO HM5118165 Series EDO Page Mode Read Cycle (2CAS) t RP t RNCD t RASP RAS tT t CSH t CAS LCAS t CRP t HPC t CP tRSH tCAS t CAS t RCHC t RRH t RCH t RCS WE tASR Address tHPC t CP t CAS LP UCAS t HPC t CP tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL High-Z t CAL tRDD t CAL tCDD tCOL tCOP tOED OE tOEA tCPA tAA tCAC tCAC tAA tOHO tDOH tRAC L Dout tOEZ du tDZO t WED Column 4 ro tDZC Din t CAL t RAL t CAH tASC tOEZ tOEA tAA tCAC tOHO Dout 1 Dout 2 tOHO tOFF tOH tOEA ct Dout 1 tOFR tOHR tOEZ Dout 4 Dout 2 tCPA tAA tCAC U Dout tCPA Dout 3 Dout 4 Data Sheet E0154H10 23 EO HM5118165 Series EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH LP UCAS LCAS tASR Address tHPC tCAS tRCD Row tRAH tASC tCAH Column 1 tWCH WE Din Dout tDH Din 1 tASC tCAH Column 2 tWCH tWCS tDS tDH tCP tCAS tASC tCRP tCAH Column N tWCS tDS tWCH tDH du tDS tRSH tCAS ro tWCS tCP Din 2 Din N High-Z* ct * t WCS Data Sheet E0154H10 24 t WCS (min) EO HM5118165 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP LP t CSH t RCD UCAS LCAS t ASR t CAS t RSH t CAS t RAD t ASC t RAH Address t CRP t CP t HPC t CAS t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL WE t WP t DZC t DS t CWL t RCS t WP t WP t DZC t DS t DZC t DS t DH t DZO t DH Din 2 Din N t DZO # t DZO t DH du Din 1 Din t CWL t RWL t RCS ro t RCS Column N t OED t OED t OED t OEH t OEH OE t CLZ t CLZ t OEZ t OEH t CLZ t OEZ t OEZ ct High-Z Dout Invalid Dout Invalid Dout Invalid Dout Data Sheet E0154H10 25 EO HM5118165 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t RCD UCAS LCAS t ASR Address t RSH t CP LP t CP t CAS t CAS t CRP t CAS t RAD t ASC t RAH Row t ASC t CAH t CAH Column 1 t RWD Column 2 t CWL t WP t CWD t RCS t DZC t DS t DH t OED t DH Din 2 t OED t DZO Din N t OED t DZO t OEH t OEH *# t OEH t DH du t DZO t RWL t WP t DZC t DS Din 1 t CWL t CWD t WP t DZC t DS Din t CPW t AWD ro t RCS t CWL t AWD t RCS WE Column N t CPW t AWD t CWD t ASC t CAH OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t AA t CPA t OEZ t CLZ t CLZ ct t OEZ t CLZ t OHO t OEA t CAC t OEZ High-Z Dout Dout 1 Dout 2 Data Sheet E0154H10 26 Dout N EO HM5118165 Series EDO Page Mode Mix Cycle (1) t RP t RASP RAS tT t CAS t CAS tCAS tCAS t CSH LP UCAS LCAS t CRP t CP t CP t CP tRSH t RCD t WCS WE t ASC tRAH tASR Address Row t DS Column 1 tCPW tAWD t ASC t CAH tASC t CAH Column 2 Column 3 tASC t RAL t CAH Column 4 t CAL tRDD tCDD t CAL t DH Din 1 tWP t DH t DS High-Z Din 3 tOED tWED OE tCAH t RRH t RCH t RCS t RCS ro Din t WCH tCPA tAA tOEA Dout tAA tAA t OEZ t DOH Dout 2 tCAC t OHO Dout 3 tOEZ tCAC du tCAC tOFR tWEZ tCPA tCPA tOHO tOEA tOFF tOH Dout 4 ct Data Sheet E0154H10 27 EO HM5118165 Series EDO Page Mode Mix Cycle (2) t RP t RNCD t RASP RAS tT t CAS t RCD t ASC tRAH tASR Address Row tCAS t RCH tCAH Column 1 tWCS t WCH t ASC t CAH Column 2 Column 3 t CAH tASC Column 4 t CAL t DS t DH tRDD tCDD t DH Din 2 tOED t RAL t CAL ro High-Z Din t RRH t RCH tWP tCPW t ASC t CAH t DS tRSH t RCS t RCS t CAL Din 3 tOED tCOP tWED tCOL OE tAA tOEZ t OEA tCPA tAA tCAC tRAC t OHO Dout 1 tOFR tWEZ tCPA tOEZ du tOEA tCAC Dout tCAS t RCHR t RCS WE t CAS t CRP t CP t CP t CP LP UCAS LCAS t CSH t OHO Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 ct Data Sheet E0154H10 28 EO HM5118165 Series Self Refresh Cycle (L-version)* 28, 29, 30, 31 t RASS t RP t RPS RAS tT t CRP t CSR t CHS #$%*+ UCAS LP , t RPC t CP LCAS t OFR t OFF Dout High-Z ct du ro Data Sheet E0154H10 29 EO HM5118165 Series Package Dimensions HM5118165J/LJ Series (CP-42D) Unit: mm 27.06 27.43 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 10.16 ± 0.13 11.18 ± 0.13 2.50 ± 0.12 1.30 Max 21 0.80 +0.25 –0.17 0.74 3.50 ± 0.26 1 22 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-42D Conforms — 1.75 g ct du ro LP 42 Data Sheet E0154H10 30 EO HM5118165 Series HM5118165TT/LTT Series (TTP-50/44DC) 20.95 21.35 Max 40 36 26 LP 10.16 50 Unit: mm 11 15 25 0.10 Dimension including the plating thickness Base material dimension 0.145 ± 0.05 0.125 ± 0.04 3.20 11.76 ± 0.20 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-50/44DC Conforms — 0.50 g ct du ro 1.20 Max 0.27 ± 0.07 0.13 M 0.25 ± 0.05 1.15 Max 0.80 0.68 0.80 0.13 ± 0.05 1 Data Sheet E0154H10 31 EO HM5118165 Series Cautions ct du ro LP 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Data Sheet E0154H10 32