SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan DATA SHEET M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) DESCRIPTION M2V64S50ETP-I is a 4-bank x 524,288-word x 32-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V64S50ETP-I achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), and are suitable for digital consumer products or graphic memory in computer systems. FEATURES - Single 3.3v + 0.3V power supply - Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms (4 banks concurrent refresh) (x32) - Address Input, Row address A0-10 / Column address A0-7 (x32) - LVTTL Interface - Package type : 0.5mm lead pitch 86-pin TSOP(II) - Ambient temperature range:-40 to +85 oC Operating Frequencies Max. Frequency @CL=2 * Max. Frequency @CL=3 * Standard M2V64S50ETP-6I 100MHz 133MHz PC133(CL3) M2V64S50ETP-7I 100MHz 100MHz PC100(CL2) * CL = CAS(Read) Latency This Product became EOL in August, 2004. Elpida Memory, Inc. 2003-2004 1 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) PIN CONFIGURATION x32 CLK CKE /CS /RAS /CAS /WE DQ0-31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O 0.5mm pin pitch VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 400mil x875mil 86pin TSOP(II) (TOP VIEW) 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS DQM0-3 : Output Disable/ Write Mask A0-10 BA0,1 VDD VDDQ : Address Input : Bank Address : Power Supply : Power Supply for Output VSS VSSQ : Ground : Ground for Output 2 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) PIN FUNCTION CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command are masked except CLK, CKE and DQM /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-11 Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-10(x32). The Column Address is specified by A0-7. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. DQ0-31(x32) Input / Output Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. DQM0-3(X32) Input VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry. VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only. 3 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) BLOCK DIAGRAM DQ0-31 I/O Buffer Memory Array 2048 x256 x32 Cell Array Bank #0 Memory Array Memory Array 2048 x256 x32 Cell Array 2048 x256 x32 Cell Array Bank #1 Bank #2 Memory Array 2048 x256 x32 Cell Array Bank #3 Mode Register Control Circuitry Address Buffer Control Signal Buffer Clock Buffer A0-10 BA0,1 CLK TYPE DESIGNATION CODE CKE /CS /RAS /CAS /WE DQM0-3 These rules are only applied to the Synchronous DRAM family. M2 V 64 S 5 0 E TP -6 I Operating Temp. I : I Version Access Item -6 : 7.5ns (PC133/3-3-3) -7 : 10ns(PC100/2-2-2) Package Type TP : TSOP (II) WG : BGA Process Generation E: 6th gen. Function Reserved for Future Use Organization 5: x32 Synchronous DRAM Density 64 : 64Mbit Interface V : LVTTL Mitsubishi DRAM 4 SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan DATA SHEET M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) BASIC FUNCTIONS The M2V64S50ETP-I provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @refresh command A10 Precharge Option @precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically. 5 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) COMMAND TRUTH TABLE COMMAND MNEMONIC CKE n-1 CKE n /CS Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Banks PREA H X L L H L X H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TBST H X L H H L X X X Mode Register Set MRS H X L L L L L L V /RAS /CAS /WE BA0,1 A10 /AP A0-9, note 11 1 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE:A7-9=L, A0-A6 =Mode Address (x32) 6 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) FUNCTION TRUTH TABLE (1/4) Current State /CS /RAS /CAS /WE IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X L L L L H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST NOP L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X L L L L H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst ROW ACTIVE READ Address Op-Code, Mode-Add Op-Code, Mode-Add Command NOP*4 Auto-Refresh*5 MRS Mode Register Set*5 READ / READA WRITE / WRITEA Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge REFA ILLEGAL MRS ILLEGAL Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X L L L L Mode-Add Bank Active, Latch RA REFA L Op-Code, Action WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge REFA ILLEGAL MRS ILLEGAL 7 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) FUNCTION TRUTH TABLE (2/4) Current State /CS /RAS /CAS /WE WRITE H X X X L H H L H H L H L Command Action X DESEL NOP (Continue Burst to END) H X NOP NOP (Continue Burst to END) L X TBST Terminate Burst H Address BA, CA, A10 READ / READA WRITE / Terminate Burst, Latch CA, Begin Read, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with H X X X X DESEL NOP (Continue Burst to END) AUTO L H H H X NOP NOP (Continue Burst to END) PRECHARGE L H H L X TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with H X X X X DESEL NOP (Continue Burst to END) AUTO L H H H X NOP NOP (Continue Burst to END) PRECHARGE L H H L X TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITEA READ / READA WRITE / WRITEA READ / READA WRITE / WRITEA Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL for same Bank *6 ILLEGAL for same Bank *6 Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL for same Bank *7 ILLEGAL for same Bank *7 Bank Active / ILLEGAL*2 ILLEGAL*2 8 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) FUNCTION TRUTH TABLE (3/4) Current State /CS /RAS /CAS /WE Address Command Action PRE – H X X X X DESEL NOP (Idle after tRP) CHARGING L H H H X NOP NOP (Idle after tRP) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW H X X X X DESEL NOP (Row Active after tRCD) ACTIVATING L H H H X NOP NOP (Row Active after tRCD) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL NOP*4 (Idle after tRP) 9 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) FUNCTION TRUTH TABLE (4/4) Current State /CS /RAS /CAS /WE Address Command Action RE- H X X X X DESEL NOP (Idle after tRFC) FRESHING L H H H X NOP NOP (Idle after tRFC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE H X X X X DESEL NOP (Idle after tRSC) REGISTER L H H H X NOP NOP (Idle after tRSC) SETTING L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to Read with Auto-Precharge in page 17 7. Refer to Write with Auto-Precharge in page 18 ILLEGAL = Device operation and/or data-integrity are not guaranteed. 10 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) FUNCTION TRUTH TABLE for CKE Current State CKE n-1 CKE n /CS SELF- H X X X REFRESH*1 L H H L H L /RAS /CAS /WE Add Action X X X INVALID X X X X Exit Self-Refresh (Idle after tRFC) L H H H X Exit Self-Refresh (Idle after tRFC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) POWER H X X X X X X INVALID DOWN L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2 H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down ANY STATE H H X X X X X Refer to Function Truth Table other than H L X X X X X Begin CLK Suspend at Next Cycle*3 listed above L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously A minimum setup time must be satisfied before any command other than EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. 11 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) SIMPLIFIED STATE DIAGRAM POWER APPLIED POWER ON REFA ( 2 or MORE ) PRE CHARGE ALL PREA MRS AUTO REFRESH MODE REGISTER SET MRS SELF REFRESH REFS AUTO REFRESH REFA IDLE REFSX CKEL CLK SUSPEND CKEH ACT POWER DOWN CKEL CKEH ROW ACTIVE TBST WRITE WRITE SUSPEND CKEH READ WRITEA CKEL WRITE WRITEA TBST WRITE READA READ CKEL READ CKEH WRITEA READA READA CKEL WRITEA WRITEA SUSPEND CKEH READ SUSPEND CKEL READA PRE PRE PRE READA CKEH SUSPEND PRE CHARGE Automatic Sequence Command Sequence 12 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP or DESEL condition at the inputs. 2. Maintain stable power, stable clock, and NOP or DESEL input conditions for a minimum of 100us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER CLK Burst Length, Burst Type, /CAS Latency and Write Mode can be programmed By setting the mode register (MRS) with BA0=BA1=0. The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. Unused bit A7-A8,A10(x32) have to be programmed to “0”. /CS /RAS /CAS /WE BA0,BA1 A11-A0 BA0 BA1 A11 A10 A9 A8 A7 WM 0 0 0 0 0 Write Mode Latency Mode CL 000 001 010 011 100 101 110 111 0 0 1 A6 A5 A4 LTMODE A3 A2 A1 A0 BT BL Burst Write Single Write /CAS LATENCY R R 2 3 R R R R BL Burst Length Burst Type 000 001 010 011 100 101 110 111 0 1 BT=0 1 2 4 8 R R R Full Page V BT=1 1 2 4 8 R R R R SEQUENTIAL INTERLEAVED R: Reserved for Future Use 13 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) CLK Command Address Read Write Y Y Q0 DQ Q1 Q2 Q3 D0 D1 D2 D3 /CAS Latency CL= 3 BL= 4 Burst Length Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 Sequential 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 - - 1 1 0 1 0 8 4 2 Interleaved 14 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) OPERATIONAL DESCRIPTION BANK ACTIVATE One of four banks is activated by an ACT command. A bank is selected by BA0-1. A row is selected by A0-10(x32). Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=3) CLK Command ACT ACT tRRD A0-9,11 READ tRCD ACT tRP Xa Xb Yb A10 Xa Xb 0 BA0-1 00 01 01 DQ PRE Xa Xa 1 00 Qb0 Qb1 Qb2 Qb3 Precharge All READ A READ command can be issued to any active bank. The start address is specified by A0-7. 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. 15 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Multi Bank Interleaving Read (CL=2, BL=4) CLK Command READ ACT ACT tRCD A0-9,11 READ PRE tRCD ACT tRP Xa Ya Xb Yb A10 Xa 0 Xb 0 0 Xa BA0-1 00 00 01 01 00 00 Qa2 Qa3 DQ Qa0 Qa1 Xa Qb0 Qb1 Qb2 Qb3 Read with Auto-Precharge (CL=2, BL=4) CLK Command ACT READ tRCD A0-9,11 ACT BL tRP Xa Ya Xa A10 Xa 1 Xa BA0-1 00 00 00 DQ Qa0 Qa1 Qa2 Qa3 internal precharge starts Auto-Precharge Timing (READ, BL=4) CLK Command ACT ACT READ tRCD DQ CL=2 DQ CL=3 BL Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 internal precharge starts 16 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-7. 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. Write (BL=4) CLK Command ACT PRE Write tRCD BL Xa Ya A10 Xa 0 BA0-1 00 00 A0-9,11 ACT tRP Xa 0 Xa 00 tWR DQ Da0 Da1 Da2 Da3 Write with Auto-Precharge (BL=4) CLK Command ACT ACT Write tRCD BL tRP Xa Ya Xa A10 Xa 1 Xa BA0-1 00 00 00 A0-9,11 tWR DQ Da0 Da1 Da2 Da3 internal precharge starts 17 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) BURST INTERRUPTION Read Interrupted by Read Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (CL=2, BL=4) CLK READ READ Command READ A0-9,11 Ya Yb Yc A10 0 0 0 BA0-1 00 00 10 Qa1 Qa2 DQ Qa0 Qb0 Qc0 Qc1 Qc2 Qc3 Read Interrupted by Write Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read Interrupted by Write (CL=2, BL=4) CLK Command ACT READ Write A0-9,11 Xa Ya Ya A10 Xa 0 0 BA0-1 00 00 00 DQM DQ Qa0 Da0 Da1 Da2 Output disable by DQM Da3 by WRITE 18 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Read Interrupted by Precharge A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Precharge (BL=4) CLK Command READ DQ Command PRE Q0 READ Q1 Q2 PRE CL=2 DQ Command Q0 READ PRE DQ Command Q0 READ PRE DQ Command Q1 READ Q0 Q1 Q0 Q1 Q2 PRE CL=3 DQ Command DQ READ PRE Q0 19 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Read Interrupted by Burst Terminate Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Burst Terminate (BL=4) CLK Command READ DQ Command TBST Q0 READ Q1 Q2 TBST CL=2 DQ Command Q0 READ TBST DQ Command Q0 READ TBST DQ Command Q1 READ Q0 Q1 Q0 Q1 Q2 TBST CL=3 DQ Command DQ READ TBST Q0 20 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write Interrupted by Write Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4) CLK Command Write Write Write A0-9,11 Ya Yb Yc A10 0 0 0 BA0-1 00 00 10 Db0 Dc0 DQ Da0 Da1 Da2 Dc1 Dc2 Dc3 Write Interrupted by Read Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write Interrupted by Read (CL=2, BL=4) CLK Command ACT Write READ A0-9,11 Xa Ya Yb A10 Xa 0 0 BA0-1 00 00 00 DQ Da0 Da1 Qb0 Qb1 Qb2 Qb3 don't care 21 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write Interrupted by Precharge Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. Write Interrupted by Precharge (BL=4) CLK Command ACT Write PRE ACT tRP Xa Ya A10 0 0 0 0 BA0-1 00 00 00 00 A0-9,11 Xa DQM tWR DQ Da0 Da1 Write Interrupted by Burst Terminate Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK. Write Interrupted by Burst Terminate (BL=4) CLK TBST Write Command ACT Write A0-9,11 Xa Ya Yb A10 0 0 0 BA0-1 00 00 00 DQ Da0 Da1 Db0 Db1 Db2 Db3 22 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write with Auto-Precharge Interrupted by Write / Read to Different Bank Burst write with auto-precharge can be interrupted by write or read to different bank. Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA Interrupted by WRITE to Different Bank (BL=4) CLK Command ACT Write Write BL A0-9,11 tRP Xa Yb Ya tWR A10 1 0 Xa BA0-1 00 10 00 DQ Da0 Da1 auto-precharge Db0 Db1 Db2 interrupted Db3 activate precharge WRITEA Interrupted by READ to Different Bank (CL=2, BL=4) CLK Command Write ACT Read BL A0-9,11 Ya tRP Xa Yb tWR A10 1 0 Xa BA0-1 00 10 00 DQ Da0 Qb0 Da1 auto-precharge interrupted Qb1 precharge Qb2 Qb3 activate 23 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Read with Auto-Precharge Interrupted by Read to Different Bank Burst read with auto-precharge can be interrupted by read to different bank. Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA Interrupted by READ to Different Bank (CL=2, BL=4) CLK Command Read ACT Read BL tRP Ya Yb Xa A10 1 0 Xa BA0-1 00 10 00 A0-9,11 DQ Qa0 auto-precharge interrupted Qa1 Qb0 precharge Qb1 Qb2 Qb3 activate Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated until a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal. 24 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. Auto-Refresh CLK /CS NOP or DESELECT /RAS /CAS /WE CKE minimum tRFC A0-11 BA0-1 Auto Refresh on All Banks Auto Refresh on All Banks 25 SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan DATA SHEET M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK Stable CLK NOP /CS /RAS /CAS /WE CKE new command A0-11 X BA0-1 00 Self Refresh Entry Self Refresh Exit minimum tRFC for recovery 26 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK tIH tIS tIH tIS CKE int.CLK Power Down by CKE CLK Standby Power Down CKE Command PRE NOP NOP NOP Active Power Down CKE Command ACT NOP NOP NOP DQ Suspend by CKE CLK CKE Command DQ Write D0 Read D1 D2 D3 Q0 Q1 Q2 Q3 27 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) DQM CONTROL DQM* is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to Data In latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. * DQM: DQ0-3 (X32) DQM Function CLK Command Write Read DQM0-3 DQ D0 D2 D3 masked by DQM=H Q0 Q1 Q3 disabled by DQM=H 28 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit VDD Supply Voltage with respect to VSS -0.5 to 4.6 V VDDQ Supply Voltage for Output with respect to VSSQ -0.5 to 4.6 V VI Input Voltage with respect to VSS -0.5 to VDD+0.5 V VO Output Voltage with respect to VSSQ -0.5 to VDD+0.5 V IO Output Current 50 mA Pd Power Dissipation 1000 mW TA Operating Ambient Temperature -40 to 85 oC Tstg Storage Temperature -65 to 150 oC TA=25oC RECOMMENDED OPERATING CONDITIONS (TA=-40 to 85oC, unless otherwise noted) Symbol Parameter VDD Limits Unit Min. Typ. Max. Supply Voltage 3.0 3.3 3.6 V VSS Supply Voltage 0 0 0 V VDDQ Supply Voltage for Output 3.0 3.3 3.6 V VSSQ Supply Voltage for Output 0 0 0 V VIH High-Level Input Voltage all inputs 2.0 VDD+0.3 V VIL Low-Level Input Voltage all inputs -0.3 0.8 V CAPACITANCE (TA=-40 to 85oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted) Symbol Parameter CI(A) Input Capacitance,address pin CI(C) Input Capacitance,control pin CI(K) Input Capacitance,CLK pin CI/O Input Capacitance,I/O pin Test Condition VI=1.4V f=1MHz VI=25mVrms Limits Unit Min. Max. 2.0 4.0 pF 2.0 4.0 pF 2.0 4.0 pF 3.0 6.0 pF 29 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) AVERAGE SUPPLY CURRENT from VDD (TA=-40 to 85oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, Output Open, unless otherwise noted) Symbol Parameter Operating Current (1bank) Icc1 Icc2P Icc2PS Icc2N Icc2NS Icc3N Idle Standby Current in Power Down Mode Idle Standby Current in Normal Mode Test Conditions tCLK=min, tRC=min, BL=1 Limits(max) -6 -7 110 100 Unit Note mA 1 tCLK=min, CKE<VILmax 2 mA 2 tCLK=L, CKE<VILmax 1 mA 2 10 mA 2,3 5 mA 2,4 tCLK=min, CKE>VIHmin, /CS>VIHmin tCLK=L, CKE>VIHmin Active Standby Current in Normal Mode tCLK=min, CKE>VIHmin, /CS> VIHmin 20 mA 3,5 tCLK=L, CKE>VIHmin 10 mA 4,5 Icc4 Burst Operating Current tCLK=min, BL=4, gapless data 120 100 mA 5 Icc5 Auto-Refresh Current tCLK=min, tRFC=min 140 120 mA Icc6 Self-Refresh Current Icc3NS Notes CKE<0.2v 1.0 mA 1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3 x tCLK 4. input signals are stable 5. all banks are active AC OPERATING CONDITIONS AND CHARACTERISTICS (TA=-40 to 85oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted) Symbol Parameter Test Conditions VOH(DC) High-Level Output Voltage (DC) IOH=-2mA VOL(DC) Low-Level Output Voltage (DC) IOL= 2mA IOZ Off-state Output Current Q floating Vo=0 to VDDQ IL Input Current VIH=0 to VDDQ+0.3V, other input pins=0V Limits Min. Max. 2.4 Unit V 0.4 V -10 10 uA -10 10 uA 30 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) AC TIMING REQUIREMENTS (TA=-40 to 85oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted) Input Pulse Levels:0.8V to 2.0V Input Timing Measurement Level:1.4V Limits Symbol Parameter -6I -7I Min. Max. Min. Unit Max. CL=2 10 10 ns CL=3 7.5 10 ns CLK High pulse width 2.5 3 ns tCL CLK Low pulse width 2.5 3 ns tT Transition time of CLK 1 tIS Input Setup time (all inputs) 1.5 2 ns tIH Input Hold time (all inputs) 0.8 1 ns tRC Row Cycle time 67.5 70 ns tCLK CLK cycle time tCH 10 1 10 ns tRFC Refresh Cycle time 75 80 ns tRCD Row to Column Delay 20 20 ns tRAS Row Active time 45 tRP Row Precharge time 20 20 ns tWR Write Recovery time 15 20 ns tRRD ACT to ACT Delay time 15 20 ns tRSC Mode Register Set Cycle time 10 10 ns tREF Refresh Interval time 120000 64 CLK 50 Note 120000 64 ns ms 1.4V Signal 1.4V tIS AC timing is referenced to the input signal crossing through 1.4V. tIH tCLK 31 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) SWITCHING CHARACTERISTICS (TA=-40 to 85oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted) Limits Symbol Parameter -6I Min. tAC tOH -7I Max Min. Unit Max CL=2 6 6 ns CL=3 5.4 6 ns Access Time from CLK CL=2 3 3 ns CL=3 3 3 ns 0 0 ns Output Hold Time from CLK tOLZ Delay Time, Output Low impedance from CLK tOHZ Delay Time, Output High impedance from CLK CL=2 3 6 3 6 ns CL=3 3 5.4 3 6 ns Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters. Output Load Condition Vout 50pF CLK 1.4V DQ 1.4V tOLZ tAC tOHZ tOH 32 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) TIMING CHARTS Burst Write (Single Bank) [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS tWR tWR /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y X Y X 0 D0 0 D0 ACT#0 WRITE#0 D0 D0 0 0 D0 PRE#0 0 D0 ACT#0 WRITE#0 D0 D0 PRE#0 Italic parameter shows minimum case 33 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Burst Write (Multi Bank) [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC tRC /CS tRAS tRRD tRP /RAS tRCD tRCD tRCD /CAS tWR tWR /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y X Y X X 0 1 D0 D0 ACT#0 WRITE#0 ACT#1 Y X X D0 D0 1 0 D1 D1 PRE#0 D1 X 0 0 D1 D0 1 D0 D0 ACT#0 WRITE#0 WRITEA#1 (Auto-Precharge) 0 D0 PRE#0 ACT#1 Italic parameter shows minimum case 34 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Burst Read (Single Bank) [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRAS tRP tRAS /RAS tRCD tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 Y X X 0 0 Q0 DQ ACT#0 Y READ#0 Q0 Q0 PRE#0 0 0 Q0 0 Q0 ACT#0 READ#0 Q0 Q0 Q0 PRE#0 Italic parameter shows minimum case 35 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Burst Read (Multi Bank) [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC tRC /CS tRRD tRAS /RAS tRCD tRCD tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 Y X Y X X 0 1 Q0 Q0 Q0 X 0 Q0 ACT#0 READA#0 ACT#1 X X 1 DQ Y Q1 ACT#0 READA#1 0 Q1 Q1 1 Q1 Q0 READ#0 0 Q0 Q0 Q0 PRE#0 ACT#1 Italic parameter shows minimum case 36 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write Interrupted by Write [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD /CAS tWR /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y X Y Y Y X X 0 1 D0 D0 ACT#0 WRITE#0 ACT#1 X 0 D0 D0 1 D0 WRITE#0 interrupt same bank D1 0 D1 WRITEA#1 interrupt other bank D1 D0 0 D0 WRITE#0 interrupt other bank D0 1 D0 PRE#0 ACT#1 Italic parameter shows minimum case 37 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Read Interrupted by Read [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 Y X Y Y X X 0 X 1 1 Q0 DQ ACT#0 Y READ#0 ACT#1 Q0 1 Q0 READ#1 interrupt other bank Q1 0 Q1 READA#1 interrupt same bank Q1 Q1 1 Q1 READ#0 interrupt other bank Q0 Q0 Q0 Q0 ACT#1 Italic parameter shows minimum case 38 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write Interrupted by Read, Read Interrupted by Write [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-9,11 X X A10 X X BA0,1 0 1 Y Y Y 0 1 1 D0 DQ ACT#0 D0 WRITE#0 READ#1 Q1 Q1 D1 1 D1 WRITE#1 D1 D1 PRE#1 ACT#1 Italic parameter shows minimum case 39 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write / Read Terminated by Precharge [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRP tRAS tRP /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y X Y X X 0 D0 0 0 D0 ACT#0 WRITE#0 X 0 0 Q0 PRE#0 Terminate ACT#0 0 Q0 READ#0 PRE#0 Terminate ACT#0 Italic parameter shows minimum case 40 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Write / Read Terminated by Burst Terminate [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS tWR /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y Y Y 0 0 0 D0 D0 Q0 ACT#0 WRITE#0 TBST READ#0 TBST Q0 D0 0 D0 WRITE#0 D0 D0 PRE#0 Italic parameter shows minimum case 41 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Single Write Burst Read [CL=2,BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 Y Y 0 0 D0 DQ ACT#0 WRITE#0 Q0 Q0 Q0 Q0 READ#0 Italic parameter shows minimum case 42 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Power-Up Sequence and Initialize CLK 100us /CS tRP tRFC tRFC tRSC /RAS /CAS /WE CKE DQM A0-9,11 MA X A10 0 X BA0,1 0 0 MRS ACT#0 DQ DESEL Power On PRE ALL REFA REFA REFA Minimum 2 REFA cycles Italic parameter shows minimum case 43 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Auto Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRFC /CS tRP /RAS tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 Y 0 D0 DQ PRE ALL REFA D0 D0 D0 ACT#0 WRITE#0 All banks must be idle before REFA is issued. Italic parameter shows minimum case 44 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Self Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRFC /CS tRP /RAS /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ PRE ALL Self Refresh Entry Self Refresh Exit ACT#0 All banks must be idle before REFS is issued. Italic parameter shows minimum case 45 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) CLK Suspension [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9,11 X A10 X BA0,1 0 DQ Y Y 0 0 D0 D0 D0 ACT#0 WRITE#0 Internal CLK suspended D0 Q0 READ#0 Q0 Q0 Q0 Q0 Internal CLK suspended Italic parameter shows minimum case 46 DATA SHEET SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE Standby Power Down Active Power Down CKE DQM A0-9,11 X A10 X BA0,1 0 DQ PRE ALL ACT#0 Italic parameter shows minimum case 47 SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan DATA SHEET M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 48 SDR SDRAM E0364M20 (Ver.2.0) (Previous Rev.0.3e) June 2004 (K) Japan DATA SHEET M2V64S50ETP-I 64M Single Data Rate Synchronous DRAM WTR (Wide Temperature Range) The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 49