Real time clock module I2 C-BUS COMPATIBLE REAL TIME CLOCK MODULE RTC-8583/8593 series • Builtin crystal unit. Adjustment free with 10pF external capacitor. • Small package (SOP 14-pin). • Three mode operations: internal crystal oscillation, external 50 Hz clock and event counter. • I C-Bus inter face compatible. • Builtin 240 x 8 bit S-RAM available (RTC8583). • Alarm and timer functions available. • Wide operating voltage range 2.5V to 6.0V. • Wide data hold voltage range 1.0V to 6.0V. • Low current consumption (RTC8593, 1.0µA typical). 2 Specifications (characteristics) Absolute Max. rating Symbol Condition Supply voltage VDD VDD-GND Input voltage VIN Input current Ii Output current Io Item Storage temperature Actual size The I 2 C-Bus is a trademark of Philips Electronics N.V. Terminal connection Max. Min. Unit RTC-8583/8593 +7.0 -0.8 V VDD+0.8 10 mA -55 +125 ˚C Min. Max. Unit 6.0 V +70 ˚C TSTG 14 13 12 11 10 9 8 1 7 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Operating range Item Condition Symbol Operating voltage VDD 2.5 Data holding voltage VCLK 1.0 Operating temperature TOPR -30 External capacitor CG 2 3 4 5 6 RTC-8593SB 18 17 16 15 14 13 12 11 10 pF 10±5% Frequency characteristics Symbol Condition Max. Unit ∆f/fo Ta=25˚C, VDD=5V Frequency temperature characteristics Top Ta=-10 to 70˚C, VDD=5V A: 5±20 B: 5±50 +10 -120 Frequency voltage characteristics Oscillation start-up time fv Ta=25˚C, VDD=2.0 to 6.0V ±3 tOSC Ta=25˚C, VDD=5V 3 s Ta=25˚C, VDD=5V ±5 ppm/year fa first year Symbol Condition VIH — 0.7VDD VDD+0.8 IOL VOL=0.4V 0.3 IL VIN=VDD or GND RESET Leak current 8 9 External dimensions (Unit: mm) V R8593 B E 607 6A mA 3 Input leak current AO ______ 7 Min. Typ. Max. Unit -0.8 VIL SDA “L” output current 6 OSC1 1 µA 250 nA 10.1±0.2 0˚ to 10˚ ___ IL VIN=VDD or GND 1 SCL Source current (access) IDD0 fSCL=100 kHz 200 R8593 B E Current Consumption (non access) 1 IDD1 VDD=5V, fSCL=0 Hz 10 50 8583 2 IDD2 VDD=3V, fSCL=0 Hz 3.5 15 3 IDD3 VDD=2V, fSCL=0 Hz 2.0 10 1 IDD1 VDD=5V, fSCL=0 Hz 3.0 15 8593 2 IDD2 VDD=3V, fSCL=0 Hz 1.2 10 3 IDD3 VDD=2V, fSCL=0 Hz 1.0 8 607 6A µA 11.4±0.2 0˚ to 10˚ 0.6 59 0.15 RTC-8593SB (SOP 18-pin) INT Leak current 0.05 min. 0.6 mA VOL=0.4V 5.4 ___ 1 IOL 1.8 INT Output current 7.8±0.2 “L” input voltage 4 5 2.0 max. “H” input voltage 2 3 RTC-8583/8593 (SOP 14-pin) DC characteristics Item 1 5.0 Aging ppm 8593 8593SB N.C N.C SCL N.C SDA N.C N.C N.C GND N.C N.C N.C RESET N.C OSC1 RESET N.C GND N.C SDA VDD SCL N.C INT N.C VDD OSC1 INT N.C N.C N.C N.C 7.4±0.2 Frequency tolerance 3.1 3.2±0.1 Item 8583 GND1 SCL SDA N.C GND N.C A0 OSC1 N.C N.C VDD N.C N.C INT 0.05 min. 0.15 Real time clock module Register table bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STOP HOLD MODE1 MODE2 MASK ALM AF TF 2/10 1/10 8/100 4/100 2/100 1/100 10S2 10S1 S8 S4 S2 S1 Address Register name 00 CNT 01 1/100SEC 0 to 99 8/10 4/10 02 SEC 0 to 59 10S8 10S4 03 MIN 0 to 59 10MIN8 10MIN4 10MIN2 10MIN1 MIN8 MIN4 MIN2 MIN1 04 HOUR 0 to 23 12/24 AM/PM 10HOUR2 10HOUR1 HOUR8 HOUR4 HOUR2 HOUR1 05 DAY 0 to 31 YEAR2 YEAR1 10DAY2 10DAY1 DAY8 DAY4 DAY2 DAY1 06 MONTH 0 to 12 W4 W2 W1 10MONTH1 MONTH8 MONTH4 MONTH2 MONTH1 07 TIMER 0 to 99 10TIMER8 10TIMER4 10TIMER2 10TIMER1 TIMER8 TIMER4 TIMER2 TIMER1 08 ALARM AIE TAIE AS1 AS0 TIE TCP2 TCP1 TCP0 count 09 A-1/100 0 to 99 A-8/10 A-4/10 A-2/10 A-1/10 A-8/100 A-4/100 A-2/100 A-1/100 0A A-SEC 0 to 59 10A-SEC8 10A-SEC4 10A-SEC2 10A-SEC1 10A-SEC8 10A-SEC4 10A-SEC2 10A-SEC1 0B A-MIN 0 to 59 10A-MIN8 10A-MIN4 10A-MIN2 10A-MIN1 10A-MIN8 10A-MIN4 10A-MIN2 10A-MIN1 0C A-HR 0 to 23 A-12/24 A-AM/PM 10A-HR2 10A-HR1 A-HR8 A-HR4 A-HR2 A-HR1 0D A-DAY 0 to 31 A-DAY2 A-DAY1 0E A-MON 0 to 12 0F A-TIM 0 to 99 10 to FF — — 10A-TIM8 A-DAY1 A-DAY8 A-DAY4 10A-MON1 10A-MON8 10A-MON4 10A-MON2 10A-MON1 10A-TIM1 A-TIM8 A-TIM4 A-TIM2 A-TIM1 A-DAY2 10A-TIM4 10A-TIM2 User's RAM (RTC-8583 is available) 0 to FF Timing chart Switching characteristics Symbol Item fSCL SCL clock frequency Spike tolerance on bus tSW Bus free time tBUF Min. Max. — 100 Unit KHz Protocol ns Start Condition (s) Bit 7 MSB (A7) t SU: STA t LOW t SUF tSU; STA Hold time tHD; STA 4.0 SCL “L” time tLOW 4.7 SCL “H” time tHIGH 4.0 SCL, SDA rise time tTLH SCL, SDA fall time tTHL µs Protocol 0.3 250 Date hold time tHD; DAT 0 SCL low to data out valid tVD; DAT — — t THL t HD: STA 1.0 tSU; DAT t TLH SDA — — Date set-up time 1/f SCL SCL 4.7 Start condition set-up time t HIGH Bits (A6) ns BITO LSB (R/W) t SU: DAT ACK (A) t HD: DAT STOP Condition (p) SCL 3.4 SDA µs Stop condition set-up time tSU; STO 4.0 — fi — 1.0 Event counter frequency t SU: STO t VD: DAT MHz Block diagram RTC-8583 RTC-8593 Series 32.768 KHz 32.768 KHz OSC1 OSC1 OSC Cg=10pF Divider INT Power-ON RESET Control Logic Register & Counter V DD SCL SDA 2 I C-BUS Interface Control Logic GND RESET AO Divider INT V DD GND1.2 OSC Cg=10pF Register & Counter RESET 2 Address Register RAM (8 x 240) SCL I C-BUS Interface Address Register SDA 60