ESMT M24D16161DA

ESMT
M24D16161DA
Revision History :
Revision 1.0 (Jul. 6, 2007)
- Original
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
1/12
ESMT
PSRAM
M24D16161DA
16-Mbit (1M x 16)
Pseudo Static RAM
Features
CE2 LOW), outputs are disabled ( OE HIGH), both Byte High
• Wide voltage range: 1.7V–1.95V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
‧Available in 48-ball BGA package
• Operating Temperature: –40°C to +85°C
Enable and Byte Low Enable are disabled ( BHE , BLE
Functional Description[1]
The M24D16161DA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal portable applications such as cellular telephones.
The device can be put into standby mode when deselected
( CE1 HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input/output pins (I/O0 through I/O15) are placed in
HIGH), or during a write operation ( OE1 LOW and CE2
HIGH and WE LOW).
To write to the device, take Chip Enable ( CE1 LOW and
CE2HIGH) and Write Enable ( WE ) input LOW. If Byte Low
Enable( BLE ) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0through A19). If Byte High Enable ( BHE ) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the
location specified on the address pins (A0 through A19).
To read from the device, take Chip Enables ( CE1 LOW and
CE2 HIGH) and Output Enable ( OE ) LOW while forcing the
Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is
LOW, then data from memory will appear on I/O8 to
I/O15.Refer to the truth table for a complete description of read
and write modes.
a high-impedance state when : deselected ( CE1 HIGH or
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
2/12
ESMT
M24D16161DA
Pin Configuration[2, 3]
48-ball VFBGA
Top View
Product Portfolio[4]
Power Dissipation
VCC Range (V)
Product
M24D16161DA
Speed(ns)
Min.
Typ.[4]
Max
1.7
1.8
1.95
70
Operating ICC(mA)
f = 1MHz
f = fmax
.Typ.[4] Max.
.Typ.[4]
Max
3
5
18
20
Standby ISB2(µA)
.Typ. [4]
Max
55
70
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select should be OE1 HIGH or CE2 LOW for at least 200 µs
after VCC has reached a stable value. No access must be
attempted during this period of 200 µs.
Parameter
TPU
Description
Chip Enable Low After Stable VCC
Min.
200
Max.
Unit
µs
Notes:
2.Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively.
3.NC “no connect”-not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C. Tested initially and after design changes that may affect the parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
3/12
ESMT
M24D16161DA
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential.–0.2V to VCCMAX + 0.3V
DC Voltage Applied to Outputs
in High Z State[5, 6, 7]........................–0.2V to VCCMAX + 0.3V
DC Input Voltage[5, 6, 7]....................–0.2V to VCCMAX + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
Operating Range
Range
Industrial
Ambient
Temperature (TA)
−40°C to +85°C
VCC
1.7V to 1.95V
DC Electrical Characteristics (Over the Operating Range) [5, 6, 7]
Parameter
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
-70
Test Conditions
Min.
1.7
IOH = −0.1 mA
VCC = 1.7V to 1.95V
IOL = 0.1 mA,
VCC = 1.7V to 1.95V
Typ.[4]
1.8
ISB1
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
V
VCC-0.2
V
0.2
V
VCC = 1.7V to 1.95V
0.8* VCC
VCC+0.3V
V
VCC = 1.7V to 1.95V
-0.2
0.2* VCC
V
GND ≤ VIN ≤ VCC
-1
+1
µA
GND ≤ VOUT ≤ VCC
-1
+1
µA
18
25
mA
3
5
mA
55
70
µA
55
70
µA
VCC= VCCmax
IOUT = 0mA
CMOS levels
f = fMAX = 1/tRC
f = 1 MHz
Automatic CE
Power-Down
Current
—CMOS Inputs
Unit
Max.
1.95
CE ≥ VCC − 0.2V, CE2 ≤ 0.2V, VIN > VCC
− 0.2V, VIN < 0.2V, f = fMAX (Address and
Data Only), f = 0
( OE ,
WE ,
BHE and BLE ), VCC=3.60V
CE1 ≥ VCC−0.2V, CE2 ≤ 0.2V, VIN ≥
VCC − 0.2V or VIN ≤ 0.2V, f = 0, VCC =
VCCMAX,
Capacitance[8]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
8
8
pF
pF
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Thermal Resistance[8]
Parameter
ΘJA
ΘJC
Description
Test Conditions
VFBGA
Unit
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal
impedence, per EIA/JESD51.
56
°C/W
11
°C/W
Notes:
5. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
6.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
7.Overshoot and undershoot specifications are characterized and are not 100% tested.
8.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
4/12
ESMT
M24D16161DA
AC Test Loads and Waveforms
Parameters
R1
R2
RTH
VTH
1.8V VCC
14000
14000
7000
1.90
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Read Cycle
tRC[13]
tCD
tAA
tOHA
tACE
Description
Read Cycle Time
Chip Deselect Time CE1 =HIGH or CE2=LOW,
BLE / BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
-70
Unit
Min.
Max.
70
40000
ns
ns
70
15
CE1 LOW to Data Valid
70
ns
ns
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[10, 11, 12]
tHZOE
OE HIGH to High Z[10, 11, 12]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[10, 11, 12]
tHZCE
CE1 HIGH and CE2 LOW to High Z[10, 11, 12]
25
ns
tDBE
BLE / BHE LOW to Data Valid
70
ns
tLZBE
BLE / BHE LOW to Low Z[10, 11, 12]
tHZBE
BLE / BHE HIGH to High Z[10, 11, 12]
5
ns
5
25
ns
ns
10
ns
5
25
ns
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ.)/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads
and Waveforms” section.
10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13 .If invalid address signals shorter than min. tRC are continuously repeated for 40 µs, the device needs a normal read timing
(tRC) or needs to enter standby state at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable ( CE1 or CE2) controlled. That is, the
addresses must be stable prior to Chip Enable going active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
5/12
ESMT
M24D16161DA
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Write Cycle[15]
tWC
tSCE
tAW
tCD
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Chip Deselect Time CE1 = HIGH or CE2 = LOW,
BLE / BHE High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
-70
Min.
Max.
70
60
60
40000
Unit
ns
ns
ns
ns
15
0
0
50
ns
ns
ns
60
ns
25
0
ns
ns
ns
25
WE LOW to High-Z[10, 11, 12]
WE HIGH to Low-Z[10, 11, 12]
(continued)
10
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE , CE1 = VIL or CE2 = VIH, BHE and/or BLE = VIL.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data
input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
6/12
ESMT
M24D16161DA
Switching Wave forms
Read Cycle 1 (Address Transition Controlled)[17, 18]
Read Cycle 2 ( OE Controlled)[16, 18,19]
Notes:
16.Whenever CE1 = HIGH or CE2 = LOW, BHE / BLE are taken inactive, they must remain inactive for a minimum of 5 ns.
17.Device is continuously selected. OE = CE1 = VIL and CE2 = VIH.
18. WE is HIGH for Read Cycle.
19. CE is the Logical AND of CE1 and CE2.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
7/12
ESMT
M24D16161DA
Switching Waveforms (continued)
Notes:
20.Data I/O is high-impedance if OE ≥ VIH.
21.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
8/12
ESMT
M24D16161DA
Switching Waveforms (continued)
Write Cycle 2 ( CE1 or CE2 Controlled)[15, 12, 16, 20, 21]
Write Cycle 3 ( WE Controlled, OE LOW)[16, 21]
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
9/12
ESMT
M24D16161DA
Switching Waveforms (continued)
Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[15, 16, 20, 21]
Truth Table[22]
CE1
H
X
X
CE2
X
L
X
WE
X
X
X
OE
X
X
X
BHE
X
X
H
BLE
X
X
H
L
H
H
L
L
L
L
H
H
L
H
L
L
H
H
L
L
H
L
H
H
H
L
L
L
H
H
H
H
L
H
H
H
L
H
L
L
H
L
H
Inputs/Outputs
High Z
High Z
High Z
Mode
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Data Out (I/O0–I/O15)
Read
Active (ICC)
Read
Active (ICC)
Read
Active (ICC)
High Z
Output Disabled
Active (ICC)
L
High Z
Output Disabled
Active (ICC)
L
H
High Z
Output Disabled
Active (ICC)
X
L
L
Data In (I/O0–I/O15)
Write (Upper Byte and Lower
Byte)
Active (ICC)
L
X
H
L
Write (Lower Byte Only)
Active (ICC)
L
X
L
H
Write (Upper Byte Only)
Active (ICC)
Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Notes:
22.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
10/12
ESMT
M24D16161DA
Ordering Information
Speed (ns)
70
Ordering Code
M24D16161DA -70BIG
Package Type
48-ball Very Fine Pitch BGA (6 x 8 x 1 mm) (Pb-Free)
Operating Range
Industrial
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
11/12
ESMT
M24D16161DA
Important Notice
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No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
12/12