ESMT M24L216128SA

ESMT
PSRAM
M24L216128SA
2-Mbit (128K x 16)
Pseudo Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 1mA @ f = 1 MHz
— Typical active current: 14 mA @ f = fmax (For 55-ns)
—Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The M24L216128SA is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the chip is deselected ( CE
when both Byte High Enable and Byte Low Enable are
disabled ( BHE , BLE HIGH), or during a write operation
( CE LOW and WE LOW).
Writing to the device is accomplished by asserting Chip
Enable ( CE LOW) and Write Enable ( WE ) input LOW. If
Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A16).
Reading from the device is accomplished by asserting Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 to I/O15. Refer to the truth table for a complete description
of read and write modes.
HIGH), or when the outputs are disabled ( OE HIGH), or
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
1/14
ESMT
M24L216128SA
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
44-pin TSOPII
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V CC
V SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
Elite Semiconductor Memory Technology Inc.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BL E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
V SS
V CC
I/ O1 1
I/ O1 0
I/ O9
I/ O8
NC
A8
A9
A1 0
A1 1
NC
Publication Date : Jul. 2008
Revision : 1.2
2/14
ESMT
M24L216128SA
Product Portfolio Product
Power Dissipation
VCC Range (V)
Product
M24L216128SA
Speed(ns)
Min.
Typ.
Max.
2.7
3.0
3.6
55
70
Operating ICC(mA)
f = 1MHz
Typ.[5]
Max.
1
5
Standby ISB2(µA)
f = fmax
Typ.[5]
Max.
14
22
8
15
Typ. [5]
Max.
9
40
Notes:
2.Ball D3, H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 4-Mbit, 8-Mbit, 16-Mbit and a 32-Mbit density,
respectively.
3.NC “no connect”—not connected internally to the die.
4.DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.
5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.),
TA = 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
3/14
ESMT
M24L216128SA
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ..................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[3, 4, 5] .......................................−0.4V to 3.7V
DC Input Voltage[3, 4, 5] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ...............................20 mA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Extended
Industrial
Ambient
Temperature(TA)
−25°C to +85°C
−40°C to +85°C
VCC
2.7V to 3.6V
2.7V to 3.6V
Electrical Characteristics (Over the Operating Range)
-55
Parameter
Description
Test Conditions
Min.
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
ICC
VCC Operating
Supply Current
ISB1
Automatic CE
Power-Down
Current
—CMOS Inputs
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
IOH = −0.1 mA
VCC = 2.70V
IOL = 0.1 mA
VCC = 2.70V
2.7
VCC0.4
Typ
.[5]
3.0
-70
Max.
Min.
3.6
2.7
VCC0.4
Typ.
[5]
3.0
Unit
Max.
3.6
V
0.4
0.4
CIN
COUT
VCC+
0.4V
0.4
0.8*
VCC
-0.4
VCC+
0.4V
0.4
GND ≤ VIN ≤ VCC
-1
+1
-1
+1
µA
GND ≤ VOUT ≤ VCC, Output Disabled
-1
+1
-1
+1
µA
f = fMAX = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0mA
CMOS levels
CE ≥ VCC − 0.2V
VIN ≥ VCC − 0.2V, VIN ≤ 0.2V, f = fMAX
(Address and Data Only), f = 0 ( OE ,
V
V
14
22
8
15
mA
1
5
1
5
mA
40
250
40
250
µA
9
40
9
40
µA
WE , BHE and BLE ), VCC=3.6V
CE ≥ VCC−0.2V
VIN ≥ VCC − 0.2V or VIN ≤ 0.2V, f = 0,
VCC =3.6V
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
Unit
8
8
pF
pF
Thermal Resistance[9]
Parameter
ΘJA
V
0.8*
VCC
-0.4
VCC = 2.7V to 3.6V
Capacitance[9]
Parameter
V
Description
Thermal Resistance(Junction to Ambient)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
ΘJC
Thermal Resistance (Junction to Case)
Notes: 6.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
7.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
BGA
55
Unit
°C/W
17
°C/W
Publication Date : Jul. 2008
Revision : 1.2
4/14
ESMT
M24L216128SA
AC Test Loads and Waveforms
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[10]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
Description
Max.
CE LOW to Data Valid
55
70
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to LOW Z[11, 13]
tHZOE
OE HIGH to High Z[11, 13]
tLZCE
CE LOW to Low Z[11, 13]
tHZCE
CE HIGH to High Z[11, 13]
25
25
ns
tDBE
BLE / BHE LOW to Data Valid
55
70
ns
tLZBE
BLE / BHE LOW to Low Z[11, 13]
tHZBE
BLE / BHE HIGH to HIGH Z[11, 13]
Address Skew
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
70
Unit
tDOE
Write Cycle Time
55[14]
-70
Min.
ns
ns
ns
ns
tSK[14]
Write Cycle[12]
tWC
tSCE
tAW
tHA
tSA
tPWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
-55 [14]
Min.
Max.
55
5
70
10
5
25
2
25
ns
5
10
0
25
10
70
60
60
0
0
45
ns
ns
5
5
55
45
45
0
0
40
ns
5
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test
Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.12.The internal Write
time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
5/14
ESMT
M24L216128SA
Switching Characteristics Over the Operating Range (continued)[10]
Parameter
Description
-55 [14]
Min.
Max.
50
-70
Min.
60
Unit
Max.
tBW
BLE/BHE LOW to Write End
tSD
Data Set-Up to Write End
25
45
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High-Z[11, 13]
tLZWE
WE HIGH to Low-Z[11, 13]
25
5
ns
25
5
ns
ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[15, 16, 17]
Read Cycle 2 ( OE Controlled)[16, 17]
Notes:
15. Device is continuously selected. OE , CE = VIL.
16. WE is HIGH for Read Cycle.
17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the
addresses must be stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
6/14
ESMT
M24L216128SA
Switching Waveforms (continued)
Write Cycle 1 ( WE Controlled)[12, 13, 18, 19, 20]
Write Cycle 2 ( CE Controlled)[12, 13, 18, 19, 20]
Notes:
18.Data I/O is high impedance if OE ≥ VIH.
19.If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
20.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
7/14
ESMT
M24L216128SA
Switching Waveforms (continued)
Write Cycle 3 ( WE Controlled, OE LOW)[19, 20]
Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[19, 20]
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
8/14
ESMT
M24L216128SA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧15μ s
CE
WE
＜ tRC
Address
Avoidable Timing 1
≧15μ s
CE
WE
≧ tRC
Address
Avoidable Timing 2
≧15μ s
CE
≧ tRC
WE
＜ tRC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
9/14
ESMT
M24L216128SA
Truth Table[21]
CE
H
X
L
WE
X
X
H
OE
X
X
L
BHE
X
H
L
BLE
X
H
L
L
H
L
H
L
L
H
L
L
H
L
H
H
L
L
H
H
L
H
L
Inputs/Outputs
High Z
High Z
Data Out (I/O0–I/O15)
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Mode
Deselect/Power-Down
Deselect/Power-Down
Read
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Read
Active (ICC)
H
High Z
Output Disabled
Active (ICC)
H
L
High Z
Output Disabled
Active (ICC)
H
L
L
High Z
Output Disabled
Active (ICC)
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Write
Active (ICC)
L
L
X
L
H
Write
Active (ICC)
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Read
Active (ICC)
Note:
21.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Ordering information
Speed(ns)
Ordering Code
Package Type
Operating Range
55
M24L216128SA-55BEG
48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free)
Extended
70
M24L216128SA-70BEG
48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free)
Extended
55
M24L216128SA-55TEG
44-pin TSOPII (Pb-free)
Extended
70
M24L216128SA-70TEG
44-pin TSOPII (Pb-free)
Extended
55
M24L216128SA-55BIG
48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free)
Industrial
70
M24L216128SA-70BIG
48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free)
Industrial
55
M24L216128SA-55TIG
44-pin TSOPII (Pb-free)
Industrial
70
M24L216128SA-70TIG
44-pin TSOPII (Pb-free)
Industrial
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
10/14
ESMT
M24L216128SA
Package Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
11/14
ESMT
44-LEAD
M24L216128SA
TSOP(II)
Symbol
PRAM(400mil)
Dimension in mm
Min
Norm
A
Dimension in inch
Max
Min
Norm
1.20
A1
0.05
A2
0.95
B
0.30
B1
0.30
C
Max
0.047
0.15
0.002
1.05
0.037
0.45
0.012
0.40
0.012
0.12
0.21
0.005
0.008
C1
0.10
0.16
0.004
0.006
D
18.28
18.54
0.720
ZD
1.00
0.35
18.41
0.805
REF
0.006
0.039
0.042
0.018
0.014
0.725
0.016
0.730
0.0317 REF
E
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.4
L
0.40
0.59
0.69
0.016
0.023
0.027
L1
0.80 REF
e
0.80 BSC
θ
0°
Elite Semiconductor Memory Technology Inc.
0.031
REF
0.0315 BSC
8°
0°
8°
Publication Date : Jul. 2008
Revision : 1.2
12/14
ESMT
M24L216128SA
Revision History
Revision
Date
1.0
2007.05.11
1.1
2008.02.29
1.2
2008.07.04
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Add 44-pin TSOPII package
2. Add Avoid timing
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade
Publication Date : Jul. 2008
Revision : 1.2
13/14
ESMT
M24L216128SA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
14/14