ESMT M24L416256DA

ESMT
PSRAM
M24L416256DA
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Advanced low-power architecture
reducing power consumption dramatically when deselected
•High speed: 55 ns, 60 ns and 70 ns
( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
•Wide voltage range: 2.7V to 3.6V
high-impedance state when: deselected ( CE1 HIGH, CE2
•Typical active current: 1 mA @ f = 1 MHz
LOW, OE
is HIGH), or during a write operation (Chip
Enabled and Write Enable WE LOW).
•Low standby power
•Automatic power-down when deselected
Reading from the device is accomplished by asserting the
Chip Enables ( CE1 LOW and CE2 HIGH) and Output
Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH.
Functional Description
The M24L416256DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode
Elite Semiconductor Memory Technology Inc.
If Byte Low Enable ( BLE ) is LOW, then data from the memory
location specified by the address pins A0 through A17 will
appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table for a complete description of read and write
modes.
Publication Date: Jul. 2008
Revision: 1.5
1/15
ESMT
M24L416256DA
Pin Configuration[3, 4, 5]
44-pin TSOPII
Top View
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
V CC
V SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
Elite Semiconductor Memory Technology Inc.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BL E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
V SS
V CC
I/ O1 1
I/ O1 0
I/ O9
I/ O8
CE2
A8
A9
A1 0
A11
A1 7
Publication Date: Jul. 2008
Revision: 1.5
2/15
ESMT
M24L416256DA
Product Portfolio
Power Dissipation
VCC Range(V)
Product
Min.
Typ.
Speed
(ns)
Max.
Operating, ICC (mA)
f = 1 MHz
Typ.[2]
Max.
1
5
55
M24L416256DA
2.7
3.0
3.6
60
70
Standby, ISB2 (µA)
f = fMAX
Typ.[2]
Max.
14
22
8
15
Typ.[2]
Max.
17
40
Notes:
2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C.
3.Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively.
4.NC “no connect”—not connected internally to the die.
5.DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
3/15
ESMT
M24L416256DA
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Ambient Temperature (TA)
VCC
Extended
−25°C to +85°C
2.7V to 3.6V
Industrial
−40°C to +85°C
2.7V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
Parameter
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Test Conditions
IOH = −0.1 mA
ISB1
ISB2
Automatic CE1
Power-down
Current —CMOS
Inputs
Capacitance[9]
Parameter
CIN
COUT
Unit
Max.
3.6
V
VCC – 0.4
V
IOL = 0.1 mA
0.4
V
0.8 * VCC
VCC + 0.4
V
-0.4
0.62
V
GND ≤ VIN ≤ Vcc
-1
+1
µA
GND ≤ VOUT ≤ Vcc, Output
Disabled
-1
+1
µA
14 for –55
14 for –60
08 for –70
1 for all speeds
22 for –55
22 for –60
15 for –70
5 for all speeds
mA
150
250
µA
17
40
µA
F=0
f = fMAX = 1/tRC
f = 1 MHz
Automatic CE1
Power-down
Current —CMOS
Inputs
-55, 60, 70
Typ.[2]
3.0
Min.
2.7
VCC = 3.6V,
IOUT = 0 mA,
CMOS level
CE1 ≥ VCC − 0.2V, CE2 ≤
0.2V, VIN ≥ VCC − 0.2V, VIN ≤
0.2V, f = fMAX(Address and Data
Only),f = 0 ( OE , WE , BHE and
BLE )
CE1 ≥ VCC − 0.2V, CE2 ≤
0.2V, VIN ≥ VCC − 0.2V or VIN
≤ 0.2V, f = 0, VCC = 3.6V
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Thermal Resistance[9]
Parameter
Description
θJA
Thermal Resistance (Junction to Ambient)
θJC
Thermal Resistance (Junction to Case)
Max.
8
8
Unit
pF
pF
Test Conditions
VFBGA
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
55
°C/W
17
°C/W
Notes:
6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.
7.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
4/15
ESMT
M24L416256DA
AC Test Loads and Waveforms
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[10]
Prameter
Description
Read Cycle
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
–55
Min.
–60
Max.
55[14]
Min.
–70
Max.
Max.
CE1 LOW and CE2 HIGH to Data Valid
55
60
70
tDOE
OE LOW to Data Valid
25
25
35
ns
tLZOE
OE LOW to Low Z[11, 12]
tHZOE
OE HIGH to High Z[11, 12]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[11,
12]
tHZCE
CE1 HIGH and CE2 LOW to High Z[11,
12]
tDBE
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[11, 12]
55
5
60
8
5
5
5
25
5
25
ns
25
5
25
55
5
70
10
5
25
tHZBE
70
Unit
ns
ns
ns
ns
tLZBE
60
Min.
ns
25
60
5
ns
70
5
ns
ns
ns
10
10
25
ns
0
5
10
ns
BLE / BHE HIGH to High-Z[11, 12]
[14]
tSK
Address Skew
Write Cycle[13]
tWC
Write Cycle Time
tSCE
CE1 LOW and CE2 HIGH to Write End
55
45
60
45
70
60
ns
ns
tAW
tHA
tSA
45
0
0
45
0
0
55
0
0
ns
ns
ns
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
Notes:
10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V
to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.
11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input
set-up and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
5/15
ESMT
M24L416256DA
Switching Characteristics (Over the Operating Range)[10] (continued)
Prameter
Description
tPWE
WE Pulse Width
tBW
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
tSD
tHD
tHZWE
tLZWE
Min.
40
Max.
Min.
40
–70
Max.
Min.
45
Max.
ns
50
55
ns
25
0
25
0
25
0
ns
ns
ns
25
5
25
5
25
5
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]
Read Cycle 2 ( OE Controlled)[14, 16]
Notes:
15.Device is continuously selected. OE , CE = VIL.
16. WE is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Unit
50
WE LOW to High Z[11, 12]
WE HIGH to Low Z[11, 12]
–60
–55
Publication Date: Jul. 2008
Revision: 1.5
6/15
ns
ESMT
M24L416256DA
Switching Waveforms (continued)
Write Cycle No. 1( WE Controlled)[12, 13, 17, 18, 19]
Notes:
17.Data I/O is high impedance if OE > VIH.
18.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state.
19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
7/15
ESMT
M24L416256DA
Switching Waveforms (continued)
Write Cycle 2 ( CE1 or CE2 Controlled)[12, 13, 17, 18, 19]
Write Cycle 3 ( WE Controlled, OE LOW)[18, 19]
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
8/15
ESMT
M24L416256DA
Switching Waveforms (continued)
Write Cycle No. 4 ( BHE / BLE Controlled, OE LOW)[18, 19]
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
9/15
ESMT
M24L416256DA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE1 to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧15μs
CE1
WE
＜ tRC
Address
Avoidable Timing 1
≧15μs
CE1
WE
≧ tRC
Address
Avoidable Timing 2
≧15μs
CE1
≧ tRC
WE
＜ tRC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
10/15
ESMT
M24L416256DA
Truth Table[20]
CE1
H
X
X
L
CE2
OE
X
L
X
H
WE
X
X
X
H
L
H
L
X
X
X
L
BHE
X
X
H
L
BLE
X
X
H
L
H
L
H
L
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
L
L
L
H
L
L
H
L
X
H
L
L
H
L
X
L
H
Inputs/Outputs
Mode
Power
High Z
High Z
High Z
Data Out (I/O0–I/O15)
Data Out (I/O0–I/O7);
I/O8–I/O15 in High Z
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
High Z
High Z
High Z
Data In (I/O0–I/O15)
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read (Upper Byte and Lower Byte)
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Read (Upper Byte only)
Active (ICC)
Read (Lower Byte only)
Active (ICC)
Output Disabled
Output Disabled
Output Disabled
Write (Upper Byte and Lower Byte)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Write (Lower Byte Only)
Active (ICC)
Write (Upper Byte Only)
Active (ICC)
Note:
20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Ordering Information
Speed (ns)
55
60
70
55
60
70
55
60
70
55
60
70
Ordering Code
M24L416256DA-55BEG
M24L416256DA-60BEG
M24L416256DA-70BEG
M24L416256DA-55TEG
M24L416256DA-60TEG
M24L416256DA-70TEG
M24L416256DA-55BIG
M24L416256DA-60BIG
M24L416256DA-70BIG
M24L416256DA-55TIG
M24L416256DA-60TIG
M24L416256DA-70TIG
Package Type
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
Elite Semiconductor Memory Technology Inc.
Operating Range
Extended
Extended
Extended
Extended
Extended
Extended
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Publication Date: Jul. 2008
Revision: 1.5
11/15
ESMT
M24L416256DA
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
12/15
ESMT
44-LEAD
M24L416256DA
TSOP(II)
PSRAM(400mil)
Symbol Dimension in mm
Min
Norm
A
Dimension in inch
Max
Min
Norm
1.20
Max
0.047
A1
0.05
0.15
0.002
A2
B
0.95
0.30
1.00
1.05
0.45
0.037
0.012
0.039
0.042
0.018
B1
0.30
0.35
0.40
0.012
0.014
0.016
C
C1
D
0.12
0.10
18.28
18.41
0.21
0.16
18.54
0.005
0.004
0.720
0.725
0.008
0.006
0.730
ZD
E
E1
L
0.805
11.56
10.03
0.40
L1
11.76
10.16
0.59
0.0317 REF
11.96
10.29
0.69
0.455
0.395
0.016
0.80 REF
e
θ
REF
0.463
0.400
0.023
0.031
0.80 BSC
0°
0.006
0.471
0.4
0.027
REF
0.0315 BSC
8°
Elite Semiconductor Memory Technology Inc.
0°
8°
Publication Date: Jul. 2008
Revision: 1.5
13/15
ESMT
M24L416256DA
Revision History
Revision
Date
1.0
2007.07.04
1.1
2007.11.20
1.2
2007.11.22
1.3
2008.02.27
1.4
2008.03.24
Add I-grade for TSOPII package
2008.07.04
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade for BGA package
1.5
Elite Semiconductor Memory Technology Inc.
Description
Original
Modify the descriptive error for standby mode, tHZWE and tLZWE
description
Modify tHZBE and tLZBE descriptive and restore tHZWE and tLZWE
description
1.Add 44-pin TSOPII package
2. Add Avoid timing
Publication Date: Jul. 2008
Revision: 1.5
14/15
ESMT
M24L416256DA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any means
without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and reserves
the right to change the products or specification in this document without notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any infringement of
patents, copyrights, or other intellectual property rights of third parties which may result
from its use. No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To minimize risks
associated with customer's application, adequate design and operating safeguards against
injury, damage, or loss from such failure, should be provided by the customer when
making application designs.
ESMT's products are not authorized for use in critical applications such as, but not limited
to, life support devices or system, where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage. If products described here are to
be used for such kinds of application, purchaser must do its own quality assurance testing
appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
15/15