TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 4.5V to 28V Input, 3A Output, Synchronous SWIFT™ Step-Down Voltage Regulator Check for Samples: TPS54335, TPS54336 FEATURES DESCRIPTION • The TPS54335/54336 is a 3A, low quiescent supply current (IQ), synchronous DC-DC converter IC (integrated circuit) with up to 28V input support. 1 2 • • • • • • • • • • Two 128mΩ/84mΩ MOSFETs for 3A Continuous Output Current TPS54335: Internal 2ms Soft-start, 50kHz–1.5MHz Adjustable Frequency TPS54336: Adjustable Soft-start, Fixed 340kHz Frequency Low 2µA Shutdown Quiescent Current 0.8V Internal Voltage Reference with ±0.8% Accuracy at Room Temperature and ±1.5% Accuracy Over Temperature Fixed-Frequency Current Mode Control Pulse Skipping Boosts Efficiency at Light Loads Overcurrent Protection for Both MOSFETs with Hiccup Mode for Severe Fault Conditions Thermal Shutdown and Overvoltage Transition Protection Available in Easy-to-Use 8-Pin SOIC PowerPAD™ and 10-pin SON Monotonic Start-Up into Pre-biased Outputs APPLICATIONS • • • • Consumer Applications such as a Digital TV (DTV), Set Top Box (STB, DVD/Blu-ray Player), LCD Display, CPE (Cable Modem, WiFi Router), DLP Projectors, Smart Meters Battery Chargers Industrial and Car Audio Power Supplies 5V,12V and 24V Distributed Power Bus Supply By integrating MOSFETs and by employing current mode switching control, the TPS54335/54336 offers compact designs on PCB (printed circuit board) reducing external component count. Efficiency is maximized through the integrated 128mΩ/84mΩ MOSFETs, low IQ and pulse skipping at light loads. Using the enable pin, shutdown supply current is reduced to 2 μA by entering a shutdown mode. This step-down (buck) converter provides accurate regulation for a variety of loads with a well-regulated voltage reference 1.5% over temperature. Cycle by cycle current limiting on the high-side MOSFET protects the TPS54335/54336 in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit which turns off the low-side MOSFET to prevent excessive reverse current. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset time. Thermal hiccup protection disables the part when die temperature exceeds thermal shutdown temperature and enables the part again after the built-in thermal hiccup time. . . SIMPLIFIED SCHEMATICS VIN VIN VIN C1 VIN C1 TPS54335 BOOT EN TPS54336 CBOOT PH RT COMP BOOT EN LO CBOOT LO PH VOUT SS COMP CO VOUT CO RO1 RO1 CC CC VSENSE RRT C2 RC GND VSENSE C2 RO2 CSS RC GND RO2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, SWIFT are trademarks of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ (2) PACKAGE PART NUMBER TPS54335DDA 8-Pin SOIC PowerPAD™ TPS54336DDA –40°C to +150°C TPS54335DRC 10-pin SON (1) (2) TPS54336DRC For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54335DDAR). See applications section of data sheet for layout information. ABSOLUTE MAXIMUM RATINGS (1) Input voltage (2) MIN MAX VIN –0.3 30 V EN –0.3 6 V BOOT -0.3 (PH+7.5) V VSENSE –0.3 3 V COMP –0.3 3 V RT –0.3 3 V SS –0.3 3 V 0 7.5 V –1 30 V –3.5 30 V –0.2 0.2 V EN 100 100 µA RT 100 BOOT-PH Output voltage PH PH 10ns Transient Vdiff (GND to exposed Thermal Pad) Source current UNIT 100 µA PH Current Limit A PH Current Limit A 200 200 µA 2 2 kV Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 500 V Operating junction temperature –40 150 °C Storage temperature –65 150 °C Sink current COMP Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A) (1) (2) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 THERMAL INFORMATION TPS54335/6 THERMAL METRIC (1) DDA (8 PINS) DRC (10 PINS) θJA Junction-to-ambient thermal resistance 42.1 43.9 θJCtop Junction-to-case (top) thermal resistance 50.9 55.4 θJB Junction-to-board thermal resistance 31.8 18.9 ψJT Junction-to-top characterization parameter 8 0.7 ψJB Junction-to-board characterization parameter 13.5 19.1 θJCbot Junction-to-case (bottom) thermal resistance 7.1 5.3 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the life of the product containing it. TJ = –40°C to +150°C, VIN =4.5 TO 28V, (unless otherwise noted) PARAMETERS CONDITIONS MIN TYP MAX UNIT 4 4.5 V 180 400 mV SUPPLY VOLTAGE AND UVLO (VIN PIN) Operating input voltage Input UVLO threshold 4.5 Rising Vin Input UVLO hysteresis 28 V VIN Shutdown supply current EN = 0V 2 10 µA VIN Operating – Non switching supply current VSENSE = 810 mV 310 800 µA Enable threshold Rising 1.21 1.28 V Enable threshold Falling 1.17 V Input current EN= 1.1 V 1.15 µA Hysteresis current EN= 1.3 V 3.3 µA ENABLE (EN PIN) 1.1 VOLTAGE REFERENCE Reference TJ =25°C 0.7936 0.8 0.8064 0.788 0.8 0.812 BOOT-PH= 3 V 160 280 mΩ BOOT-PH= 6 V 128 230 mΩ 84 170 mΩ V MOSFET High side switch resistance (1) Low Side Switch Resistance (1) VIN = 12V ERROR AMPLIFIER Error amplifier transconductance (gm) –2 µA < ICOMP < 2 µA V(COMP) = 1 V Error amplifier source/sink V(COMP) = 1 V, 100 mV Overdrive Start switching peak current threshold 1300 µmhos 100 µA 0.5 COMP to Iswitch gm A 8 A/V CURRENT LIMIT High side switch current limit threshold Low side switch sourcing current limit Low side switch sinking current limit 4.9 6.5 A 4.7 6.1 A 0 Hiccup wait time Hiccup time before re-start (1) 4 3.5 A 512 Cycles 16384 Cycles Measured at pins Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 3 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the life of the product containing it. TJ = –40°C to +150°C, VIN =4.5 TO 28V, (unless otherwise noted) PARAMETERS CONDITIONS MIN TYP 160 175 MAX UNIT THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysterisis °C 10 Thermal shutdown hiccup time °C 32768 Cycles PH (PH PIN) Minimum on time Measured at 90% to 90% of VIN, IPH = 2A Minimum off time BOOT-PH ≥ 3V 94 145 0 ns % BOOT (BOOT PIN) BOOT-PH UVLO 2.1 3 V SWITCHING FREQUENCY TPS54335 50 TPS54335, Rrt = 100 kΩ Switching frequency range 384 TPS54335, Rrt = 1000 kΩ, –40°C~105°C TPS54335, Rrt = 30 kΩ Internal switching frequency TPS54336 480 1500 kHz 576 kHz 40 50 60 kHz 1200 1500 1800 kHz 272 340 408 kHz SLOW START Internal slow start time TPS54335 2 ms Slow start charge current TPS54336 2.3 µA PIN ASSIGNMENTS 8-PIN SOIC WITH THERMAL PAD (TOP VIEW) TPS54335 TPS54336 8 SS 7 EN 3 6 COMP 4 5 VSENSE 8 RT BOOT 1 7 EN VIN 2 3 6 COMP PH 4 5 VSENSE GND BOOT 1 VIN 2 PH GND PowerPAD (9) PowerPAD (9) PIN FUNCTIONS PIN NAME DESCRIPTION NUMBER BOOT 1 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. Vin 2 Input supply voltage, 4.5 V to 28 V. PH 3 The source of the internal high side power MOSFET. GND 4 Ground. VSENSE 5 Inverting node of the gm error amplifier. COMP 6 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 7 Enable pin. Float to enable. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 PIN FUNCTIONS (continued) PIN NAME DESCRIPTION NUMBER RT (TPS54335) 8 Connect to an external timing resistor to adjust the switching frequency of the device. SS (TPS54336) 8 Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. PowerPAD™ 9 GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. 10-PIN SON WITH THERMAL PAD (TOP VIEW) TPS54336 TPS54335 DRC PACKAGE (TOP VIEW) IE W DRC PACKAGE (TOP VIEW) VIN 1 GND 3 GND 4 GND 5 Exposed Thermal Pad (11) PR EV PH 2 10 RT VIN 1 10 SS 9 BOOT PH 2 9 BOOT 8 EN GND 3 8 EN 7 COMP GND 4 7 COMP 6 VSENSE GND 5 6 VSENSE Exposed Thermal Pad (11) PIN FUNCTIONS PIN NAME VIN PH GND DESCRIPTION NUMBER 1 Input supply voltage, 4.5 V to 28 V. 2 The source of the internal high side power MOSFET. 3, 4, 5 Ground. VSENSE 6 Inverting node of the gm error amplifier. COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 8 Enable pin. Float to enable. BOOT 9 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. RT (TPS54335) 10 Connect to an external timing resistor to adjust the switching frequency of the device. SS (TPS54336) 10 Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. PowerPAD™ 11 GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 5 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN EN Ip Ih Enable Comparator Thermal Hiccup UVLO Shutdown Logic Enable Threshold Hiccup Shutdown OV Boot Charge Current Sense Minimum Clamp Pulse Skip ERROR AMPLIFIER VSENSE BOOT Boot UVLO SS (TPS54336) HS MOSFET Current Comparator Voltage Reference Power Stage & Deadtime Control Logic PH Slope Compensation VIN Regulator Hiccup Shutdown Overload Recovery Maximum Clamp Oscillator LS MOSFET Current Limit Current Sense GND COMP 6 RT (TPS54335) Submit Documentation Feedback EXPOSED THERMAL PAD Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS HIGH-SIDE MOSFET ON RESISTANCE vs JUNCTION TEMPERATURE LOW-SIDE MOSFET ON RESISTANCE vs JUNCTION TEMPERATURE 140 130 Rdson - On Resistance (mohm) Rdson - On Resistance (mohm) 210 190 170 150 130 110 90 120 110 100 90 80 70 60 VIN = 12 V 70 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (C) ±50 150 0 25 50 75 100 125 TJ - Junction Temperature (C) Figure 1. Figure 2. VOLTAGE REFERENCE vs JUNCTION TEMPERATURE OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 150 C002 495 FSW - Oscillator Frequency (kHz) VREF - Voltage Reference (V) ±25 C001 0.808 0.804 0.800 0.796 0.792 490 485 480 475 470 465 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (C) ±50 150 ±25 0 25 50 75 100 125 TJ - Junction Temperature (C) C003 Figure 3. Figure 4. UVLO THRESHOLD vs JUNCTION TEMPERATURE HYSTERESIS CURRENT vs JUNCTION TEMPERATURE 1.230 150 C004 3.50 IH - Hysterisis Current (uA) EN - UVLO Threshold (V) VIN = 12 V 50 1.225 1.220 1.215 3.45 3.40 3.35 3.30 3.25 VIN = 12 V VIN = 12 V 1.210 3.20 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 ±50 ±25 C005 Figure 5. 0 25 50 75 100 125 TJ - Junction Temperature (C) 150 C006 Figure 6. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 7 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) PULLUP CURRENT vs JUNCTION TEMPERATURE NON-SWITCHING OPERATING QUIESCENT CURRENT vs INPUT VOLTAGE 400 IQ - Non-switching Operating Quiesen Current (uA) IP - Pullup Current (uA) 1.2 1.175 1.15 1.125 350 300 250 TTJ -40C -40 J == TTJ 25C 25 J == TTJ 150C 150 J == VIN = 12 V 200 1.1 ±50 ±25 0 25 50 75 100 125 8 16 20 24 VIN - Input Voltage (V) Figure 8. SHUTDOWN QUIESCENT CURRENT vs INPUT VOLTAGE SS CHARGE CURRENT vs JUNCTION TEMPERATURE 10 2.40 ISS - SS Charge Current (uA) -40 TTJ -40C J == TTJ 25C 25 J == TTJ 150C 150 J == 8 28 C008 Figure 7. 6 4 2 2.35 2.30 2.25 EN = 0 V 0 2.20 4 8 12 16 20 24 VIN - Input Voltage (V) ±25 0 25 50 75 100 125 TJ - Junction Temperature (C) Figure 10. MINIMUM CONTROLLABLE ON TIME vs JUNCTION TEMPERATURE MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE 110 100 90 80 VIN = 12 V 70 ±25 0 25 50 75 100 125 150 150 C010 Figure 9. 120 ±50 ±50 28 C009 TJ - Junction Temperature (C) 6.0 5.0 4.0 VIN = 12 V 3.0 ±50 ±25 C011 Figure 11. 8 12 C007 Dmin - Minimum Controllable Duty Ratio (%) ISD - Shutdown Quiescent Current (uA) TJ - Junction Temperature (C) Tonmin - Minimum Controllable On Time (ns) 4 150 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 C012 Figure 12. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS (continued) CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE 6.0 2.300 ICL - Current Limit Threshold (A) VBOOT - BOOT-PH UVLO Threshhold (uA) BOOT-PH UVLO THRESHOLD vs JUNCTION TEMPERATURE 2.200 2.100 2.000 = -40 TJTJ = -40C TJTJ = 25C = 25 TJTJ = 150C = 150 5.5 5.0 4.5 4.0 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (C) 125 150 4 8 C013 Figure 13. 12 16 20 24 VIN - Input Voltage (V) 28 C014 Figure 14. OVERVIEW The device is a 28-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. The device has been designed for safe monotonic startup into pre-biased loads. It has a typical default start up voltage of 4.0 V. The EN pin has an internal pull-up current source that can provide a default condition when the EN pin is floating for the device to operate. The total operating current for the device is typically 310µA when not switching and under no load. When the device is disabled, the supply current is less than 5μA. The integrated 128mΩ/84mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents up to 3 amperes. The device reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. The output voltage can be stepped down to as low as the 0.8 V reference. The device minimizes excessive output over-voltage transients by taking advantage of the over-voltage power good comparator. When the regulated output voltage is greater than 106% of the nominal voltage, the overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 104%. The TPS54335 has wide switching frequency of 50 kHz to 1500 kHz which allows for efficiency and size optimization when selecting the output filter components. The internal 2ms slow start time is implemented to minimize inrush currents. The TPS54336 is fixed at 340kHz. It is able to adjust the slow start time by the SS pin. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 9 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The device uses a fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response performance. LIGHT LOAD OPERATION The device monitors the peak switch current of the high-side MOSFET. Once the peak switch current is lower than typically 0.5A, the device stops switching to boost the efficiency until the peak switch current again rises higher than typically 0.5A. VOLTAGE REFERENCE The voltage reference system produces a precise ±1.5% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a 10 kΩ for the upper resistor divider, R1 and useEquation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. VREF R2 = ´ R1 VOUT - VREF (1) ENABLE AND ADJUSTING UNDERVOLTAGE LOCKOUT The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 180mV. If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown in Figure 15. When using the external UVLO function it is recommended to set the hysteresis to be greater than 500mV. The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2, and Equation 3. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 TPS54335/6 VIN ip ih R1 R2 EN Figure 15. Adjustable VIN Undervoltage Lock Out æV ö VSTART ç ENFALLING ÷ - VSTOP è VENRISING ø R1 = æ V ö Ip ç1 - ENFALLING ÷ + Ih VENRISING ø è R2 = VSTOP (2) R1´ VENFALLING - VENFALLING + R1(Ip + Ih ) (3) Where Ih = 3.3 μA, Ip = 1.15 μA, VENRISING = 1.21 V, VENFALLING = 1.17 V ERROR AMPLIFIER The device has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of the internal slow start voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is 1300μA/V typically. The frequency compensation components are placed between the COMP pin and ground. SLOPE COMPENSATION AND OUTPUT CURRENT The device adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full duty cycle range. SAFE START-UP INTO PRE-BIASED OUTPUTS The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the internal slow-start voltage (TPS54335), or SS pin voltage (TPS54336) is higher than VSENSE pin voltage. BOOTSTRAP VOLTAGE (BOOT) The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold, which is typically 2.1V, the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. ADJUSTABLE SWITCHING FREQUENCY (TPS54335 ONLY) To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 16. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. Rrt(kW) = 55300 ´ Fsw(kHz)-1.025 (4) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 11 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com RT SET RESISTOR vs OSCILLATOR FREQUENCY Rrt - Resistance - kohm 1000 800 600 400 200 0 0 250 500 750 1000 1250 Fsw - Oscillator Frequency - kHz 1500 Figure 16. RT Set Resistor vs Switching Frequency SLOW START (TPS54336 ONLY) The device uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS pin to ground implements a slow start time. The device has an internal pull-up current source of 2.3 μA that charges the external slow start capacitor. The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 5. The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3μA. Css(nF) ´ Vref(V) Tss(ms) = Iss(m A) (5) When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the device stops switching and enters low current operation. At the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS pin to ground ensuring proper soft start behavior. OUTPUT OVERVOLTAGE PROTECTION (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. OVERCURRENT PROTECTION The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. High-side MOSFET overcurrent protection The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 Low-side MOSFET overcurrent protection While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current limit is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. THERMAL SHUTDOWN The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time (32768 cycles) is over. SMALL SIGNAL MODEL FOR LOOP RESPONSE Figure 17 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Roea (3.07 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. PH VOUT Power Stage 8 A/V a b c 0.8 V R3 Coea C2 R1 RESR VSENSE CO COMP C1 Roea gm 1300 mA/V RL R2 Figure 17. Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 18 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 6 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 17) is the power stage transconductance (gmps) which is 8 A/V for the device. The DC gain of the power stage is the product of gmps Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 13 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com and the load resistance, R L, as shown in Equation 7 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 8). The combined effect is highlighted by the dashed line in Figure 19. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. VOUT VC RESR RL gm ps CO Figure 18. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR fp RL gm ps CO fz Figure 19. Simplified Frequency Response for Peak Current Mode Control æ ç1+ 2p VOUT = Adc ´ è VC æ ç1+ è 2p ö s ÷ ´ ¦z ø ö s ÷ ´ ¦p ø (6) Adc = gmps ´ RL (7) 1 ¦p = C O ´ R L ´ 2p (8) ¦z = 1 CO ´ RESR ´ 2p (9) Where gmea is the GM amplifier gain (1300μA/V) gmps is the power stage gain (8 A/V). RL is the load resistance CO is the output capacitance. RESR is the equivalent series resistance of the output capacitor. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 20. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III compensation. The design guidelines below are provided for advanced users who prefer to compensate using the general method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. VOUT C11 R8 Type 3 VSENSE COMP Type 2A Vref R9 gm ea Roea R4 Coea C6 Type 2B R4 C4 C4 Figure 20. Types of Frequency Compensation The general design guidelines for device loop compensation are as follows: 1. Determine the crossover frequency, fc. A good starting point is 1/10th of the switching frequency, fsw. 2. R4 can be determined by: 2p ´ ¦ c ´ VOUT ´ Co R4 = gmea ´ Vref ´ gmps (10) Where: gmea is the GM amplifier gain (1300 μA/V) gmps is the power stage gain (8 A/V) Vref is the reference voltage (0.8 V) æ ö 1 ç ¦p = ÷ CO ´ RL ´ 2p ø 3. Place a compensation zero at the dominant pole: è C4 can be determined by: R ´ Co C4 = L R4 (11) 4. C6 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output capacitor Co. ´ Co R C6 = ESR R4 (12) 5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 13. 1 C11 = (2 × p × R8 × fc ) (13) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 15 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com APPLICATION INFORMATION TPS54335 APPLICATION SCHEMATIC U1 TPS54335DDA VIN = 8 - 28 V 2 VIN C1 10µF C2 0.1µF VSENSE 5 7 R1 220k 8 VIN VSENSE BOOT PH EN COMP RT GND PAD L1 15µH VOUT = 5 V, 3 A max C3 0.1µF 1 VOUT 3 C6 47µF 6 C7 47µF R4 51.1 4 R3 3.74k R5 100k C5 120pF R2 43.2k R7 143k VSENSE C4 0.012µF R6 19.1k Figure 21. Typical Application Schematic, TPS54335 STEP BY STEP DESIGN PROCEDURE The following design procedure can be used to select component values for the TPS54335 and TPS54336. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process using the TPS54335. To • • • • • • begin the design process a few parameters must be decided upon. The designer needs to know the following: Input voltage range Output voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency For this design example, use the following as the input parameters Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 8 V to 28V Output voltage 5V Transient response, 1.5 A load step ΔVout = +/- 5 % Input ripple voltage 400 mV Output ripple voltage 30 mV Output current rating 3A Operating Frequency 340 kHz SWITCHING FREQUENCY The switching frequency of the TPS54335 is set at 340 kHz to match the internally set frequency of the TPS54336 for this design. Use Equation 4 to calculate the required value for R7. The calculated value is 140.6 kΩ. Use the next higher standard value of 143 kΩ. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 OUTPUT VOLTAGE SET POINT The output voltage of the TPS54335 is externally adjustable using a resistor divider network. In the application circuit of Figure 21, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 14 and Equation 15: R5 ´ VREF R6 = VOUT - VREF (14) é R5 ù VOUT = VREF ´ ê +1ú ë R6 û (15) Choose R5 to be approximately 100 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage matching when using standard value resistors. In this design, R5 = 100 kΩ and R6 = 19.1 kΩ, resulting in a 4.988 V output voltage. The 51.1 ohm resistor R4 is provided as a convenient place to break the control loop for stability testing. Under Voltage Lockout Set Point The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is connected between VIN and the EN pin of the TPS54335 and R2 is connected between EN and GND . The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the start voltage threshold is set to 7.15 V with 1 V hysteresis. Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values of R1 and R2. INPUT CAPACITORS The TPS54335 requires an input decoupling capacitor and depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54335 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design, a 10 μF, X7R dielectric capacitor rated for 35 V is used for the input decoupling capacitor. . The equivalent series resistance (ESR) is approximately 2mΩ, and the current rating is 3 A. Additionally, a small 0.1 μF capacitor is included for high frequency filtering. This input ripple voltage can be approximated by Equation 16 IOUT(MAX) ´ 0.25 DVIN = + IOUT(MAX) ´ ESRMAX CBULK ´ fSW ( ) (16) Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value and ESRMAX is the maximum series resistance of the bulk capacitor. The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximated by Equation 17 IOUT(MAX) ICIN = 2 (17) In this case, the input ripple voltage would be 227 mV and the RMS ripple current would be 1.5 A. It is also important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in Design Parameters and is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen bypass capacitor is rated for 35 V and the ripple current capacity is greater than 3 A, both providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded under any circumstance. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 17 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com OUTPUT FILTER COMPONENTS Two components need to be selected for the output filter, LOUT and COUT. Since the TPS54335 is an externally compensated device, a wide range of filter component types and values can be supported. Inductor Selection To calculate the minimum value of the output inductor, use Equation 18 LMIN = VOUT ´ (VIN(MAX) - VOUT ) VIN(MAX) ´ KIND ´ IOUT ´ FSW (18) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher ESR output capacitors, KIND = 0.2 yields better results. For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 13.4 μH. For this design, a close standard value was chosen: 15 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 19 IL(RMS) = ( ) æ V ö OUT ´ VIN(MAX) - VOUT 1 ÷ + ´ ç ç VIN(MAX) ´ LOUT ´ FSW ´ 0.8 ÷ 12 è ø 2 IOUT(MAX) 2 (19) and the peak inductor current can be determined with Equation 20 IL(PK) = IOUT(MAX) + VOUT ´ (VIN(MAX) - VOUT ) 1.6 ´ VIN(MAX) ´ LOUT ´ FSW (20) For this design, the RMS inductor current is 3.002 A and the peak inductor current is 3.503 A. The chosen inductor is a Coilcraft 15 μH, XAL6060-153MEB. It has a saturation current rating of 5.8 A and an RMS current rating of 6.0 A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wishes to allow so long as the other design requirements are met. Larger value inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values will increase ac current and output voltage ripple. In general, inductor values for use with the TPS54335 are in the range of 0.68 μH to 100 μH. Capacitor Selection There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of drop in the output voltage. Equation 21 shows the minimum output capacitance necessary to accomplish this. 2 × DIout Co > f sw × DVout (21) 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 5% change in Vout for a load step of 1.5 A. For this example, ΔIout = 1.5 A and ΔVout = 0.05 x 5.0 = 0.250 V. Using these numbers gives a minimum capacitance of 35.3 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement Equation 22, yields 12.3 µF. 1 1 Co > × 8 × f sw Voripple Iripple (22) Equation 23 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 23 indicates the ESR should be less than 29.8 mΩ. In this case, the ceramic caps’ ESR is much smaller than 29.8 mΩ. Voripple Resr < Iripple (23) Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 47 μF 10V X5R ceramic capacitor with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 24 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 24 yields 116.2 mA for each capacitor. æ VOUT × VIN(MAX) - VOUT ö 1 ÷ ICOUT(RMS) = × ç ç VIN(MAX) × LOUT × FSW × NC ÷ 12 è ø (24) ( ) COMPENSATION COMPONENTS There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal current mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole shown in Equation 25 ¦ p m od = Iout m ax 2 p ´ Vout ´ Cout (25) For the TPS54335 most circuits will have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple approximations. It is best to use Pspice to accurately model the power stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can be used. That is the technique used in this design procedure. For this design, L1 = 15 µH. C6 and C7 are set to 47µF each, and the ESR is 3 mΩ. Now the power stage characteristics are shown in Figure 22. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 19 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com 180 Gain 40 Gain = 2.23 dB @ F = 31.62 kHz 120 60 0 0 Gain - dB 20 -20 -60 Phase -40 Phase - Degrees 60 -120 -60 10 100 1000 10000 Frequency - Hz -180 100000 C020 Figure 22. Power Stage Gain and Phase Characteristics For this design, the intended crossover frequency is 31.62 kHz (there is an actual measured data point for that frequency). From the power stage gain and phase plots, the gain at 31.62 kHz is 2.23 dB and the phase is about -106 degrees. For 60 degrees of phase margin, additional phase boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider is not needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. The required value of R3 can be calculated from Equation 26 . R3 = 10 -GPWRSTG 20 gmEA × VOUT VREF (26) To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 31.62 kHz. The required value for C4 is given by Equation 27. 1 C4 = F 2 × p × R3 × CO 10 (27) To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 31.62 kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. The value for C5 can be calculated from Equation 28. 1 C5 = 2 × p × R3 × 10 × FCO (28) For this design the calculated values for the compensation components are R3 = 3.74 kΩ ,C4 = 0.012 µF and C5 = 120 pF. BOOTSTRAP CAPACITOR Every TPS54335 design requires a bootstrap capacitor, C3. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a highquality ceramic type with X7R or X5R grade dielectric for temperature stability. POWER DISSIPATION ESTIMATE The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse skipping Eco-modeTM. The device power dissipation includes: 1) Conduction loss: Pcon = Iout2 x RDS(on) x VOUT/VIN 2) Switching loss: Psw = 0.5 x 10-9 x VIN 2 x IOUT x Fsw 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 3) Gate charge loss: Pgc = 22.8 x 10-9 x Fsw 4) Quiescent current loss: Pq = 0.11 x 10-3 x VIN Where: IOUT is the output current (A). RDS(on) is the on-resistance of the high-side MOSFET (Ω). VOUT is the output voltage (V). VIN is the input voltage (V). Fsw is the switching frequency (Hz). So Ptot = Pcon + Psw + Pgc + Pq For given TA , TJ = TA + Rth x Ptot. For given TJMAX = 150°C, TAMAX = TJMAX– Rth x Ptot. Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C) . Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C). PCB LAYOUT The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connection. the VIN pin, and the GND pin of the IC. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN and GND pins of the device. See Figure 23 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. To facilitate close placement of the input bypass capacitors, The PH pin should be routed to a small copper area directly adjacent to the pin. Use vias to rout the PH signal to the bottom side or an inner layer. If necessary you can allow the top side copper area to extend slightly under the body of the closest input bypass capacitor. Make the copper trace on the bottom or internal layer short and wide as practical to reduce EMI issues. Connect the trace with vias back to the top side to connect with the output inductor as shown after the GND pin. In the same way use a bottom or internal layer trace to rout the PH signal across the VIN pin to connect to the BOOT capacitor as shown. Make the circulating loop from PH to the output inductor, output capacitors and back to GND as tight as possible while preserving adequate etch width to reduce conduction losses in the copper . For operation at full rated load, the ground area near the IC must provide adequate heat dissipating area. Connect the exposed thermal pad to bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top side copper to the internal or bottom layer copper. The additional external components can be placed approximately as shown. Use a separate ground trace to connect the feed back, compensation, UVLO and RT (SS for TPS54336) returns. Connect this ground trace to the main power ground at a single point to minimize circulating currents. It may be possible to obtain acceptable performance with alternate layout schemes, however this layout has been shown to produce good results and is intended as a guideline. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 21 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com VIA to Power Ground Plane VIA to SW Copper Pour on Bottom or Internal Layer VIN VIN INPUT BYPASS CAPACITOR Connect to VIN on internal or bottom layer VIN HIGH FREQUENCY BOOT BYPASS CAPACITOR CAPACITOR ANALOG GROUND TRACE FREQUENCY SET RESISTOR BOOT RT VIN EN PH COMP GND VSENSE UVLO RESISTORS COMPENSATION NETWORK EXPOSED THERMAL PAD AREA POWER GROUND FEEDBACK RESISTORS OUTPUT INDUCTOR SW node copper pour area on internal or bottom layer POWER GROUND VOUT Note: Pin 8 for TPS54336 is SS. Connect SS capacitor instead of RT resistor from pin 8 to GND. OUTPUT FILTER CAPACITOR Figure 23. TPS54335DDA Board Layout 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 TPS54335 APPLICATION CURVES spacer 100 100 90 90 80 80 VIN = 12 V VIN = 24 V 70 Efficiency - % Efficiency - % 70 60 50 40 50 30 20 20 10 10 0.0 0.5 1.0 1.5 2.0 2.5 Output Current - A VIN = 12 V 40 30 0 VIN = 24 V 60 0 0.001 3.0 0.01 0.1 Figure 24. TPS54335 Efficiency 1 10 Output Current - A C015 C016 Figure 25. TPS54335 Low Current Efficiency spacer 0.5 0.10 0.4 0.08 0.3 0.06 0.2 Line Regulation - % Load Regulation - % spacer VIN = 12 V 0.1 0.0 ±0.1 ±0.2 ±0.3 IOUT = 1.5 A 0.04 0.02 0.00 ±0.02 ±0.04 ±0.06 VIN = 24 V ±0.4 ±0.08 ±0.5 ±0.10 0.0 0.5 1.0 1.5 2.0 2.5 Output Current - A 3.0 8 10 Figure 26. TPS54335 Load Regulation 12 14 16 18 20 22 24 26 Input Voltage - V C017 28 C018 Figure 27. TPS54335 Line Regulation spacer spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 23 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com 60 180 Gain - dB 20 60 0 0 Gain -20 IOUT = 1 A/div 120 Phase -60 -40 0.75 A to 2.25 A load step, slew rate = 500 mA / µsec Phase - Degrees 40 VOUT = 200 mV/div (ac coupled) -120 -60 10 100 1000 10000 100000 -180 1000000 Frequency - Hz C019 Time = 200 µs/div Figure 28. TPS54335 Transient Response Figure 29. TPS54335 Loop Response spacer spacer VOUT = 20 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled) PH = 10 V/div PH = 10 V/div Time = 2 µs/div Time = 2 µs/div Figure 30. TPS54335 Full Load Output Ripple Figure 31. TPS54335 100 mA Output Ripple spacer spacer VIN = 200 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled) PH = 10 V/div PH = 10 V/div Time = 100 µs/div Time = 2 µs/div Figure 32. TPS54335 No Load Output Ripple Figure 33. TPS54335 Full Load Input Ripple spacer 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 spacer VIN = 10 V/div VIN = 10 V/div EN = 2 V/div EN = 2 V/div VOUT = 2 V/div VOUT = 2 V/div Time = 2 ms/div Time = 2 ms/div Figure 34. TPS54335 Start Up Relative to VIN Figure 35. TPS54335 Start-up Relative to Enable spacer spacer VIN = 10 V/div VIN = 10 V/div EN = 2 V/div EN = 2 V/div VOUT = 2 V/div VOUT = 2 V/div Time = 2 ms/div Time = 2 ms/div Figure 36. TPS54335 Shut Down Relative to VIN Figure 37. TPS54335 Shut Down Relative to EN TPS54336 APPLICATION SCHEMATIC U1 TPS54336DDA VIN = 8 - 28 V 2 VIN C1 10µF C2 0.1µF VSENSE 5 7 R1 220k 8 VIN VSENSE BOOT PH EN COMP SS GND PAD L1 15µH VOUT = 5 V, 3 A max C3 0.1µF 1 VOUT 3 C6 47µF 6 C7 47µF R4 51.1 4 R3 3.74k R5 100k C5 120pF R2 43.2k C8 0.01µF VSENSE C4 0.012µF R6 19.1k Figure 38. Typical Application Schematic, TPS54336 TPS54336 DESIGN The design procedure for the TPS54336 is identical to the TPS54335, except the TPS54336 utilizes a slow start circuit rather than an externally set switching frequency at pin 8. The switching frequency is internally set for 340 kHz. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 25 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54336 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be calculated using Equation 5. For the example circuit, the soft start time is not too critical since the output capacitor value is 2 x 47 μF which does not require much current to charge to 5 V. The example circuit has the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF capacitor. In TPS54336, Iss is 2.3 µA and Vref is 0.8V. TPS54336 APPLICATION CURVES spacer 100 100 90 90 80 80 VIN = 12 V 70 VIN = 24 V Efficiency - % Efficiency - % 70 60 50 40 50 30 20 20 10 10 0.0 0.5 1.0 1.5 2.0 2.5 Output Current - A VIN = 12 V 40 30 0 VIN = 24 V 60 0 0.001 3.0 0.01 0.1 Figure 39. TPS54336 Efficiency 1 10 Output Current - A C021 C022 Figure 40. TPS54336 Low Current Efficiency spacer 0.5 0.5 0.4 0.4 VIN = 24 V 0.3 Load Regulation - % Load Regulation - % 0.3 0.2 VIN = 12 V 0.1 0.0 ±0.1 ±0.2 0.2 0.1 0 -0.1 Vin=12V -0.2 ±0.3 Vin=24V -0.3 ±0.4 -0.4 ±0.5 0.0 0.5 1.0 1.5 2.0 2.5 Output Current - A 3.0 C023 -0.5 0 0.5 1 1.5 2 2.5 3 Output Current - A Figure 41. TPS54336 DDA Load Regulation Figure 42. TPS54336 DRC Load Regulation spacer 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 0.10 0.1 0.08 0.08 IOUT = 1.5 A 0.06 0.04 Line Regulation - % Line Regulation - % 0.06 0.02 0.00 ±0.02 ±0.04 0.04 0.02 0 16 -0.02 -0.04 ±0.06 Iout=1.5A -0.06 ±0.08 -0.08 ±0.10 8 12 16 20 24 Input Voltage - V 28 -0.1 8 C024 Figure 43. TPS54336 DDA Line Regulation 10 12 14 16 20 18 Input Voltage - V 22 24 26 28 Figure 44. TPS54336 DRC Line Regulation spacer spacer 60 180 Gain - dB 20 60 0 0 Gain -20 IOUT = 1 A/div 120 Phase -60 -40 0.75 A to 2.25 A load step, slew rate = 500 mA / µsec Phase - Degrees 40 VOUT = 200 mV/div (ac coupled) -120 -60 10 100 1000 10000 100000 -180 1000000 Frequency - Hz C025 Time = 200 µs/div Figure 45. TPS54336 Transient Response Figure 46. TPS54336 Loop Response spacer spacer VOUT = 20 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled) PH = 10 V/div PH = 10 V/div Time = 2 µs/div Time = 2 µs/div Figure 47. TPS54336 Full Load Output Ripple Figure 48. TPS54336 100 mA Output Ripple spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 27 TPS54335 TPS54336 SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 www.ti.com spacer VIN = 200 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled) PH = 10 V/div PH = 10 V/div Time = 100 µs/div Time = 2 µs/div Figure 49. TPS54336 No Load Output Ripple Figure 50. TPS54336 Full Load Input Ripple spacer spacer VIN = 20 V/div VIN = 20 V/div EN = 5 V/div EN = 5 V/div SS = 2 V/div SS = 2 V/div VOUT = 2 V/div VOUT = 2 V/div Time = 2 ms/div Time = 2 ms/div Figure 51. TPS54336 Start Up Relative to VIN Figure 52. TPS54336 Start-up Relative to Enable spacer spacer 28 VIN = 20 V/div VIN = 20 V/div EN = 5 V/div EN = 5 V/div SS = 2 V/div SS = 2 V/div VOUT = 2 V/div VOUT = 2 V/div Time = 2 ms/div Time = 2 ms/div Figure 53. TPS54336 Shut Down Relative to VIN Figure 54. TPS54336 Shut Down Relative to EN Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 TPS54335 TPS54336 www.ti.com SLVSC03B – MAY 2013 – REVISED NOVEMBER 2013 REVISION HISTORY NOTE: Previous versions may have different page numbers than current version. Changes from Original (May 2013) to Revision A Page • Changed title from "....Step Down SWIFT™ Converter" to "....SWIFT™ Step-Down Voltage Regulator" and changed product status from "Production Data" to "Product Mix" ....................................................................................................... 1 • Changed Feature bullet from "Thermal and Overvoltage Transient Protection" to "Thermal Shutdown and Overvoltage Transition Protection" ....................................................................................................................................... 1 • Added text "...and 10-pin SON" to Feature bullet ................................................................................................................. 1 • Changed Applications bullet from "...such as DTV, Set Top Boxes, LCD displays, CPE Equipment" to "....such as a Digital TV (DTV), Set Top Box (STB, DVD/Blu-ray Player), LCD Display, CPE (Cable Modem, WiFi Router), DLP Projectors, Smart Meters" ..................................................................................................................................................... 1 • Changed Applications bullet from "...Distributed Power Systems" to "...Distributed Power Bus Supply .............................. 1 • Changed Description section for clarification. ....................................................................................................................... 1 • Changed Simplified Schematic images for readability ......................................................................................................... 1 • Added DRC package option to Ordering Information table. ................................................................................................. 2 • Added DRC package to Thermal Information table .............................................................................................................. 3 • Changed Reference voltage MIN spec from "0.792" to "0.7936" and MAX from "0.808" to "0.8064" for TJ =25°C condition ................................................................................................................................................................................ 3 • Deleted "Error amplifier dc gain" spec from Electrical Characteristics table ........................................................................ 3 • Added SON (DRC) pin assignment drawings and pin descriptions ..................................................................................... 5 • Added TPS54336 DRC Load and Line Regulation characteristics graphs ........................................................................ 26 Changes from Revision A (July 2013) to Revision B • Page Corrected Equation 26. ....................................................................................................................................................... 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54335 TPS54336 29 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS54335DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 54335 TPS54335DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 54335 TPS54336DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 54336 TPS54336DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 54336 TPS54336DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 54336 TPS54336DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 54336 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54335DDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 TPS54336DDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 TPS54336DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54336DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54335DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 TPS54336DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 TPS54336DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS54336DRCT SON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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