TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 2.95 V to 6 V Input, 4 A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™) FEATURES 1 • 2 • • • • • • • • • • Two 30 mΩ (typical) MOSFETs for high efficiency at 4 A loads 200kHz to 2MHz Switching Frequency 0.8 V ± 1% Voltage Reference Over Temperature Synchronizes to External Clock Adjustable Slow Start/Sequencing UV and OV Power Good Output Low Operating and Shutdown Quiescent Current Safe Start-up into Pre-Biased Output Cycle by Cycle Current Limit, Thermal and Frequency Fold Back Protection –40°C to 150°C Operating Junction Temperature Range Thermally Enhanced 3mm × 3mm 16-pin QFN APPLICATIONS • • • Low-Voltage, High-Density Power Systems Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure SIMPLIFIED SCHEMATIC VIN R4 TPS54418 EN The TPS54418 enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2 MHz switching frequency, and minimizing the IC footprint with a small 3mm x 3mm thermally enhanced QFN package. The TPS54418 provides accurate regulation for a variety of loads with an accurate ±1% Voltage Reference (VREF) over temperature. Efficiency is maximized through the integrated 30mΩ MOSFETs and 350mA typical supply current. Using the enable pin, shutdown supply current is reduced to 2 mA by entering a shutdown mode. Under voltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the slow start pin. An open drain power good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency fold back and thermal shutdown protects the device during an overcurrent condition. For more SWIFTTM documentation, see the TI website at www.ti.com/swift. BOOT CI The TPS54418 device is a full featured 6 V, 4 A, synchronous step down current mode converter with two integrated MOSFETs. The TPS54418 is supported in the SwitcherProTM Software Tool at www.ti.com/switcherpro. CBOOT VIN DESCRIPTION LO VOUT PH 100 CO R5 95 R1 PWRGD 90 SS RT /CLK COMP GND AGND POWERPAD C ss RT R3 C1 R2 Efficiency - % 85 VSENSE 80 75 70 VIN = 5 V, VO = 1.8 V, fsw = 500 kHz 65 60 55 50 0 0.5 1 1.5 2 2.5 Load Current - A 3 3.5 4 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TJ PACKAGE PART NUMBER –40°C to 150°C 3 × 3 mm QFN TPS54418RTE ABSOLUTE MAXIMUM RATINGS Input voltage VALUE UNIT VIN –0.3 to 7 V EN –0.3 to 7 BOOT PH + 8 VSENSE –0.3 to 3 COMP –0.3 to 3 PWRGD Output voltage –0.3 to 7pau SS –0.3 to 3 RT/CLK –0.3 to 6 BOOT-PH 8 PH PH 10 ns Transient Source current Sink current V –0.6 to 7 –2 to 7 EN 100 mA RT/CLK 100 mA COMP 100 mA PWRGD 10 mA SS 100 mA 2 kV Electrostatic discharge (HBM) Electrostatic discharge (CDM) 500 V Operating Junction temperature, Tj –40 to 150 °C Storage temperature, Tstg –65 to 150 °C PACKAGE DISSIPATION RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) (1) (2) (3) 2 PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT fJT THERMAL CHARACTERISTIC JUNCTION TO TOP RTE 37°C/W 1°C/W Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. Test boards conditions: (a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 thermal vias (10mil) located under the device package Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 6 V 2.6 2.8 V SUPPLY VOLTAGE (VIN PIN) Operating input voltage 2.95 Internal under voltage lockout threshold No voltage hysteresis, rising and falling Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V Quiescent Current - Iq VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ 2 5 mA 350 500 mA 1.25 1.37 V ENABLE AND UVLO (EN PIN) Enable threshold Input current Rising 1.16 Falling 1.18 Enable threshold + 50 mV -3.2 Enable threshold – 50 mV -0.65 mA VOLTAGE REFERENCE (VSENSE PIN) Voltage Reference 2.95 V ≤ VIN ≤ 6 V, –40°C <TJ < 150°C 0.795 0.803 0.811 BOOT-PH= 5 V 30 60 BOOT-PH= 2.95 V 44 70 VIN= 5 V 30 60 VIN= 2.95 V 44 70 V MOSFET High side switch resistance Low side switch resistance mΩ mΩ ERROR AMPLIFIER Input current 7 nA Error amplifier transconductance (gm) –2 mA < I(COMP) < 2 mA, V(COMP) = 1 V 225 mmhos Error amplifier transconductance (gm) during slow start –2 mA < I(COMP) < 2 mA, V(COMP) = 1 V, Vsense = 0.4 V 70 mmhos Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±20 mA 13.0 A/V 6.4 A 175 °C 15 °C COMP to Iswitch gm CURRENT LIMIT Current limit threshold 5.0 THERMAL SHUTDOWN Thermal Shutdown Hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency range using RT mode Switching frequency 200 Rt = 400 kΩ 400 Switching frequency range using CLK mode 300 Minimum CLK pulse width RT/CLK voltage 500 2000 kHz 600 kHz 2000 kHz 75 R(RT/CLK)= 400kΩ ns 0.5 RT/CLK high threshold 1.6 RT/CLK low threshold 0.4 V 2.2 V 0.6 V RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns PLL lock in time Measure at 500 kHz 14 ms 60 ns PH (PH PIN) Minimum On time Measured at 50% points on PH, IOUT = 4 A Measured at 50% points on PH, VIN = 5 V, IOUT = 0 A 110 Minimum Off time Prior to skipping off pulses, BOOT-PH = 2.95 V, IOUT = 4 A 60 ns Rise/Fall Time VIN = 5 V 1.5 V/ns Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 3 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT BOOT (BOOT PIN) BOOT Charge Resistance VIN = 5 V 16 Ω BOOT-PH UVLO VIN = 2.95 V 2.1 V Charge Current V(SS) = 0.4 V 1.8 mA SS to reference crossover 98% nominal 0.9 V SS discharge voltage (overload) VSENSE = 0 V 20 mA SS discharge current (UVLO, EN, Thermal Fault) VIN = 5 V, V(SS) = 0.5 V 1.25 mA SLOW START (SS PIN) POWER GOOD (PWRGD PIN) VSENSE falling (Fault) VSENSE threshold 91 % Vref VSENSE rising (Good) 93 % Vref VSENSE rising (Fault) 107 % Vref VSENSE falling (Good) 105 % Vref Hysteresis VSENSE falling 2 % Vref Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 2 nA 100 Ω On resistance Output low I(PWRGD) = 3.5 mA 0.3 Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 mA 1.2 4 Submit Documentation Feedback V 1.6 V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 DEVICE INFORMATION PIN CONFIGURATION 2 GND 3 GND 4 EN PWRGD BOOT 14 13 Thermal Pad (17) AGND 5 6 7 8 RT/CLK VIN 15 COMP 1 16 VSENSE VIN VIN QFN16 RTE PACKAGE (TOP VIEW) 12 PH 11 PH 10 PH 9 SS PIN FUNCTIONS PIN DESCRIPTION NAME NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 15 Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. GND 3, 4 Power Ground. This pin should be electrically connected directly to the power pad under the IC. PH 10, 11, 12 The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier MOSFET. PowerPAD 17 GND pin should be connected to the exposed power pad for proper operation. This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. PWRGD 14 An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-voltage or EN shut down. RT/CLK 8 Resistor Timing or External Clock input pin. SS 9 Slow-start. An external capacitor connected to this pin sets the output voltage rise time. VIN 1, 2, 16 VSENSE 6 Input supply voltage, 2.95 V to 6 V. Inverting node of the transconductance (gm) error amplifier. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 5 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM EN PWRGD VIN 93% ihys i1 Shutdown Thermal Shutdown Enable Comparator Logic UVLO Shutdown Shutdown Logic 107% Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum COMP Clamp ERROR AMPLIFIER Current Sense PWM Comparator VSENSE BOOT SS Logic and PWM Latch Shutdown Logic Slope Compensation S COMP PH Frequency Shift Overload Recovery Maximum Clamp Oscillator with PLL GND TPS54418RTE Block Diagram AGND RT/CLK POWERPAD TYPICAL CHARACTERISTICS CURVES FREQUENCY vs TEMPERATURE 550 0.055 High Side Rdson VI = 3.3 V Low Side Rdson VI = 3.3 V 0.05 0.045 540 fs - Switching Frequency - kHz RDSON - Static Drain-Source On-State Resistance - W HIGH SIDE AND LOW SIDE Rdson vs TEMPERATURE High Side Rdson VI = 5 V 0.04 0.035 Low Side Rdson VI = 5 V 0.03 RT = 400 kW, VI = 3.3 V 530 520 510 500 490 480 470 0.025 460 0.02 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 450 -50 -25 Figure 1. 6 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 2. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 TYPICAL CHARACTERISTICS CURVES (continued) HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE 7 6.9 0.808 VIN = 3 .3 V VIN = 3 V 0.806 Vref - Voltage Reference - V High Side Switch Current - A 6.8 6.7 6.6 6.5 6.4 6.3 6.2 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0.798 0.796 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 Figure 3. Figure 4. SWITCHING FREQUENCY vs RT RESISTANCE LOW FREQUENCY RANGE SWITCHING FREQUENCY vs RT RESISTANCE HIGH FREQUENCY RANGE 150 2000 1900 fs - Switching Frequency - KHz 900 fs - Switching Frequncy - KHz 0.8 0.792 -50 150 1000 800 700 600 500 400 1800 1700 1600 1500 1400 1300 1200 300 1100 200 100 1000 80 200 300 400 500 600 700 RT - Resistance - kW 800 900 1000 100 120 140 160 RT - Resistance kW 180 Figure 5. Figure 6. SWITHING FREQUENCY vs VSENSE TRANSCONDUCTANCE vs TEMPERATURE 100 200 280 VIN = 3 .3 V Vsense Falling 260 EA - Transconductance - mA/V Normal Switching Frequency - % 0.802 0.794 6.1 6 -50 0.804 75 Vsense Rising 50 25 240 220 200 180 160 0 0 0.1 0.2 0.3 0.4 0.5 Vsense - V 0.6 0.7 0.8 140 -50 -25 Figure 7. 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 8. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 7 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) TRANSCONDUCTANCE (SLOW START) vs JUNCTION TEMPERATURE ENABLE PIN VOLTAGE vs TEMPERATURE 1.3 90 85 VIN = 3 .3 V 1.29 1.28 EA - Transconductance - mA/V VIN = 3.3 V, rising 1.27 80 1.26 EN - Threshold - V 75 70 65 60 55 1.25 1.24 1.23 1.22 1.21 1.2 VIN = 3.3 V, falling 1.19 1.18 50 1.17 45 40 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 1.16 1.15 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 9. PIN CURRENT vs TEMPERATURE -0.35 -3.05 -0.55 EN - Pin Current - mA EN - Pin Current - mA VIN = 5 V, Ien = Threshold +50 mV -0.45 -3.15 -3.25 -3.35 -3.45 -0.85 -0.95 -3.65 -1.15 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 11. Figure 12. CHARGE CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE -1 105 -1.2 103 SS/TR - Discharge Current - mA SS/TR - Charge Current - mA -1.25 -50 150 -1.4 VIN = 5 V -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 101 VIN = 5 V 99 97 95 93 91 89 87 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 85 -50 -25 Figure 13. 8 150 -0.75 -1.05 -25 VIN = 5 V, Ien = Threshold -50 mV -0.65 -3.55 -3 -50 125 PIN CURRENT vs TEMPERATURE -0.25 -2.95 -3.75 -50 150 Figure 10. -2.75 -2.85 125 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 14. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE 3 3 VIN = 3.3 V 2.9 2.5 2.7 Shutdown Supply Current - mA VIN - Input Voltage - V 2.8 UVLO Start Switching 2.6 2.5 UVLO Stop Switching 2.4 2.3 2.2 2 1.5 1 0.5 2.1 2 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 Figure 15. Figure 16. SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE SUPPLY CURRENT vs TEMPERATURE 3 150 400 TJ = 25°C 390 VIN = 3.3 V 380 ICC - Supply Current - mA Shutdown Supply Current mA 2.5 2 1.5 1 370 360 350 340 330 320 0.5 310 0 3 3.5 4 4.5 5 VIN - Input Voltage - V 5.5 300 -50 6 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 17. 150 Figure 18. SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE 110 400 TJ = 25°C 390 108 380 106 PWRGD - Threshold - % Vref ICC - Supply Current - mA 125 370 360 350 340 330 320 Vsense Rising, VIN = 3.3 V Vsense Falling 104 102 100 98 96 94 Vsense Rising 92 310 90 300 88 -50 3 3.5 4 4.5 5 VIN - Input Voltage - V 5.5 6 Vsense Falling -25 Figure 19. 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 20. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 9 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) RDSON - Static Drain-Sourec On State Resistance - W PWRGD ON RESISTANCE vs TEMPERATURE 200 180 VIN = 3.3 V 160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 21. OVERVIEW The TPS54418 is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS54418 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the pull up current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54418 is 350 mA when not switching and under no load. When the device is disabled, the supply current is less than 5 mA. The integrated 30 mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents up to 4 amperes. The TPS54418 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54418 to operate approaching 100%. The output voltage can be stepped down to as low as the 0.8 V reference. The TPS54418 has a power good comparator (PWRGD) with 2% hysteresis. The TPS54418 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 105%. The SS (slow start) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin for slow start. The SS pin is discharged before the output power up to ensure a repeatable restart after an over-temperature fault, UVLO fault or disabled condition. The use of a frequency foldback circuit reduces the switching frequency during startup and over current fault conditions to help limit the inductor current. 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54418 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response performance. SLOPE COMPENSATION AND OUTPUT CURRENT The TPS54418 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full duty cycle range. BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION The TPS54418 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1 mF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54418 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.5 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Since the supply current sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high. ERROR AMPLIFIER The TPS54418 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is 225 mA/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating using the SS voltage, the gm is 70 mA/V. The frequency compensation components are placed between the COMP pin and ground. VOLTAGE REFERENCE The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier. ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a 100 kΩ for the R1 resistor and use the Equation 1 to calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. æ ö 0.8 V R2 = R1 ´ ç ÷ è VO - 0.8 V ø (1) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 11 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com TPS54418 VO R1 VSENSE R2 0.8 V + Figure 22. Voltage Divider Circuit ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54418 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 23 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (VSTOP) above 2.7 V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54418 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.55 mA of hysteresis is added. When the EN pin is pulled below 1.18 V, the 2.55 mA is removed. This additional current facilitates input voltage hysteresis. TPS54418 i hys VIN 2.55 mA i1 R1 0.6 mA R2 EN + - Figure 23. Adjustable Under Voltage Lock Out R1 = R2 = 0.944 × VSTART - VSTOP 2.59 ´ 10-6 (2) 1.18 × R1 VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6 (3) SLOW START PIN The TPS54418 regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the SS pin to ground implements a slow start time. The TPS54418 has an internal pull-up current source of 1.8mA which charges the external slow start capacitor. Equation 4 calculates the required slow start capacitor value where Tss is the desired slow start time in ms, Iss is the internal slow start charging current of 1.8 mA, and Vref is the internal voltage reference of 0.8 V. Tss(mS) ´ Iss(mA) Css(nF) = Vref(V) (4) 12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown event occurs, the TPS54418 stops switching and the SS is discharged to 0 volts before reinitiating a powering up sequence. SEQUENCING Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device. Figure 24 shows the sequential method. The power good is coupled to the EN pin on the TPS54418 which enables the second power supply once the primary supply reaches regulation. Ratiometric start up can be accomplished by connecting the SS pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 4. The ratiometric method is illustrated in Figure 26. TPS54418 PWRGD EN1 = 2 V / div EN EN SS SS PWRGD1 = 2 V / div Vout1 = 1 / div PWRGD Vout2 = 1 V / div Time = 5 msec / div Figure 24. Sequential Start-Up Sequence Figure 25. Sequential Startup using EN and PWRGD TPS54418 EN1 = 2 V / div EN SS Vout1 = 1 V / div PWRGD Vout2 = 1 V / div TPS54418 EN Time = 5 msec / div SS PWRGD Figure 26. Schematic for Ratiometric Start-Up Sequence Figure 27. Ratiometric Start-Up using Coupled SS Pins Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 13 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin) The switching frequency of the TPS54418 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 1000kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figures TBD and TBD, or Equation 5. 311890 RT (kW) = Fsw(kHz)1.0793 (5) Fsw(kHz) = 133870 RT(kW)0.9393 (6) To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 60 ns at full current load and 110 ns at no load, and limits the maximum operating input voltage or output voltage. OVERCURRENT PROTECTION The TPS54418 implements a cycle by cycle current limit. During each switching cycle the high side switch current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp functions as a switch current limit. FREQUENCY SHIFT To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54418 implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%, then 75%, then 50%, then 25% as the voltage decreases from 0.8 to 0 volts on VSENSE pin to allow the low side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.8 volts. See Figure 7 for details. REVERSE OVERCURRENT PROTECTION The TPS54418 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is more than 1.3 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs. SYNCHRONIZE USING THE RT/CLK PIN The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 28. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least 75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin. 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 TPS54418 SYNC Clock = 2 V / div PLL PH = 2 V / div RT/CLK Clock Source RT Time = 500 nsec / div Figure 28. Synchronizing to a System Clock Figure 29. Plot of Synchronizing to System Clock POWER GOOD (PWRGD PIN) The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V. OVERVOLTAGE TRANSIENT PROTECTION The TPS54418 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next clock cycle. THERMAL SHUTDOWN The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 160°C, the device reinitiates the power up sequence by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C. SMALL SIGNAL MODEL FOR LOOP RESPONSE Figure 30 shows an equivalent model for the TPS54418 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 225 mA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 15 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com PH VO Power Stage 13.0 A/V a b R1 c RL COMP R3 C2 RESR 0.8 V CO RO VSENSE gm 225 uA/V C1 COUT R2 Figure 30. Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 30 is a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54418 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 7 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage transconductance. The gm for the TPS54418 is 13.0 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 8. As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 9]. The combined effect is highlighted by the dashed line in the right half of Figure 31. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. VO Adc VC RESR fp RL gmps COUT fz Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control æ ç 1+ vo è 2p = Adc ´ vc æ ç 1+ è 2p ö s ÷ × ¦z ø ö s ÷ × ¦p ø (7) Adc = gmps ´ RL 16 (8) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com ¦p = ¦z = SLVS946A – MAY 2009 – REVISED MAY 2010 1 C OUT ´ R L ´ 2 p (9) 1 COUT ´ RESR ´ 2p (10) SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54418 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 32. The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type 2A, one additional high frequency pole is added to attenuate high frequency noise. VO R1 VSENSE COMP gmea R2 Vref RO CO 5pF Type 2A R3 C2 Type 2B R3 C1 C1 Figure 32. Types of Frequency Compensation The design guidelines for TPS54418 loop compensation are as follows: 1. Tthe modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 11 and Equation 12. Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 13 and Equation 14 to estimate a starting point for the crossover frequency, fc. Equation 13 is the geometric mean of the modulator pole and the esr zero and Equation 14 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 13 or Equation 14 as the maximum crossover frequency. Iout m ax 2 p ´ Vout ´ Cout (11) 1 ¦ z m od = 2 p ´ Resr ´ Cout (12) ¦C = ¦p mod ´ ¦ z mod (13) ¦C = ¦p mod ´ ¦ p m od = ¦ sw 2 (14) 2. R3 can be determined by 2p × ¦ c ´ Vo ´ COUT R3 = gmea ´ Vref ´ gmps (15) Where is the gmea amplifier gain (225 mA/V), gmps is the power stage gain (13 A/V). ¦p = 1 C OUT ´ R L ´ 2 p . C1 can be determined by 3. Place a compensation zero at the dominant pole R ´ COUT C1 = L R3 4. C2 is optional. It can be used to cancel the zero from Co’s ESR. (16) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 17 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 C2 = 18 www.ti.com Resr ´ COUT R3 (17) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level. For this example, we start with the following known parameters: Output Voltage 1.8 V Transient Response 1 to 2A load step ΔVout = 3% Maximum Output Current 4A Input Voltage 3.3 V nom. 3 V to 5 V Output Voltage Ripple < 30 mV p-p Start Input Voltage (rising VIN) 3.1 V Stop Input Voltage (falling VIN) 2.8 V Switching Frequency (Fsw) 1000 kHz SELECTING THE SWITCHING FREQUENCY The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest switching frequency possible since this produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a high efficiency operation. Using Equation 5, R4 is calculated to be 180 kΩ. A standard 1% 182 kΩ value was chosen in the design. Figure 33. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO OUTPUT INDUCTOR SELECTION The inductor selected works for the entire TPS54418 input voltage range. To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 19 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com For this design example, use KIND = 0.3 and the inductor value is calculated to be 0.96 mH. For this design, a nearest standard value was chosen: 1.0 mH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 20 and Equation 21. For this design, the RMS inductor current is 4.014 A and the peak inductor current is 4.58 A. The chosen inductor is a TOKO FDV0630-1R0M. It has a current rating of 9.1 A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Vinmax - Vout Vout ´ L1 = Io ´ Kind Vinmax ´ ¦ sw (18) Iripple = ILrms = Vinmax - Vout Vout ´ L1 Vinmax ´ ¦ sw Io 2 + æ Vo ´ (Vinmax - Vo) ö 1 ´ ç ÷ 12 è Vinmax ´ L1 ´ ¦ sw ø (19) 2 (20) Iripple ILpeak = Iout + 2 (21) OUTPUT CAPACITOR There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary to accomplish this. For this example, the transient load response is specified as a 3% change in Vout for a load step from 1A (25% load) to 2A (50%). For this example, ΔIout = 2-1 = 1.0 A and ΔVout= 0.03 × 1.8 = 0.054 V. Using these numbers gives a minimum capacitance of 37mF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 23 yields 4.8uF. 2 ´ DIout Co > ¦ sw ´ DVout (22) Co > 1 ´ 8 ´ ¦ sw 1 Voripple Iripple Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. 20 Submit Documentation Feedback (23) Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 26 mΩ. In this case, the ESR of the ceramic capacitor is much less than 26 mΩ. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 22 mF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 333 mA. Voripple Resr < Iripple (24) Icorm s = Vout ´ (Vinm ax - Vout) 12 ´ Vinm ax ´ L1 ´ ¦ sw (25) INPUT CAPACITOR The TPS54418 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 mF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54418. The input ripple current can be calculated using Equation 26. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 mF and one 0.1 mF 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, Ioutmax=4 A, Cin=10 mF, Fsw=1 MHz, yields an input voltage ripple of 99 mV and a rms input ripple current of 1.96 A. Icirms = Iout ´ Vout ´ Vinmin (Vinmin - Vout ) Vinmin (26) Ioutmax ´ 0.25 DVin = Cin ´ ¦ sw (27) SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54418 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The slow start capacitor value can be calculated using Equation 28. For the example circuit, the slow start time is not too critical since the output capacitor value is 44 mF which does not require much current to charge to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In TPS54418, Iss is 2 mA and Vref is 0.8 V. Tss(ms) ´ Iss(mA) Css(nF) = Vref(V) (28) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 21 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com BOOTSTRAP CAPACITOR SELECTION A 0.1 mF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating. UNDER VOLTAGE LOCK OUT SET POINT The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54418. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 3.1 V (VSTART). After the regulator starts switching, it should continue to do so until the input voltage falls below 2.8 V (VSTOP). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 29 and Equation 30 can be used to calculate the resistance values necessary. From Equation 29 and Equation 30, a 48.7 kΩ between Vin and EN and a 32.4 kΩ between EN and ground are required to produce the 3.1 and 2.8 volt start and stop voltages. 0.944 × VSTART - VSTOP R1 = 2.59 ´ 10-6 (29) R2 = 1.18 × R1 VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6 (30) OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION For the example design, 100 kΩ was selected for R6. Using Equation 31, R7 is calculated as 80 kΩ. The nearest standard 1% resistor is 80.5 kΩ. Vref R7 = R6 Vo - Vref (31) Due to the internal design of the TPS54418, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal vlotage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 32 ( ( ( )))- (Ioutmin ´ (RL + RDS )) Voutmin = Ontimemin ´ Fsmax ´ Vinmax - Ioutmin ´ (2 ´ RDS ) Where: Voutmin = minimum achieveable output voltage Ontimemin = minimum contollable on-time (60 ns typical. 110 nsec no load) Fsmax = maximum switching frequency including tolerance Vinmax = maximum input voltage Ioutmin = minimum load current RDS = minimum high side MOSFET on resistance (30 - 44 mΩ) RL = series resistance of output inductor (32) There is also a maximum acheivable output voltage which is limited by the minimum off time. The maximum output voltage is given by Equation 33 22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 )( ( ( )) Voutmax = 1 - (Offtimemax ´ Fsmax ) ´ Vinmin - Ioutmax ´ (2 ´ RDS ) - Ioutmax ´ (RL + RDS ) Where: Voutmax = maximum achieveable output voltage Offtimeman = maximum off time (60 nsec typical) Fsmax = maximum switching frequency including tolerance Vinmin = minimum input voltage Ioutmax = maximum load current RDS = maximum high side MOSFET on resistance (60 - 70 mΩ) RL = series resistance of output inductor (33) COMPENSATION There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54418. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design. To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 34 and Equation 12. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 36 and Equation 37 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 8.04 kHz and fzmod is 2412 kHz. Equation 36 is the geometric mean of the modulator pole and the esr zero and Equation 37 is the mean of modulator pole and the switching frequency. Equation 36 yields 139 kHz and Equation 37 gives 63 kHz. Use the lower value of Equation 36 or Equation 37 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed). Iout m ax 2 p ´ Vout ´ Cout (34) 1 ¦ z m od = 2 p ´ Resr ´ Cout (35) ¦C = ¦p mod ´ ¦ z mod (36) ¦C = ¦p mod ´ ¦ p m od = ¦ sw 2 (37) The compensation design takes the following steps: 1. Set up the anticipated cross-over frequency. Use Equation 38 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency (fc) is 35 kHz. The power stage gain (gmps) is 13 A/V and the error amplifier gain (gmea) is 225 mA/V. 2p × ¦ c ´ Vo ´ Co R3 = Gm ´ Vref ´ VIgm (38) 2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 39. Ro ´ Co C3 = R3 (39) 3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it. From the procedures above, the compensation network includes a 7.5 kΩ resistor and a 2700 pF capacitor. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 23 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com APPLICATION CURVES EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 3.3 Vin,1.8 Vout 95 90 90 80 3.3 Vin,1.8 Vout Efficiency - % 5 Vin, 1.8 Vout Efficiency - % 85 80 75 70 60 5 Vin, 1.8 Vout 50 40 70 30 65 20 60 10 0 0.001 55 0.01 0.1 Output Current - A 50 0 1 2 3 1 10 4 Output Current - A Figure 34. Figure 35. TRANSIENT RESPONSE, 2 A STEP Vout = 50 mV / div (ac coupled) TRANSIENT RESPONSE, 4 A STEP Vout = 50 mV / div (ac coupled) Iout = 1 A / div (1 A to 3 A load step) Iout = 2 A / div (0 A to 4 A load step) Time = 500 μsec / div Time = 600 μsec / div Figure 36. Figure 37. POWER UP VOUT, VIN POWER DOWN VOUT, VIN Vin = 5 V / div Vin = 5 V / div EN = 2 V / div EN = 2 V / div SS = 2 V / div SS = 2 V / div Vout = 2 V / div Vout = 2 V / div Time = 5 msec / div Time = 5 msec / div Figure 38. 24 Figure 39. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 POWER UP VOUT, EN POWER DOWN VOUT, EN Vin = 5 V / div Vin = 5 V / div EN = 2 V / div EN = 2 V / div SS = 2 V / div SS = 2 V / div Vout = 2 V / div Vout = 2 V / div Time = 5 msec / div Time = 5 msec / div Figure 40. Figure 41. OUTPUT RIPPLE, 0 A OUTPUT RIPPLE, 4 A Vout = 10 mV / div (ac coupled) Vout = 10 mV / div (ac coupled) PH = 2 V / div PH = 2 V / div Time = 500 nsec / div Time = 500 msec / div Figure 42. Figure 43. INPUT RIPPLE, 0 A INPUT RIPPLE, 4 A Vin = 100 mV / div (ac coupled) Vin = 100 mV / div (ac coupled) PH = 2 V / div PH = 2 V / div Time = 500 nsec / div Time = 500 nsec / div Figure 44. Figure 45. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 25 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com LOAD REGULATION vs LOAD CURRENT CLOSED LOOP RESPONSE, VIN (3.3 V), 4 A 60 180 50 150 90 20 60 10 30 Gain 0.1 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 -180 0.05 0 -0.05 -0.1 -0.15 -0.2 1000000 100000 10000 1000 100 Frequency - Hz Percent Deviation - % 30 0 Vin = 3.3 0.15 120 Phase Phase - Deg Gain 40 0.2 0 1 2 3 4 Output Current - A Figure 46. Figure 47. LOAD REGULATION vs LOAD CURRENT REGULATION vs INPUT VOLTAGE 0.2 0.1 Vin = 5.0 V 0.08 0.15 Iout = 2 A Percent Deviation - % Percent Deviation - % 0.06 0.1 0.05 0 -0.05 -0.1 0.04 0.02 0 -0.02 -0.04 -0.06 -0.15 -0.08 -0.2 -0.1 0 1 2 3 4 3 Output Current - A 4 5 6 Input Voltage-V Figure 48. Figure 49. POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq). Pcon = Io2 × Rdson Pd = ƒsw × Iout × 0.7 × 60 × 10-9 Psw = 2 × Vin2 × ƒsw × Io × 0.25 × 10-9 Pgd = 2 × Vin × 3 × 10-9 × ƒsw Pq = 350 × 10-6 × Vin Where: IOUT is the output current (A). Rdson is the on-resistance of the high-side MOSFET (Ω). VOUT is the output voltage (V). 26 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 VIN is the input voltage (V). ƒsw is the switching frequency (Hz). So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth × Ptot For given TJMAX = 150°C TAmax = TJ max – Rth × Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C). Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C). There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator. As an example, the maximum ambient temperature versus power dissapation for the EVM is shown in Figure 51. 150 140 Ta = room temperature, no air flow Tj - Junction Temperature 130 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 3 3.5 Power Dissapated (W) Figure 50. Junction Temperature vs IC Power Dissipation Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 27 TPS54418 SLVS946A – MAY 2009 – REVISED MAY 2010 www.ti.com TAmax - Maximum Ambient Temperature - C 150 140 130 Tjmax = 150 °C, no air flow 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 3 3.5 Power Dissapated (W) Figure 51. Maximum Ambient Temperature vs IC power Dissipation LAYOUT Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 52 for a PCB layout example. The GND pins and AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors. For operation at full rated load, the top side ground area along with any additional internal ground planes must provide adequate heat dissipating area. Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output inductor. Since the PH connection is the switching node, the output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. 28 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 TPS54418 www.ti.com SLVS946A – MAY 2009 – REVISED MAY 2010 VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA VIA to Ground Plane Figure 52. PCB Layout Example Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS54418 29 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS54418RTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples TPS54418RTET ACTIVE WQFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Contact TI Distributor or Sales Office (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DLP® Products www.dlp.com Communications and Telecom www.ti.com/communications DSP dsp.ti.com Computers and Peripherals www.ti.com/computers Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps Interface interface.ti.com Energy www.ti.com/energy Logic logic.ti.com Industrial www.ti.com/industrial Power Mgmt power.ti.com Medical www.ti.com/medical Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Space, Avionics & Defense www.ti.com/space-avionics-defense RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video Wireless www.ti.com/wireless-apps Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2010, Texas Instruments Incorporated