FINTEK F72830SG

F72830
Four-Phase Linear Controller with I2C
Interface
Release Date: July, 2007
Version: 0.14P
Fintek
Feature Integration Technology Inc.
F72830
F72830 Datasheet Revision History
Version
Date
Page
Revision History
0.10P
Sep, 2006
0.11P
Sep, 2006
18
Register-Chip ID
0.12P
Dec, 2006
4
Pin configuration
5
Pin 9, GND Æ VSS
Preliminary version
EN pin description
7
Electrical characteristic, VCC ÆVDDA
8
Input high voltage: 2V Æ 1.5V
21
Application circuit
0.13P
Feb, 2007
7
VREF Range: 0.79~0.83V, typical: 0.8V
0.14P
Jul, 2007
20
Update company address
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
1
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
Table of Contents
1
GENERAL DESCRIPTION ........................................................................................................................................................ 3
2
FEATURE ..................................................................................................................................................................................... 3
3
PIN CONFIGURATION .............................................................................................................................................................. 4
4
PIN DESCRIPTION..................................................................................................................................................................... 4
5
ELECTRICAL CHARACTERISTIC......................................................................................................................................... 6
5.1
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 6
5.2
DC AND AC ELECTRICAL CHARACTERISTICS (VDDA = 5V, TA = 25℃) ................................................................................... 7
5.3
SPECIFICATION OF RELIABILITY................................................................................................................................................ 8
6
BLOCK DIAGRAM ..................................................................................................................................................................... 9
7
SIMPLIFIED EXTERNAL APPLICATION DIAGRAM....................................................................................................... 10
8
FUNCTIONAL DESCRIPTION ............................................................................................................................................... 10
9
8.1
LINEAR CONTROLLER DESCRIPTION....................................................................................................................................... 10
8.2
SOFT-START ............................................................................................................................................................................ 11
8.3
UNDER VOLTAGE PROTECTION ................................................................................................................................................ 13
8.4
ACCESS INTERFACE ................................................................................................................................................................ 13
REGISTER DESCRIPTION ..................................................................................................................................................... 15
9.1 LR_1, LR_2 Fine Tune Voltage Register ⎯ Index 1.................................................................................................................. 15
9.2 LR_3, LR_4 Fine Tune Voltage Register ⎯ Index 2.................................................................................................................. 16
9.3 Under Voltage, Over Current Enable Protection Register ⎯ Index 03h .................................................................................... 17
9.4 Reserved Function, Read back SSOK Status, If LR finished Soft Start, it Will Read back 1 Register ⎯ Index 04h ................ 17
9.5 CHIP ID 1 ⎯ INDEX 5AH ............................................................................................................................................................ 18
9.6 CHIP ID 2 ⎯ Index 5Bh ............................................................................................................................................................ 18
10 ORDERING INFORMATION .................................................................................................................................................. 19
11 PACKAGE DIMENSIONS (16-SOP) ....................................................................................................................................... 20
12 APPLICATION CIRCUIT ........................................................................................................................................................ 21
2
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
1 General Description
The F72830 is a quadro MOSFET drivers specifically designed to drive quadro power N-Channel MOSFETs as
a four-phase linear regulators. The device contains under voltage protection for every linear controller, an
external ceramic capacitor to adjust slew rate of soft-start, and integrated I2C interface. The built-in I2C interface
provides the function to fine tune the output of every linear controller from 0.74V to 1.04V, 0.02V per step, and
the default output is set to 0.8V.
The F72830 also offers 3 independent enable pins to control the corresponding linear controller. Linear
controller 1 is active as power on, and other remained linear controller 2~4 are controlled by enable pin, EN2~4.
Except being a regular linear controller, the F72830 can be paired with the chip, which contains AMD K8 power
on/off timing sequence to be used a platform power supplier, for example, F71863, or any specific purpose. The
chip is a 16pin SOP package and powered by 5/12V.
2 Feature
‹
4 Channels of Linear Controller Supported Controlled by 3 Enable Pins:
„
Linear Controller 1 Will Be Active as Power on
‹
„
Linear Controller 2~4 Can Be Active in any Sequence or at the Same Time(in 3CLK Debounce)
Under Voltage Protection of All Linear Controllers
‹
External Capacitor for Adjusting Soft-start Slew Rate
‹
Integrated I2C Interface to Fine Tune Output of Linear Controller from 0.74V to 1.04V, 0.02V per Step,
Typical Output Is 0.8V
‹
Independent Enable Pin Controls Single Linear Controller On/Off Individually
‹
Powered by VVDDA: 5~12V
‹
16-SOP Green Package
3
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
3 Pin Configuration
Figure1. F72830 pin configuration
4 Pin Description
I/OD12st
- TTL level bi-directional pin with schmitt trigger., Open-drain outpu with 12 mA sink capability.
INst
- TTL level input pin with schmitt trigger.
AIN - Input pin(Analog).
AOUT
P
- Output pin(Analog).
- Power.
4
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
‹
‹
Power Pins
PIN NO
PIN NAME
9
VSS
16
VDDA
TYPE
P
DESCRIPTION
Power pins
Control signal
PIN NO
PIN NAME
TYPE
PWR
10
EN2
INts
VDD
Linear driver2 control signal input, input voltage > 1.5V, L Æ H
11
EN3
INts
VDD
Linear driver3 control signal input, input voltage > 1.5V, L Æ H
12
EN4
INts
VDD
Linear driver4 control signal input, input voltage > 1.5V, L Æ H
‹
DESCRIPTION
Switching Signal & Linear/PWM Controller
PIN NO
PIN NAME
TYPE
PWR
1
LR1_SEN
AIN
VDD
DESCRIPTION
Sense the voltage of linear regulator. LR1_SEN and LR1_DRV
act as a linear regulator. The linear controller 1 will act while
powering on the chip and finishing soft-start.
Connect this pin to the gate of a suitable N-channel MOSFET.
2
LR1_DRV
AOUT
VDDA
LR1_SEN and LR1_DRV act as a linear regulator. The linear
controller 1 will act while powering on the chip and finishing
soft-start.
Connect this pin to the gate of a suitable N-channel MOSFET.
LR2_SEN and LR2_DRV act as a linear regulator. The linear
3
LR2_DRV
AOUT
VDDA
controller 2 will act when the input of EN2 acts high. The linear
controller 2 will be off when the input of EN2 acts low.
Sense the voltage of linear regulator. LR2_SEN and LR2_DRV
act as a linear regulator. The linear controller 2 will act when the
4
LR2_SEN
AIN
VDD
input of EN2 acts high. The linear controller 2 will be off when the
input of EN2 acts low.
Sense the voltage of linear regulator. LR3_SEN and LR3_DRV
act as a linear regulator. The linear controller 3 will act when the
5
LR3_SEN
AIN
VDDA
input of EN3 acts high. The linear controller 3 will be off when the
input of EN3 acts low.
5
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
Connect this pin to the gate of a suitable N-channel MOSFET.
LR3_SEN and LR3_DRV act as a linear regulator. The linear
6
LR3_DRV
AOUT
VDDA
controller 3 will act when the input of EN3 acts high. The linear
controller 3 will be off when the input of EN3 acts low.
Sense the voltage of linear regulator. LR4_SEN and LR4_DRV
7
LR4_DRV
AOUT
VDDA
act as a linear regulator. The linear controller 4 will act when the
input of EN4 acts high. The linear controller 4 will be off when the
input of EN4 acts low.
Connect this pin to the gate of a suitable N-channel MOSFET.
LR4_SEN and LR4_DRV act as a linear regulator. The linear
8
LR4_SEN
AIN
VDD
controller 4 will act when the input of EN4 acts high. The linear
controller 4 will be off when the input of EN4 acts low.
‹
Others
PIN NO
PIN NAME
TYPE
PWR
DESCRIPTION
14
SCLK
INts
VDD
I2C serial bus clock
13
SDATA
I/OD12ts
VDD
I2C serial bus data
Soft-Start. Connect this pin to a small ceramic capacitor to
15
SS
AIN
VDD
determine the soft-start rate. The value of capacitor is bigger, the
slew rate is slower.
* The VDD is the internal voltage which is a step-down voltage generated from input voltage, VDDA.
5 Electrical Characteristic
5.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATINGS
UNIT
IC supply voltage
VDDA
17
V
ESD classification
HBM
2
kV
6
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
※ Maximum junction temperature (plastic
package)
※ Maximum storage temperature
Tj
150
°C
TSTO
-65 ~ 150
°C
260
°C
※ Maximum lead temperature (soldering
10s)
Note: If ICs are stressed beyond the limits listed in the “absolute maximum ratings”, they may be permanently destroyed. These are stress ratings only and
functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Package thermal information
PARAMETER
Thermal resistance junction-ambient
SYMBOL
SOIC
UNIT
Rth_ja
57
°C/W
Recommended Operating Conditions
Supply Voltage, VDDA -----------------------------------------------------------------------------------
5V~12V 10%
Ambient Temperature Range-----------------------------------------------------------------------
0 C to 70 C
Junction Temperature Range-----------------------------------------------------------------------
0 C to 125 C
5.2 DC and AC electrical characteristics (VDDA = 5V, TA = 25℃)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
5
10
mA
VDDA SUPPLY CURRENT/Regulated Voltage
Nominal supply current
IVDDA
POWER-ON RESET
Rising VDDA threshold
3.0
3.3
3.6
V
Falling VDDA threshold
2.7
3.0
3.3
V
200
250
300
kHz
OSCILLATOR AND Protection
Free running frequency
FOSC
Soft-start interval
TSS
12
uA
REFERENCE VOLTAGE
Reference voltage
VREF
VDDA=12V, T= 25
0.79
0.8
0.83
V
LINEAR REGULATOR
7
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
PARAMETER
SYMBOL
DC gain
TEST CONDITIONS
A0
Gain-bandwidth product
Under voltage level
GBWP
CL = 1000pF
VUV
Percent of nominal
MIN.
TYP.
MAX.
UNIT
-
70
-
dB
-
1.86
-
MHz
0.3
0.4
0.5
V
※: Design Guarantee
I/O PAD DC Characteristics
(Ta = 0° C to 70° C, VDDA = 5~12V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/OD12st-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink capability.
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Current
IOL
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
1.5
+12
+1
-1
V
VDDA =5~12V
V
VDDA = 5~12V
mA
VOL = 0.4V
μA
VIN = 3.3V
μA
VIN = 0V
I/O12st- TTL level bi-directional pin with schmitt trigger and with 12mA source-sink capability.
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Current
IOL
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
1.5
-12
+1
-1
V
VDDA =5~12V
V
VDDA = 5~12V
mA
VOL = 0.4 V
μA
VIN = 3.3V
μA
VIN = 0V
INst - TTL level input pin with schmitt trigger
Input Low Voltage
VIL
Input High Voltage
VIH
Input High Leakage
ILIH
Input Low Leakage
ILIL
0.8
1.5
V
V
+1
-1
μA
VIN = 3.3V
μA
VIN = 0 V
mA
VOL = 0.4V
OD12-Open-drain output with12 mA sink capability.
Output Low Current
IOL
-12
5.3 Specification of Reliability
Test Item
Description
Y/N
Test Item
Description
ESD
VHBM > 2KV, VMM > 200V
TH(B)
1000Hrs, 85% RH, 85℃
Latch-UP
Itr => 50~ 100mA
PCT
168 Hrs, 100% RH , 121℃
8
Y/N
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
6 Block Diagram
VDDA
VDDA
BandGap
Bias & SS
Power On
Reset
REG3V
0.8V
LR1_DRV
VDD
SS
LR1_SEN
0.4V
LR1_UV
VDDA
0.8V
LR3_DRV
VDDA
0.8V
LR3_SEN
LR2_DRV
0.4V
LR3_UV
VDDA
0.8V
I2C Interface,
ACPI Control Circuit,
VFB fine tune voltage LR2_UV
LR2_SEN
0.4V
LR4_DRV
LR4_SEN
0.4V
LR4_UV
SCL
SDA
Figure2. F72830 block diagram
9
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
7 Simplified External Application Diagram
PWR
SDA
I2C &
ACPI Control
SCL
LR1
LR
Controllers
LR
Application
circuit
LR2
LR3
LR4
Figure3. F72830 external application diagram
8 Functional Description
8.1 Linear Controller Description
The F72830 contains 4 sets of linear controllers. When the chip is powered on, soft-start will be active. Then, the
first linear controller will generate the output voltage. The other 3 sets of linear controllers, LR_2, LR_3, and LR_4
are controlled by the corresponding enable pin, EN2, EN3, and EN4. There is no priorities in linear controllers 2~4.
The output voltage sequence of linear controllers 2~4 issued depends on enable signal of EN2~4 sequence only. If
any enable pin acts high before or at the same time as VDDA PWROK, the corresponding linear controller will
generate output as linear controller 1 simultaneously. When the enable pin receives enable signal, soft-start and
enable status checking will be active. To receive first coming high signal from any enable pin then soft-start will
start. Before the duration of soft-start reaching 0.1V, any successive acting high enable signal is considered in the
same soft-start sequence. All of the linear regulators corresponding to high acting enable pins will generate output
following soft-start procedure. If the successive enable signal is received out of the bound of the duration, the
enable sequence will be arranged after this period of soft-start finishes. The detail can be referred in Figure4.
10
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
1.6V
0.1V
PAD_SS
SS_LOW
Allowed Soft start Active region Soft Start can't be active regionAllowed Soft start Active region
EN2
EN3
EN4
Figure4. F72830 enable and Soft Start Timing Chart
8.2 Soft-start
Pin15 of the F72830 acts as soft-start function. As shown in schematic, a ceramic capacitor is attached between
this pin and ground. When power is first applied to the chip, a constant current is applied from the pin into an
external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of F72830
providing a soft-start for linear regulator. As for switches, they must be either on or off in the system therefore
soft-start has no effect on them. It is important to know soft-start is not an enable signal; pulling it low will not be
sure to turn off all outputs. But if there are appropriate signals asserted, the switches will be turn on at once. The
actual state of F72830 on power up will be determined by the controlled input signal. And the soft-start is effective
only during power on. The detail timing chart could be shown as Figure 5.
11
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
3.3v
3.0v
VDDA
RESET_N
50u
LR1_SS
LR1_DRV
SD LR1
EN_2
LR2_SS
3clk debounce
3clk debounce
SD LR2
LR2_DRV
EN_3
LR3_SS
3clk debounce
3clk debounce
SD LR3
LR3_DRV
EN_4
LR4_SS
3clk debounce
LR4_DRV
3clk debounce
SD LR4
Note that: LR1, LR2, LR3, and LR4 can be active at the same time or not. (if you want to let the LR2, LR3, and LR4 soft start at the same
time, EN_2, EN_3, and EN_4 should be high before SS under 0.1V. It is recommended to set high at the same time, if you want to let the
linear regulators soft start at the same time. If you set high after SS is higher than 0.1v, it will wait the soft start finished, and begin the
next soft start). If LR2~LR4 are desired to act as LR1 while power on, EN2~ EN4 must be pulled high before VDDA reaches PWROK.
Figure5. Soft-start timing and indication
12
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
8.3 Under voltage protection
If the LR_SEN voltage drops below 0.4V, a fault signal is generated. When under voltage condition occurs, the
related Linear Regulator will shut down.
8.4 Access interface
The F72830 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave
device under the control of the master device, using two device terminals SCL and SDA. The controller can provide
a clock signal to the device SCL pin and read/write data from/to the device through the device SDA pin. The
address default is 0x5E(0101_1110) and the operation of device to the bus is described with details in the following
sections.
(a) SMBus write to internal address register followed by the data byte
0
7
8
0
7
8
SCLK
SDA
0
Start By
Master
1
0
1
1
1
1
R/W
D7
Ack
by
830
Frame 1
Serial Bus Address Byte
D6
D5
D4
D3
D2
D1
D0
Ack
by
569
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Frame 3
Data Byte
Stop
by
Master
Figure 6. Serial Bus Write to Internal Address Register followed by the
(b) Serial bus write to internal address register only
13
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
0
7
8
0
7
8
SCL
SDA
0
1
Start By
Master
0
1
1
1
1
R/W
D7
D6
Ack
by
830
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
569
Frame 2
Internal Index Register Byte
Stop by
Master
0
Figure 7. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
7
8
0
7
8
SCL
SDA
0
Start By
Master
1
0
1
1
1
1
R/W
D7
Ack
by
830
Frame 1
Serial Bus Address Byte
D6
D5
D4
D3
D2
Frame 2
Internal Index Register Byte
D1
D0
Ack
Stop by
by
Master Master
1
Figure 8. Serial Bus Read from Internal Address Register
14
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
9 Register Description
9.1 LR_1, LR_2 Fine Tune Voltage Register ⎯ Index 1
Bit
Name
R/W
Default
Description
Fine tune LR_1 reference voltage, LR1 Voltage table is set by Register
01h bit 7:4.
7:4
LR_1
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
Fine tune LR_2 reference voltage, LR2 Voltage table is set by Register
01h bit 3:0.
3:0
LR_2
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
15
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
9.2 LR_3, LR_4 Fine Tune Voltage Register ⎯ Index 2
Bit
Name
R/W
Default
Description
Fine tune LR_3 reference voltage, LR3 Voltage table is set by Register
02h bit 7:4.
7:4
LR_3
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
Fine tune LR_4 reference voltage, LR4 Voltage table is set by Register
02h bit 3:0.
3:0
LR_4
R/W
3
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
16
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
9.3 Under Voltage, Over Current Enable Protection Register ⎯ Index 03h
Bit
Name
R/W
Default
Description
7
Reserved
R/W
1
Reserved Register
6
Reserved
R/W
0
Reserved Register
5
Reserved
R/W
0
Reserved Register
4
SAME_UV
R/W
0
If set to 1, one of 4 LR occurs UV, it will shut down all LR
3
LR1_UVEN
R/W
1
LR1 Under voltage enable
2
LR2_UVEN
R/W
1
LR2 Under voltage enable
1
LR3_UVEN
R/W
1
LR3 Under voltage enable
0
LR4_UVEN
R/W
1
LR4 Under voltage enable
9.4 Reserved Function, Read back SSOK Status, If LR finished Soft Start, it Will Read back 1 Register ⎯ Index
04h
Bit
Name
R/W
Default
7
SOFT_SD_LR1
R/W
0
6
SOFT_SD_LR2
R/W
5
SOFT_SD_LR3
R/W
4
SOFT_SD_LR4
R/W
3
LATCH_S1_SSOK
R
0
If LR1 finished soft start, it will read back 1
2
LATCH_S2_SSOK
R
0
If LR2 finished soft start, it will read back 1
1
LATCH_S3_SSOK
R
0
If LR3 finished soft start, it will read back 1
0
LATCH_S4_SSOK
R
0
If LR4 finished soft start, it will read back 1
0
Description
If set to 1, LR1 will SD, and if set to 0, and the Power is higher than
internal PWROK, it will re-soft start.
If set to 1, LR2 will SD, and if set to 0, it will detect EN2 high to do soft
start
0
If set to 1, LR3 will SD, and if set to 0, it will detect EN3 high to do soft
start
0
If set to 1, LR4 will SD, and if set to 0, it will detect EN4 high to do soft
start
17
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
9.5 CHIP ID 1 ⎯ Index 5Ah
Bit
Name
R/W
Default
7
0
6
0
5
0
4
3
Description
0
CHIP ID 1
R
0
2
1
1
1
0
0
CHIP_ID1 = 8’h06;
9.6 CHIP ID 2 ⎯ Index 5Bh
Bit
Name
R/W
Default
7
0
6
0
5
0
4
3
CHIP ID 2
R
0
Description
CHIP_ID1 = 8’h03;
0
2
0
1
1
0
1
18
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
10 Ordering Information
Part Number
Package Type
Production Flow
F72830SG
16-SOP (Green Package)
Commercial, 0°C to +70°C
19
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
11 Package Dimensions (16-SOP)
Figure9. 16 Pin SOP Package Diagram
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
20
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
12 Application Circuit
+12V
U1
LR1_SEN
LR1_DRV
LR2_DRV
LR2_SEN
LR3_SEN
LR3_DRV
LR4_DEV
LR4_SEN
1
2
3
4
5
6
7
8
LR1_SEN VDDA
LR1_DRV
SS
LR2_DRV SCL
LR2_SEN SDA
EN4
LR3_SEN
LR3_DRV EN3
LR4_DRV EN2
LR4_SEN GND
16
15
14
13
12
11
10
09
C2
0.1u
C1
0.1u
SCL
SDA
EN4
EN3
EN2
F72830
VCC3_3V
Q1
MOSFET N
LR1_DRV
LR1_SEN
VCC3_3V
LR1_VOUT
Rout1
LR3_SEN
Rgnd1
Q3
MOSFET N
LR3_DRV
C3
470u
C4
0.1u
Rgnd3
VCC3_3V
LR2_SEN
C8
0.1u
Q4
MOSFET N
LR4_DRV
LR2_VOUT
Rout2
Rgnd2
C7
470u
VCC3_3V
Q2
MOSFET N
LR2_DRV
LR3_VOUT
Rout3
LR4_SEN
C5
470u
C6
0.1u
LR4_VOUT
Rout4
Rgnd4
C9
470u
C10
0.1u
Figure10. F72830SG Application Circuit
21
2007 V0.14P
Fintek
Feature Integration Technology Inc.
F72830
C33
0.1u
VRAM
RAM
R55 1K
R56 1K
J38
SCL
SDA
EN2
EN3
Q28
ENx > 1.5V =>High
1P05_SEN
L5
DUAL
VRAM
J40
1P5_DRV
3
C40
1000u
C56
470u
C57
0.1u
VCC
PHASE
FB
OCSET
VREF
LGATE
2
R65
Q26
22
8
7
R66
4
R67
VOUT=[(Rout / Rgnd) + 1] * 0.8
4.7u
J42
CON3
POWER CON
Q27
22
J36
C42
1000u
C43
1000u
C44
1000u
VSB
1
2EN3
J37
EN2
1
3
L7
2
4
FB
VCC
DUAL POWER
9
J35
VDUAL
20K
F72815/F72814
0.78V< REF <= 1.2V
VCORE
default REF = 0.8V
VRAM
L6
J33
1
2
3
5
150
VSB 12V
4
3
2
1
C39
470u
UGATE
GND
RAM_REF
BOOT
1
2
6
VCC
1
VCC
R80 200
R83
C38
0.1u
C41
1P8V
1
2
1P5_SEN
D8
0.1u
Q31
C37
1000u
R62
D7
C51
0.1u
1000u
VCORE
1u
J34
CON2
D6
C50
470u
150
10
U4
R73 200
R75
VCORE
VSB 12V
1P05V
1P05_DRV
X_0.1u
X_0.1u
F72830
C32
0.1u
C35
C34
RAM_REF
16
15
14
13
12
11
10
09
C36
1P05_DRV
1P05_SEN
1P5_SEN
1P5_DRV
0.02V per step
DUAL
LR1_SEN VDDA
LR1_DRV
SS
LR2_DRV SCL
LR2_SEN SDA
LR3_SEN EN4
LR3_DRV EN3
LR4_DRV EN2
LR4_SEN GND
1
2
U3
1
2
3
4
5
6
7
8
SUS
0.74V<= REF <= 1.04V
2
1
TP1
R69
R70
0_R
X_33
R71
R68
0.1/10W
C45
X_47n
X_R
DUAL
DUAL
R72
L8
10
1u
C46
0.1u
J39
CON2
0.1u
C49
1
6
C47
470u
FB
OCSET
VREF
0.78V< REF <= 1.2V
GND
3
LGATE
2
R74
22
VSUS
8
L9
7
R76
20K
4
R77
22
4.7u
Q30
C52
1000u
F72815/F72814
C53
1000u
C54
1000u
9
J41
C48
1000u
Q29
UGATE
PHASE
1
2
SUS
BOOT
VCC
U5
5
D9
2
1
R79
R81
R82
X_R
TP2
0_R
X_33
R78
0.1/10W
Note:
Take note of what's kind of GND you using.
C55
X_47n
Figure11. F72830 and F72815 Practice Application Circuit
22
2007 V0.14P