TI TPS51219

TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
High Performance, Single-Synchronous Step-Down Controller
with Differential Voltage Feedback
FEATURES
DESCRIPTION
•
•
•
•
The TPS51219 is a small-sized single buck controller
with adaptive on-time control. It provides a choice of
control modes (D-CAP™ or D-CAP2™) to meet a
wide range of system requirements. It is designed for
tight DC regulation requirements such as the VCCIO
application for Intel® notebooks. The performance
and flexibility of the TPS51219 makes it suitable for
low output voltage, high current, PC system power
rails and similar point-of-load (POL) power supplies.
Differential voltage feedback and the voltage
compensation function combine to provide high
precision power to load devices.
1
23
•
•
•
•
•
•
•
•
•
•
•
Differential Voltage Feedback
DC Compensation for Accurate Regulation
Wide Input Voltage Range: 3 V to 28 V
Output Voltage Range: 0.5 V to 2.0 V with
Fixed Options of 1.05 V and 1.00 V
Wide Output Load Range: 0 A to 20 A+
Adaptive On-Time Modulation with Selectable
Control Architecture and Frequency
– D-CAP™ Mode at 300 kHz/400 kHz for Fast
Transient Response
– D-CAP2™ Mode at 500 kHz/670 kHz for
Ceramic Output Capacitor
4700 ppm/°C, Low-Side RDS(on) Current Sensing
RSENSE Accurate Current Sense Option
Internal, 1-ms Voltage Servo Softstart
Built-In Output Discharge
Power Good Output
Integrated Boost Switch
Built-In OVP/UVP/OCP
Thermal Shutdown (Non-latched)
3 mm × 3 mm, 16-Pin, QFN (RTE) Package
A small package, fixed voltage options and minimal
external component count saves cost and space,
while a dedicated EN pin and pre-set frequency
selections minimize design effort. The skip-mode at
light load condition, strong gate drivers, and low-side
FET RDS(on) current sensing provides high efficiency
operation over a broad load range. The external
resistor current sense option enables accurate
current sensing. The conversion input voltage (the
high-side FET drain voltage) ranges from 3 V to 28 V
and output voltage ranges from 0.5 V to 2.0 V. The
device requires an external 5-V supply.
The TPS51219 is available in a 16-pin, QFN package
and is specified for ambient temperature from -40°C
to 85°C.
APPLICATIONS
•
•
Notebook Computers
I/O Supplies
13
BST
REFIN
14
EN
2
15
MODE
VREF
16
PGOOD
1
PwrPd
VIN
V5IN
PGOOD
EN
SW 12
DH 11
VOUT
TPS51219RTE
4
VSNS
PGND
VSNS
GND
GSNS
TRIP
3
COMP
GSNS
V5
5
6
7
8
9
DL 10
UDG-11006
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP, D-CAP2 are trademarks of Texas Instruments.
Intel is a registered trademark of Intel.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
PACKAGE
–40°C to 85°C
Plastic Quad Flat Pack (QFN)
(1)
ORDERABLE DEVICE
NUMBER
TPS51219RTER
TPS51219RTET
PINS
16
OUTPUT
SUPPLY
MINIMUM
QUANTITY
Tape and reel
3000
Mini-reel
250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MAX
BST
–0.3
36
BST (3)
–0.3
6
–5
30
EN, MODE, TRIP, V5
–0.3
6.0
COMP, REFIN, VSNS
–0.3
3.6
GSNS
–0.35
0.35
PGND
–0.3
0.3
–5
36
SW
Input voltage range (2)
DH
(3)
–0.3
6
DL
–0.3
6
PGOOD
–0.3
6
VREF
–0.3
3.6
DH
Output voltage range (2)
Junction temperature range, TJ
Storage temperature range, TSTG
(1)
(2)
(3)
2
UNIT
MIN
–55
V
V
125
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
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TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
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RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
V5
BST
–0.1
33.5
BST (1)
–0.1
5.5
-3
28
SW (2)
–4.5
28
EN, TRIP, MODE
–0.1
5.5
REFIN, VSNS, COMP
–0.1
3.5
GSNS
–0.3
0.3
PGND
–0.1
0.1
–3
33.5
DH
Output voltage range
TA
(1)
(2)
MAX
5.5
SW
Input voltage range
TYP
4.5
DH (1)
–0.1
5.5
DH (2)
–4.5
33.5
DL
–0.1
5.5
PGOOD
–0.1
5.5
VREF
–0.1
3.5
Operating free-air temperature
–40
85
UNIT
V
V
V
°C
Voltage values are with respect to the SW terminal.
This voltage should be applied for less than 30% of the repetitive period.
THERMAL INFORMATION
TPS51219
THERMAL METRIC (1)
RTE
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance (2)
48.5
θJCtop
Junction-to-case (top) thermal resistance (3)
49.5
θJB
Junction-to-board thermal resistance (4)
22.1
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
22.1
θJCbot
Junction-to-case (bottom) thermal resistance (7)
7.1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.7
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2011, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV5
V5 supply current
TA = 25°C, No load, VEN = 5 V
560
IV5SDN
V5 shutdown current
TA = 25°C, No load, VEN = 0 V
0.5
Output voltage
IVREF = 0 μA wrt GSNS
μA
2.0
μA
VREF OUTPUT
VVREF
VVREF(tol)
Output voltage tolerance
IVREF(ocl)
Current limit
2.000
0 μA ≤ IVREF < 30 μA, TA = 0°C to 85°C
-0.8%
0 μA ≤ IVREF < 300 μA, TA = –40°C to 85°C
-1.2%
VVREF-GSNS = 1.7 V
0.4
V
0.8%
1.2%
1.0
mA
OUTPUT VOLTAGE
VREFIN = 0 V
VVSNS
VSNS sense voltage
VREFIN = 3.3 V
0.5 V ≤ VREFIN ≤ 2 V
VREFIN = 0 V, 0°C ≤ TA ≤ 85°C
VVSNS(tol)
VSNS regulation voltage tolerance
1.000
V
1.050
V
VREFIN
V
–9
9
VREFIN = 0 V, -40°C ≤ TA ≤ 85°C
-14
14
VREFIN = 3.3 V, 0°C ≤ TA ≤ 85°C
–9
9
VREFIN = 3.3 V, -40°C ≤ TA ≤ 85°C
-14
14
VREFIN = 0.5 V and VREFIN = 2.0 V
-5
5
VREFIN1
REFIN voltage for 1.00-V output
0.3
VREFIN1P05
REFIN voltage for 1.05-V output
VOFF_LPCMP
Loop comparator offset voltage
VCOMPCLP
COMP clamp voltage
gM
Error amplifier transconductance
VREFIN = 0 V
IVSNS
VSNS input current
VVSNS = 1.05 V
-1
1
IREFIN
REFIN input current
VREFIN = 0 V
–1
1
IVSNS(dis)
VSNS discharge current
VEN = 0 V, VVSNS = 0.5 V
2.2
VREFIN = 1 V, VSNS shorted to COMP
mV
V
V
-5
5
mV
VREFIN = 0 V, VVSNS = 0.95 V
0.885
VREFIN = 0 V, VVSNS = 1.05 V
1.115
V
130
μS
5
V
12
μA
μA
mA
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
VIN = 12 V, VVSNS = 1.8 V, VMODE = 2.5 V
400
VIN = 12 V, VVSNS = 1.8 V, VMODE = 1.67 V
300
VIN = 12 V, VVSNS = 1.8 V, VMODE = 0.2 V
670
VIN = 12 V, VVSNS = 1.8 V, VMODE = 0.033 V
500
fSW
Switching frequency
kHz
tON(min)
Minimum on time
DH rising to falling (1)
tOFF(min)
Minimum off time
DH falling to rising
320
Source, IDH = –50 mA
1.6
3.0
Sink, IDH = 50 mA
0.6
1.5
Source, IDL = –50 mA
0.9
2.0
Sink, IDL = 50 mA
0.5
1.2
DH-off to DL-on
10
DL-off to DH-on
20
60
ns
MOSFET DRIVERS
RDH
DH resistance
RDL
DL resistance
tDEAD
Dead time
Ω
ns
INTERNAL BOOT STRAP SWITCH
VFBST
Forward voltage
VV5-BST, TA = 25°C, IF = 10 mA
IBSTLK
BST leakage current
TA = 25°C, VBST = 33 V, VSW = 28 V
(1)
4
0.1
0.2
V
0.01
1.5
μA
Ensured by design. Not production tested.
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TPS51219
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
μA
LOGIC THRESHOLD
IMODE
VTHMODE
MODE source current
MODE threshold voltage
VLL
EN low-level voltage
VLH
EN high-level voltage
VLHYST
EN hysteresis voltage
ILLK
EN input leakage current
15.6
16.7
17.8
MODE 0-1
113
143
173
MODE 1-2
253
283
313
MODE 2-3
433
458
483
MODE 3-4
644
667
690
MODE 4-5
914
949
984
MODE 5-6
1329
1369
1409
MODE 6-7
1950
2000
2050
mV
0.5
1.8
V
0.25
–1
0
1
μA
SOFT START
tSS
Soft-start time
Internal soft-start time
1.1
ms
POWERGOOD COMPARATOR
VTHPG
PGOOD threshold
IPG
PGOOD sink current
tPGDLY
PGOOD delay time
tPGCMPSS
PGOOD start-up delay
IPG(leak)
PGOOD leakage current
PGOOD in from higher
106%
108%
PGOOD in from lower
90%
92%
94%
PGOOD out to higher
114%
116%
118%
PGOOD out to lower
82%
84%
86%
3
6
0.8
1.0
VPGOOD = 0.5 V
Delay for PGOOD in
Delay for PGOOD out, with 100 mV over drive
PGOOD comparator wake-up delay
110%
mA
1.2
ms
0.25
µs
2.5
ms
-1
0
1
µA
9
10
11
μA
CURRENT DETECTION
ITRIP
TRIP source current
TA = 25°C, VTRIP = 0.4 V, RDS(on) sensing
TCITRIP (2)
TRIP source current temperature
coefficient (2)
RDS(on) sensing
VTRIP
VTRIP voltage range
RDS(on) sensing
0.2
VTRIP = 3.0 V, RDS(on) sensing
360
375
390
VTRIP = 1.6 V, RDS(on) sensing
190
200
210
VTRIP = 0.2 V, RDS(on) sensing
20
25
30
VTRIP = 3.0 V, RDS(on) sensing
–390
–375
–360
VTRIP = 1.6 V, RDS(on) sensing
–212
–200
–188
VTRIP = 0.2 V, RDS(on) sensing
–30
–25
–20
VOCL
Current limit threshold
VOCLN
Negative current limit threshold
VRTRIP
Resistor sense trip voltage
VZC
Zero cross detection offset
(2)
Resistor sensing
4700
ppm/°C
3
V
mV
mV
25
mV
0
mV
Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Wake-up
4.2
4.4
4.5
Shutdown
3.7
3.9
4.1
118%
120%
122%
UNIT
PROTECTIONS
VUVLO
V5 UVLO threshold voltage
VOVP
OVP threshold voltage
OVP detect voltage
tOVPDLY
OVP propagation delay
With 100 mV over drive
VUVP
UVP threshold voltage
UVP detect voltage
tUVPDLY
UVP delay
tUVPENDLY
UVP enable delay
370
66%
68%
V
ns
70%
1
ms
1.4
ms
THERMAL SHUTDOWN
TSDN
(3)
6
Thermal shutdown threshold
Shutdown temperature (3)
Hysteresis
(3)
140
10
°C
Ensured by design. Not production tested.
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DEVICE INFORMATION
VREF
PGOOD
MODE
EN
BST
RTE PACKAGE (TOP VIEW)
16
15
14
13
1
12 SW
TPS51219
VSNS
4
PowerPADTM
10 DL
9
5
6
7
8
PGND
3
GND
GSNS
11 DH
TRIP
2
COMP
REFIN
V5
PIN FUNCTIONS
PIN
NAME
BST
NO.
13
I/O
DESCRIPTION
I
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the BST pin to the SW pin.
COMP
5
I
Connection for the DC compensation integrator for improved load-line performance. Connect a capacitor from
this pin to the VSNS pin (when operating in D-CAP2 mode), or to the positive terminal of the output capacitor
(when operating in D-CAP mode). Connect directly to the VSNS pin without capacitor to disable the integrator
function.
DH
11
O
High-side MOSFET gate driver output.
DL
10
O
Low-side MOSFET gate driver output.
EN
14
I
Enable pin. 3.3-V I/O level, 100 ns de-bounce. Short to GND to disable the device.
GND
7
–
Device analog ground; Connect to a quiet point on the system GND plane
GSNS
3
I
Voltage sense return tied directly to the GND sense point of the load. Short to GND if remote sense is not used.
MODE
15
I
Connect a resistor to GND to configure switching frequency, control mode and current sense scheme. (See
Table 2)
PGND
8
–
Synchronous low-side MOSFET gate driver return. Also serve as the current sensing input (+). Connect to the
GND pin as close as possible to the device.
PGOOD
16
O
Powergood signal open drain output. PGOOD goes high when the output voltage is within the target range.
REFIN
2
I
Output voltage setting pin. See the VREF and REFIN, Output Voltage section.
SW
12
TRIP
6
VSNS
VREF
I/O High-side MOSFET gate driver return. RDS(on) current sensing input (–) when using RDS(on) current sensing.
I
Current sense comparator input (-) for resistor current sensing. Or overcurrent threshold setting pin for RDS(on)
current sensing if connected to GND through an OCL setting resistor. For RDS(on) current sensing operation, 10
μA at room temperature, TC=4700ppm/°C, is sourced to set the trip voltage.
4
I
Voltage sense line tied directly to the load voltage sense point.
1
O
2.0-V ±0.8% voltage reference output.
V5
9
I
5V power supply input for internal circuits and MOSFET gate drivers.
Thermal
pad
–
–
Thermal pad. Connect directly to system GND plane with multiple vias.
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FUNCTIONAL BLOCK DIAGRAM
VREF
1
Reference
TPS51219
+ UV
VREFIN – 32%
Set_1p05v
VREFIN +8/16%
EN
+
16 PGOOD
Delay
+
GSNS
3
OV
VREFIN + 20%
+
VREFIN – 8/16%
COMP
5
VSNS
4
+
VREFIN
REFIN
PWM
+
OVP
Set_resistor _sensing
UVP
16.7 mA
2
Soft-Start
Set_adj
0.3 V
Control Mode
On-Time
Current Sense
Selection
+
Control Logic
Set_adj
Discharge
+
15 MODE
13 BST
Set_1p05v
VBG
11 DH
2.2 V
25 mV
EN 14
EN
12 SW
8R
10 mA
XCON
tON
OneShot
OC
+
R
+
TRIP
6
7R
NOC
+
R
9
+
V5
10 DL
ZC
Set_resistor _sensing
Discharge
V5OK
8
PGND
5-V UVLO
GND
7
+
4.3 V/3.9 V
EN
UDG-11007
8
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TYPICAL CHARACTERISTICS
10
V5 Supply Current (µA)
800
600
400
200
VV5 = 5 V
VEN = 5 V
No Load
0
−50
0
25
50
75
Junction Temperature (°C)
100
8
6
4
2
0
−50
125
−25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 2. V5 Shutdown Current vs Junction Temperature
16
150
VV5 = 5 V
VTRIP = 0.5 V
UVP/OVP Threshold (%)
12
10
8
6
4
VV5 = 5 V
VREFIN = 0 V
UVP
OVP
140
2
130
120
110
100
90
80
70
60
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
50
−50
125
−25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 3. Current Sense Current vs Junction Temperature
Figure 4. OVP/UVP Threshold vs Junction Temperature
2.020
900
VV5 = 5 V
TA = 27°C
2.010
2.005
2.000
1.995
1.990
RMODE = 1 kΩ
RMODE = 12 kΩ
RMODE = 100 kΩ
RMODE = 200 kΩ
800
Switching Frequency (kHz)
2.015
VREF Voltage (V)
VV5 = 5 V
VEN = 0 V
No Load
Figure 1. V5 Supply Current vs Junction Temperature
14
Trip Source Current (µA)
−25
V5 Shutdown Current (µA)
1000
700
600
500
400
1.985
300
1.980
200
IOUT = 10 A
0
50
100
150
200
250
VREF Current (µA)
300
Figure 5. VREF Load Regulation
Copyright © 2011, Texas Instruments Incorporated
350
400
6
8
10
12
14
16
Input Voltage (V)
18
20
22
Figure 6. Switching Frequency vs Input Voltage
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TYPICAL CHARACTERISTICS
Figure 11 and Figure 12 refer to the application schematic in Figure 33.
800
800
RMODE = 100 kΩ
VIN = 12 V
VOUT = 1.05 V
L = 0.56 µH
600
500
400
300
200
100
0
RMODE = 200 kΩ
VIN = 12 V
VOUT = 1.05 V
L = 0.56 µH
700
Switching Frequency (kHz)
Switching Frequency (kHz)
700
600
500
400
300
200
100
0
2
4
6
8
10
12
14
Output Current (A)
16
18
0
20
0
Figure 7. Switching Frequency vs Load Current
Switching Frequency (kHz)
Switching Frequency (kHz)
600
500
400
300
200
16
18
20
600
500
400
300
RMODE = 12 kΩ
VIN = 12 V
VOUT = 1.05 V
L = 0.36 µH
200
100
0
2
4
6
8
10
12
14
Output Current (A)
16
18
0
20
1.070
1.065
1.060
1.055
1.050
1.045
1.040
RMODE = 1 kΩ
VIN = 12 V
1.035
0
2
4
6
8
10
12
14
1.05−V Output Current (A)
16
18
Figure 11. 1.05-V Output Load Regulation
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0
2
4
6
8
10
12
14
Output Current (A)
16
18
20
Figure 10. Switching Frequency vs Load Current
20
G001
VSNS−GSNS − 1.05−V Output Voltage (V)
Figure 9. Switching Frequency vs Load Current
VSNS−GSNS − 1.05−V Output Voltage (V)
8
10
12
14
Output Current (A)
700
100
10
6
800
RMODE = 1 kΩ
VIN = 12 V
VOUT = 1.05 V
L = 0.45 µH
700
1.030
4
Figure 8. Switching Frequency vs Load Current
800
0
2
1.070
RMODE = 1 kΩ
1.065
1.060
1.055
1.050
1.045
1.040
IOUT = 0 A
IOUT = 10 A
1.035
1.030
6
8
10
12
14
16
Input Voltage (V)
18
20
22
G001
Figure 12. 1.05-V Output Line Regulation
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TYPICAL CHARACTERISTICS
VSNS−GSNS − 1.00−V Output Voltage (V)
Figure 11, Figure 12, and Figure 13 refer to the application schematic in Figure 33.
Figure 14, Figure 15 and Figure 16, refer to the application schematic in Figure 33 except the parameters
of L1 (0.56 µH), C7 (2 × 330 µF) and Q3 (not used).
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 8 V
VIN = 12 V
VIN = 20 V
10
RMODE = 1 kΩ
0
0.001
0.01
0.1
1
1.05−V Output Current (A)
10
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.980
2
4
6
1.00−V Output Current (A)
8
10
G001
Figure 14. 1.00-V Output Load Regulation
1.020
100
RMODE = 1 kΩ
1.015
90
1.010
80
70
1.005
Efficiency (%)
VSNS−GSNS − 1.00−V Output Voltage (V)
0
100
Figure 13. 1.05-V Output Efficiency
1.000
0.995
0.990
60
50
40
30
IOUT = 0 A
IOUT = 10 A
0.985
0.980
RMODE = 1 kΩ
VIN = 12 V
0.985
6
8
10
12
14
16
Input Voltage (V)
18
20
Figure 15. 1.00-V Output Line Regulation
Copyright © 2011, Texas Instruments Incorporated
20
VIN = 8 V
VIN = 12 V
VIN = 20 V
10
22
G001
RMODE = 1 kΩ
0
0.001
0.01
0.1
1
1.00−V Output Current (A)
10
100
Figure 16. 1.00-V Output Efficiency
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TYPICAL CHARACTERISTICS
VIN=20 V
VIN=20 V
VSNS-GSNS (20 mV/div)
offset: 1.00 V
VSNS-GSNS (20 mV/div)
offset: 1.05 V
IOUT (8 A/div)
offset: 6 A
IOUT (8 A/div)
COUT = 2 x 330 µF(Bulk) + 12 x 22 µF(MLCC)
COUT = 5 x 330 µF(Bulk) + 12 x 22 µF(MLCC)
Figure 17. 1.05-V Load Transient Response
EN (5 V/div)
IOUT = 15A
Figure 18. 1.00-V Load Transient Response
IOUT = 0 A
VSNS-GSNS
(500mV/div)
EN (5 V/div)
VSNS-GSNS
(500mV/div)
0.5-V Pre-biased
PGOOD (5V/div)
Time (400 µs/div)
Figure 19. 1.05-V Startup Waveforms
12
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PGOOD (5V/div)
Time (400 µs/div)
Figure 20. 1.05-V Startup Waveforms (0.5-V Pre-Biased)
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TYPICAL CHARACTERISTICS
Figure 22 refers to application schematic of Figure 33.
IOUT = 0 A
EN (5 V/div)
VSNS-GSNS
(500mV/div)
PGOOD (5V/div)
Time (100 ms/div)
80
180
60
135
40
90
20
45
0
0
−20
−45
−40
−60
−80
100
Phase (°)
Gain (dB)
Figure 21. 1.05-V Soft-stop Waveforms
−90
Gain
Phase
1000
VIN =12 V
IOUT =15 A
RMODE =1 kΩ
10000
Frequency (Hz)
−135
100000
−180
1000000
Figure 22. Bode Plot, VOUT=1.05 V
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APPLICATION INFORMATION
Swtich Mode Power Supply Control
The TPS51219 is a high performance, single-synchronous step-down controller with differential voltage feedback.
The TPS51219 realizes accurate regulation at the specific load point over wide load range with the combination
of three functions.
• 2-V Reference with 0.8% Tolerance. Internal voltage divider provides precise reference (See Table 1 in the
VREF and REFIN, Output Voltage section). A value of 0.1µF is recommended as the decoupling capacitance
between VREF and GSNS pins.
• Integrator. Feedback capacitance connected from the output (COMP pin) to the input (VSNS pin) of the error
amplifier comprises integrator, which increases gain at DC to low frequency region and improves load
regulation of the output voltage. 10nF is recommended as the capacitance between VSNS and COMP pins.
• Differential remote sensing. Differential feedback provides precise output voltage control at the point of
load. Connect VSNS and GSNS directly to output voltage sense point and ground return point at the load
device, respectively. Short GSNS to GND if remote sense is not used.
The TPS51219 supports two control architectures, D-CAP™ mode and D-CAP2™ mode. Both control modes do
not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2™ mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive
on-time control scheme is used to achieve pseudo-constant frequency. The TPS51219 adjusts the on-time (tON)
to be inversely proportional to the input voltage (VIN) and proportional to the SMPS output voltage (VOUT). The
switching frequency remains nearly constant over the variation of input voltage at the steady-state condition.
Control modes and switching frequency are selected by the MODE pin described in Table 2.
VREF and REFIN, Output Voltage
The device provides a 2.0-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-µA current
capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of 0.1-µF or
larger should be attached close to the VREF terminal.
The SMPS output voltage is defined by REFIN voltage, within the range between 0.5 V and 2.0 V, programmed
by the resister-divider connected between VREF and GSNS. (See Figure 23 and External Components Selection
section.) A few nano-farads of capacitance from REFIN to GSNS is recommended for stable operation. A voltage
divider and a filter capacitor to this pin should be referenced to GSNS. Fixed output voltage can be set as shown
in Table 1.
TPS51219
XXXX
Table 1. Output Voltage Selection
VREF
1
REFIN VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.3
1.05
R1
2
REFIN
0,1 mF
GSNS
1.00
Resistor Divider
Adjustable
R2
10 nF
XXXX
3
GSNS
XXXX
UDG-11042
Figure 23. Voltage Reference Connections
XXXX
XXXX
XXXX
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Soft-Start and Powergood
Provide a voltage supply to VIN and V5 before asserting EN to high. TPS51219 provides integrated soft-start
functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference
voltage ramping up. Figure 24 shows the start-up waveforms. The switching regulator waits for 400μs after EN
assertion. The MODE pin voltage is read in this period. A typical VOUT ramp up duration is 700 μs.
THe TPS51219 has a powergood open-drain output that indicates the VOUT voltage is within the target range.
The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay
for assertion (low to high), and ±16% (typ) and 2-µs delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after EN is asserted to high. The time constant, which is composed of the
REFIN capacitor and a resistor divider, needs to be short enough to reach the target value before PGOOD
comparator enabled.
EN
VREF
VOUT
PGOOD
400 ms
700 ms
1.4 ms
UDG-11008
Figure 24. Typical Start-up Waveforms
MODE Pin Configuration
The TPS51219 reads the MODE pin voltage when the EN signal is raised high and stores the status in a
register. A 16.7-μA current is sourced from the MODE pin during this time to read the voltage across the resistor
connected between the pin and GND. Table 2 shows resistor values, corresponding control mode, switching
frequency and current sense operation configurations.
Table 2. MODE Selection
MODE NO.
RESISTANCE BETWEEN
MODE AND GND (kΩ)
7
200
400
6
100
300
5
68
4
47
400
3
33
500
2
22
1
12
0
1
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CONTROL
MODE
D-CAP™
D-CAP2™
SWITCHING
FREQUENCY (kHz)
300
670
670
500
CURRENT SENSE
OPERATION
RDS(on)
Resistor
Resistor
RDS(on)
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D-CAP™ Mode
Figure 25 shows a simplified model of D-CAP™ mode architecture in the TPS51219.
C1
VIN
COMP
5
VSNS
DH
gM=130 mS
4
11
VOUT
+
+
Lx
PWM
REFIN
Control
Logic
and
Driver
2
R1 VREF
RLOAD
ESR
DL
1
+
2.0 V
10
COUT
R2
UDG-11009
Figure 25. Simplified D-CAP™ Model
The transconductance amplifier and the capacitance C1 configure an integrator. The VSNS voltage is compared
with REFIN voltage. Ripple voltage generated by ESR of the output capacitance is fed back through the C1 so
that C1 should be properly connected to the positive terminal of output capacitor, not at the remote point of load.
The PWM comparator creates a set signal to turn on the high-side MOSFET each cycle. The D-CAP™ mode
offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop
calculation and external components. However, it does require sufficient amount of ESR that represents inductor
current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or
specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0, is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f0, for example one decade low, as described in Equation 2.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
3
where
•
•
•
ESR is the effective series resistance of the output capacitor
COUT is the capacitance of the output capacitor
fSW is the switching frequency
(1)
f
gM
£ 0
2p ´ C1 10
where
•
16
gM is transconductance of the error amplifier (typically 130 µS)
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Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VSNS ripple voltage. Figure 26
shows, in the same noise condition, that jitter is improved by making the slope angle larger.
VVSNS
Slope (1)
Jitter
(2)
Slope (2)
Jitter
20 mV
(1)
VREFIN
VREFIN +Noise
tON
tOFF
Time
UDG-11010
Figure 26. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 26 and Equation 3.
VOUT ´ ESR
³ 20mV
fSW ´ L X
where
•
•
VOUT is the SMPS output voltage
LX is the inductance
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D-CAP2™ Mode Operation
Figure 27 shows simplified model of D-CAP2™ architecture.
VIN
CC1
VSNS
SW
RC1
4
12
CC2
C1
RC2
DH
11
COMP
G
5
+
–
+
+
PWM
Comparator
REFIN
LX
Control
Logic
and
Driver
VOUT
DL
10
ESR
2
RLOAD
COUT
R1 VREF
1
+
R2
2.0 V
TPS51219
UDG-11011
Figure 27. Simplified Modulator Using D-CAP2™ Mode
When the TPS51219 operates in D-CAP2™ mode, connect the COMP and VSNS pins as shown in Figure 27.
The transconductance amplifier and the capacitance C1 configures the integrator. The D-CAP2™ mode in the
TPS51219 includes an internal feedback network enabling the use of very low ESR　output capacitor(s) such as
multi-layer ceramic capacitors (MLCC). The role of the internal network is to sense the ripple　component of the
inductor current information and then combine it with the voltage feedback signal.
Using RC1=RC2≡RC and CC1=CC2≡CC, 0-dB frequency of the D-CAP2™ mode is given by Equation 4. f0 is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f0, for example one decade low, as described in Equation 5.
RC ´ CC
f
£ SW
f0 =
2p ´ G ´ L X ´ COUT
3
where
•
G is gain of the amplifier which amplifies the ripple current information generated by the compensation
circuit
f
gM
£ 0
2p ´ C1 10
(4)
(5)
The typical G value is 0.25, and typical RCCC time constant values for 500 kHz and 670 kHz operation are 32 μs
and 23 μs, respectively.
For example, when fSW = 500 kHz and LX=0.45 μH, COUT should be larger than 272 μF. At the selection of
capacitor, pay attention to its characteristics. For MLCC use X5R or better dielectric and take into account
derating of the capacitance by both DC bias and AC bias. When derating by DC bias and AC bias are 80% and
50%, respectively, the effective derating is 40% because 0.8 x 0.5 = 0.4. The capacitance of specialty polymer
capacitors may change depending on the operating frequency. Consult capacitor manufacturers for specific
characteristics.
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Light-Load Operation
In auto-skip mode, the TPS51219 SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 6 shows the boundary load condition of this skip
mode and continuous conduction operation.
ILOAD(LL) =
(VIN - VOUT ) ´ VOUT ´
2 ´ LX
VIN
1
fSW
(6)
Current Sensing
In order to provide both cost effective solution and good accuracy, TPS51219 supports both of MOSFET RDS(on)
sensing and external resistor sensing. For RDS(on) sensing scheme, TRIP pin should be connected to GND
through the trip voltage setting resistor, RTRIP. In this scheme, TRIP terminal sources 10µA of ITRIP current and
the trip level is set to 1/8 of the voltage across the RTRIP. The inductor current is monitored by the voltage
between the PGND pin and the SW pin so that the SW pin is connected to the drain terminal of the low-side
MOSFET. ITRIP has a 4700ppm/°C temperature slope to compensate the temperature dependency of the RDS(on).
For resistor sensing scheme, an appropriate current sensing resistor should be connected between the source
terminal of the low-side MOSFET and PGND. The TRIP pin is connected to the MOSFET source terminal node.
The inductor current is monitored by the voltage between PGND pin and TRIP pin. In either scheme, PGND is
used as the positive current sensing node so that PGND should be connected to the proper current sensing
device, i.e. the sense resistor or the source terminal of the low-side MOSFET.
Overcurrent Protection
TPS51219 has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state and the controller maintains the off-state when the inductor current is larger than the overcurrent trip
level. The trip level and current sense operation are determined by the MODE pin setting and TRIP pin
connection (See Table 2 and Current Sensing section). For RDS(on) sensing scheme, TRIP terminal sources
10 µA and the trip level is set to 1/8 of the voltage across this RTRIP　resistor. The overcurrent trip level, VOCTRIP,
is determined by Equation 7.
æI
ö
VOCTRIP = RTRIP ´ ç TRIP ÷
8
è
ø
(7)
For a resistor sensing scheme, the trip level, VOCTRIP, is a fixed value of 25 mV.
Because the comparison is made during the off-state, VOCTRIP sets the valley level of the inductor current. The
load current OCL level, IOCL, can be calculated by considering the inductor ripple current.
Overcurrent limiting using RDS(on) sensing is shown in Equation 8.
æV
IOCL = ç OCTRIP
ç RDS(on )
è
ö I
æ
÷ + IND(ripple) = ç VOCTRIP
÷
ç RDS(on )
2
ø
è
ö 1 V -V
VOUT
OUT
÷ + ´ IN
´
÷ 2
LX
fSW ´ VIN
ø
where
•
IIND(ripple) is inductor ripple current
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Overcurrent limiting using resistor sensing is shown in Equation 9.
æ 25mV ö IIND(ripple) æ 25mV ö 1 VIN - VOUT
VOUT
IOCL = ç
=ç
´
÷+
÷+ ´
2
LX
fSW ´ VIN
è REXT ø
è REXT ø 2
where
•
•
IIND(ripple) is inductor ripple current
REXT is the external current sense resistance
(9)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
Overvoltage and Undervoltage Protection
The TPS51219 sets the overvoltage protection (OVP) when VSNS voltage reaches a level 20% (typ) higher than
the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V. This
usually turns off DH and forces DL to be on. When the inductor current begins to flow through the low-side
MOSFET and reaches the negative OCL, DL is turned off and DH is turned on, for a minimum on-time.
After the minimum on-time expires, DH is turned off and DL is turned on again. This action minimizes the output
node undershoot due to LC resonance. When the VSNS reaches 0 V, the driver output is latched as DH off, DL
on.
The undervoltage protection (UVP) latch is set when the VSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DH low and DL low and discharges
the VOUT. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.
To release the OVP and UVP latches, toggle EN or adjust the V5 voltage down and up beyond the undervoltage
lockout threshold.
V5 Undervoltage Lockout Protection
TPS51219 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5 voltage is lower
than UVLO threshold voltage, typically 3.9 V, VOUT is shut off. This is a non-latch protection.
Thermal Shutdown
TPS51219 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ),
VOUT is shut off. The state of VOUT is open at thermal shutdown. This is a non-latch protection and the operation
is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
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External Components Selection
The external components selection is simple in D-CAP™ mode.
1. DETERMINE THE VALUE OF R1 AND R2
The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in Figure 25.
R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin and GSNS.
Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 10.
R1
R2 =
æ
ö
ç
÷
ç
÷
2.0
ç
÷ -1
æ IIND(ripple ) ´ ESR ö ÷
ç
÷÷
ç VOUT - ç
ç
÷÷
2
ç
è
øø
è
(10)
2. CHOOSE THE INDUCTOR
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum output
current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps
stable operation.
LX =
(V
IN(max ) - VOUT
1
)´ V
´
IIND(ripple ) ´ fSW
OUT
VIN(max )
(V
IN(max ) - VOUT
3
=
)´ V
OUT
´
IO(max ) ´ fSW
VIN(max )
(11)
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in Equation 12.
(
IIND(peak ) =
)
VIN(max ) - VOUT ´ VOUT
VTRIP
1
+
´
8 ´ RDS(on ) L X ´ fSW
VIN(max )
(12)
3. CHOOSE THE OCL SETTING RESISTANCE
RTRIP for RDS(on) Sensing
Combining Equation 7 and Equation 8, RTRIP can be obtained using Equation 13.
RTRIP
æ
ö
æ (V - VOUT ) ö
VOUT
÷ ´ RDS(on)
8 ´ ç IOCL - ç IN
÷÷ ´
ç
ç
÷
è (2 ´ L X ) ø (fSW ´ VIN ) ø
è
=
ITRIP
(13)
REXT for Resistor Setting
Combining Equation 7 and Equation 9, REXT can be obtained using Equation 14.
25mV
REXT =
æ V - VOUT ö
VOUT
IOCL - ç IN
÷´
è 2 ´ L X ø fSW ´ VIN
(14)
For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance (ESL) of resistor, this filter value is calculated using Equation 15.
ESL
CX ´ R X =
REXT
(15)
The time-constant of CX and RX should match the one of ESL and REXT. Even when CX is not used, an RX of
100 Ω is recommended for noise suppression.
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Lx
Lx
TPS51219
TPS51219
IOUT
DL
10
10
TRIP
TRIP
Rx
6
+
REXT
25 mV
(typ)
RX
6
+
+
IOUT
DL
+
Cx
25 mV
(typ)
REXT
Cx
RXC
ESL
UDG-11043
Figure 28. Resistor Sensing with Compensation
ESL
UDG-11044
Figure 29. Adjustment of Overcurrent Limitation in
Resistor Sensing
A voltage divider can be configured to adjust for overcurrent limitation, as described in Figure 29. For RX, RXC
and CX can be calculated as shown in Equation 16, and the overcurrent limitation value can be calculated as
shown in Equation 17.
ESL
C X ´ R X R XC =
REXT
(16)
(
)
æ 25mV ö R X + R XC æ VIN - VOUT ö
VOUT
IOCL = ç
+ç
÷+
÷´
R XC
è REXT ø
è 2 ´ L X ø fSW ´ VIN
Therefore, REXT can be obtained using Equation 18.
æ (R X + R XC ) ö
25mV
REXT =
´ç
÷
ç
÷
R XC
æ (VIN - VOUT ) ö
VOUT
è
ø
IOCL - ç
´
÷
ç
÷ fSW ´ VIN
2 ´ LX
è
ø
(17)
(18)
4. CHOOSE THE OUTPUT CAPACITORS
D-CAP™ Mode
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine the ESR
value to meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 19
and Equation 20.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
3
(19)
f
gM
£ 0
2p ´ C1 10
where
•
•
gM is 130 µS (typ)
C1 is the capacitance connected between the VSNS and COMP pins
VOUT ´ ESR
³ 20mV
fSW ´ Lx
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D-CAP2™ Mode
Determine output capacitance to meet small signal stability as shown in Equation 22 and Equation 23.
(RC ´ CC )
f
£ SW
2p ´ G ´ L X ´ COUT
3
where
•
G = 0.25
(22)
f
gM
£ 0
2p ´ C1 10
where
•
the RC × CC time constant is 32 µs for operation at 500 kHz. (23 µs for operation at 670 kHz)
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Layout Considerations
Certain issues must be considered before designing a layout using the TPS51219.
VREF
VIN
TPS51219
1
REFIN
0.1 mF
V5
2
10 nF
#1
VOUT
9
2.2 mF
GSNS
#2
GSNS
DL
3
10
VSNS
PGND
VSNS
#3
4
8
10 nF
COMP
5
TRIP
6
MODE
15
GND PwrPad
7
UDG-11012
Figure 30. DC/DC Converter Ground System
•
•
•
•
24
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
All sensitive analog traces and components such as VSNS, COMP, MODE, REFIN, VREF and TRIP should
be placed away from high-voltage switching nodes such as SW, DH, DL or BST to avoid coupling. Use
internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– Loop #1. The most important loop to minimize the area of is the path from the VIN capacitor(s) through the
high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of
the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop
#1 of Figure 30)
– Loop #2. The second important loop is the path from the low-side MOSFET through inductor and VOUT
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of
Figure 30)
– Loop #3. The third important loop is of gate driving system for the low-side MOSFET. To turn on the
low-side MOSFET, high current flows from V5 capacitor through gate driver and the low-side MOSFET,
and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current
flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the
low-side MOSFET through ground. Connect negative node of V5 capacitor, source of the low-side
MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 30)
Connect the PGND and GND pins directly at the device.
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Copyright © 2011, Texas Instruments Incorporated
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
Connect VSNS directly to the output voltage sense point at the load device. Connect GSNS to ground return
points at the load device. Insert a 10-Ω, 1-nF, R-C filter between the sense point and the VSNS pin where the
COMP capacitance is connected as shown in Case 1 (Figure 31). When the COMP pin capacitance is
connected to output bulk capacitance, connect the R-C filter in series to both the VSNS pin and the COMP
capacitance as shown in Case 2 (Figure 32).
BST
•
SW
TPS51219
DH
VSNS
V5
C
GND
R
PGND
DL
COMP
GSNS
5V
C
C
GND
VIAs to inner
ground layer
BST
Figure 31. Case 1: COMP Pin Capacitance Connected to VSNS
SW
TPS51219
DH
V5
C
PGND
VSNS
R
GND
DL
COMP
GSNS
5V
C
C
R
To output bulk
capacitance
C
GND
VIAs to inner
ground layer
Figure 32. Case 2: COMP Pin Capacitance Connected to Output Bulk Capacitance
•
•
Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as
close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node.
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
25
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
•
www.ti.com
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate
heat.　Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side
ground　plane(s) should be used to help dissipation.
•
•
TPS51219 1.05-V/20-A, D-CAP2™ 500-kHz, RDS(on) Sensing Application Circuit
V5IN
4.5V to 5.5V
R2
1k
R1
100k
VIN
EN
PwPd
16
3.3V
PGOOD
15
MODE
14
EN
13
BST
17
R3
0
1
VREF
REFIN
3
GSNS
U1
TPS51219
2
VSNS
R6
10
GND
PGND
0.1uF
/50V
4x10uF
/25V
8V to 20V
1-3
R4
0
12
SW
11
DH
DL 10
L1
0.45uH
Vout
1.05V/20A
9
5
C4
2.2uF
4
1-3
5
4
1-3
C7
5x330uF
C8
12x22uF
8
6
5
4
Q2
FDMS8670AS
C2
0.01uF
C6
5
C3
0.1uF
V5
COMP
TRIP
4
7
C1
0.1uF
Q1
FDMS8680
C5
Q3
FDMS8670AS
Vout_GND
R5
36k
C9
1nF
Figure 33. 1.05-V/20-A, D-CAP2™ 500-kHz, RDS(on) Sensing
Table 3. 1.05-V/20-A, D-CAP2™ 500-kHz, RDS(on) Sensing, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURE
PART NUMBER
Taiyo Yuden
TMK325BJ106MM
C6
4
10 µF, 25 V
C7
5
330 µF, 2 V, 6 mΩ
C8
12
22 µF, 6.3 V
L1
1
0.45 µH, 17 A, 1.1 mΩ
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2, Q3
2
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
26
Submit Documentation Feedback
Panasonic
EEFSX0D331XE
Murata
GRM21BB30J226ME38
Panasonic
ETQP4LR45XFC
Copyright © 2011, Texas Instruments Incorporated
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
1.05-V/20-A, D-CAP™ 400-kHz, RDS(on) Sensing Application Circuit
V5IN
4.5V to 5.5V
R2
200k
R1
100k
VIN
EN
1
VREF
REFIN
GSNS
VSNS
2
3
C1
0.1uF
13
14
4x10uF
/25V
5
4
1-3
L1
0.45uH
11
Vout
1.05V/20A
10
9
C4
2.2uF
4
1-3
C7
5x330uF
5
5
4
1-3
C8
12x22uF
8
7
6
5
0.1uF
/50V
8V to 20V
12
Q2
FDMS8670AS
C2
0.01uF
C9
1nF
C6
R4
0
SW
DH
DL
V5
U1
TPS51219
Q1
FDMS8680
C3
0.1uF
COMP
TRIP
GND
PGND
4
15
16
PwPd
3.3V
PGOOD
MODE
EN
BST
17
R3
0
C5
Q3
FDMS8670AS
Vout_GND
R5
36k
R6
10
R7
10
C10
1nF
Figure 34. 1.05-V/20-A, D-CAP™ 400-kHz, RDS(on) Sensing
Table 4. 1.05-V/20-A, D-CAP™ 400-kHz, RDS(on) Sensing, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURE
PART NUMBER
Taiyo Yuden
TMK325BJ106MM
C6
4
10 µF, 25 V
C7
5
330 µF, 2.5 V, 18 mΩ
Sanyo
2R5TPE330MI
C8
12
22 µF, 6.3 V
Murata
GRM21BB30J226ME38
L1
1
0.45 µH, 17 A, 1.1 mΩ
Panasonic
ETQP4LR45XFC
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2,Q3
2
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
27
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
TPS51219 1.00-V/10.4-A, D-CAP2™ 500-kHz, Resistor Sensing Application Circuit
V5IN
4.5V to 5.5V
R2
33k
R1
100k
VIN
EN
3
C1
0.1uF
VREF
REFIN
GSNS
VSNS
13
14
U1
TPS51219
0.1uF
/50V
4x10uF
/25V
8V to 20V
5
4
1-3
SW
DH
DL
V5
12
L1
0.45uH
11
Vout
1.00V/10.4A
10
9
5
C7
C4
2.2uF
Q2
FDMS8670AS
4
C8
1-3
2x330uF
12x22uF
8
7
6
5
C6
R4
0
COMP
TRIP
GND
PGND
4
15
16
PwPd
1
2
Q1
FDMS8680
C3
0.1uF
PGOOD
MODE
EN
BST
17
R3
0
C5
R7
100
C2
0.01uF
C10
0.01uF
Vout_GND
R5
3m
R6
10
C9
1nF
Figure 35. 1.00-V/10.4-A, D-CAP2™ 500-kHz, Resistor Sensing
Table 5. 1.00-V/10.4-A, D-CAP2™ 500-kHz, Resistor Sensing, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
C6
4
10 µF, 25 V
C7
2
330 µF, 2 V, 6 mΩ
C8
12
22 µF, 6.3 V
L1
1
0.45 µH, 17 A, 1.1 mΩ
Q1
1
Q2
R5
28
MANUFACTURE
PART NUMBER
Taiyo Yuden
TMK325BJ106MM
Panasonic
EEFSX0D331XE
Murata
GRM21BB30J226ME38
Panasonic
ETQP4LR45XFC
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
1
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
1
3 mΩ, 1 W
KOA
TLR2HDTD3L00F
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
TPS51219
SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011
www.ti.com
TPS51219 1.00-V/10.4-A, D-CAP™ 400-kHz, Resistor Sensing Application Circuit
V5IN
4.5V to 5.5V
R2
47k
R1
100k
VIN
EN
3
4
14
13
16
U1
TPS51219
C10
1nF
R7
10
7
0.1uF
/50V
4x10uF
/25V
8V to 20V
5
4
1-3
SW
DH
DL
V5
12
L1
0.45uH
11
Vout
1.00V/10.4A
10
9
5
C4
2.2uF
Q2
FDMS8670AS
4
C7
1-3
C8
2x330uF
12x22uF
8
6
5
C2
0.01uF
C6
R4
0
COMP
TRIP
GND
PGND
C1
0.1uF
VREF
REFIN
GSNS
VSNS
Q1
FDMS8680
C3
0.1uF
PGOOD
MODE
EN
BST
PwPd
1
2
15
17
R3
0
C5
R6
100
C9
0.01uF
Vout_GND
R5
3m
R8
10
C11
1nF
Figure 36. 1.00-V/10.4-A, D-CAP™ 400-kHz, Resistor Sensing
Table 6. 1.00-V/10.4-A, D-CAP™ 400-kHz, Resistor Sensing, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURE
PART NUMBER
Taiyo Yuden
TMK325BJ106MM
Panasonic
EEFSX0D331ER
Murata
GRM21BB30J226ME38
Panasonic
ETQP4LR45XFC
C6
4
10 µF, 25 V
C7
2
330 µF, 2 V, 9 mΩ
C8
12
22 µF, 6.3 V
L1
1
0.45 µH, 17 A, 1.1 mΩ
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2
1
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
R5
1
3 mΩ, 1 W
KOA
TLR2HDTD3L00F
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
29
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS51219RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS51219RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS51219RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS51219RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS51219RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS51219RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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