TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 800-mA SYNCHRONOUS STEP-DOWN CONVERTER Check for Samples: TPS62052, TPS62054, TPS62056, TPS62050, TPS62051 FEATURES DESCRIPTION • The TPS6205x devices are a family of high-efficiency synchronous step-down dc/dc converters ideally suited for systems powered from a 1-cell or 2-cell LiIon battery or from a 3-cell to 5-cell NiCd, NiMH, or alkaline battery. 1 2 • • • • • • • • • • • High-Efficiency Synchronous Step-Down Converter With up to 95% Efficiency 12-µA Quiescent Current (Typ) 2.7-V to 10-V Operating Input Voltage Range Adjustable Output Voltage Range From 0.7 V to 6 V Fixed Output Voltage Options Available in 1.5 V, 1.8 V, and 3.3 V Synchronizable to External Clock Signal up to 1.2 MHz High Efficiency Over a Wide Load Current Range in Power-Save Mode 100% Maximum Duty Cycle for Lowest Dropout Low Noise Operation in Forced Fixed Frequency PWM Operation Mode Internal Softstart Overtemperature and Overcurrent Protected Available in 10-Pin Microsmall Outline Package MSOP The TPS62050 is a synchronous PWM converter with integrated N-channel and P-channel power MOSFET switches. Synchronous rectification increases efficiency and reduces external component count. To achieve highest efficiency over a wide load current range, the converter enters a power-saving pulsefrequency modulation (PFM) mode at light load currents. Operating frequency is typically 850 kHz, allowing the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 600 kHz to 1.2 MHz. For low noise operation, the converter can be programmed into forced-fixed frequency in PWM mode. In shutdown mode, the current consumption is reduced to less than 2 µA. The TPS6205x is available in the 10-pin (DGS) micro-small outline package (MSOP) and operates over an free air temperature range of –40°C to 85°C. APPLICATIONS • • • • Cellular Phones Organizers, PDAs, and Handheld PCs Low Power DSP Supply Digital Cameras and Hard Disks TYPICAL APPLICATION CIRCUIT VI = 3.3 V to 10 V 1 8 VIN SW EN FB TPS62050 9 L1 = 10 µH EFFICIENCY vs OUTPUT CURRENT VO = 1.5 V / 800 mA 100 90 5 80 TPS62052 6 70 PG LBI 7 3 Co = 22 µF 2 SYNC GND 4 LBO PGND 10 Efficiency – % Ci = 10 µF 60 50 40 30 20 10 0 0.01 VI = 7.2 V, VO = 5 V, SYNC = L 0.1 1 10 100 1k IO – Output Current – mA 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MATHCAD is a registered trademark of Mathsoft Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2011, Texas Instruments Incorporated TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Package/Ordering Information PACKAGED DEVICES OUTPUT VOLTAGE LBI/LBO FUNCTIONALITY PACKAGE MARKING TPS62050DGS Adjustable 0.7 V to 6 V Standard BFM TPS62051DGS Adjustable 0.7 V to 6 V Enhanced BGB TPS62052DGS 1.5 V Standard BGC TPS62054DGS 1.8 V Standard BGE TPS62056DGS 3.3 V Standard BGG PLASTIC MSOP (1) (DGS) (1) The DGS packages are available taped and reeled. Add an R suffix to the device type (i.e., TPS62050DGSR) to order quantities of 2500 devices per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS6205x Supply voltage, VI –0.3 V to 11 V Voltage at EN, SYNC –0.3 V to VI Voltage at LBI, FB, LBO, PG –0.3 V to 7 V –0.3 V to 11 V (2) Voltage at SW Output current, IO 850 mA Maximum junction temperature, TJ 150°C Operating free-air temperature range, TA –40°C to 85°C Storage temperature range, Tstg –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) 300°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The voltage at the SW pin is sampled in PFM mode 15 µs after the PMOS has switched off. During this time the voltage at SW is limited to 7 V maximum. Therefore, the output voltage of the converter is limited to 7 V maximum. PACKAGE DISSIPATION RATING (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR TA ≤ 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 10-PIN MSOP (1) 555 mW 5.56 mW/°C 305 mW 221 mW The thermal resistance junction to ambient soldered onto a PCB of the 10-pin MSOP is 180°C/W. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage at VI 2.7 Voltage at PG, LBO Operating junction temperature 2 MAX 10 6 Maximum output current (1) NOM -40 UNIT V V 800 (1) mA 125 °C Assuming no thermal limitation Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS VI = 7.2 V, VO = 3.3 V, IO = 300 mA, EN = VI, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range I(Q) Operating quiescent current I(SD) Shutdown current IQ(LBI) Quiescent current with enhanced LBI comparator version. 10 V IO = 0 mA, SYNC = GND, VI = 7.2 V 2.7 12 20 µA EN = GND 1.5 5 EN = GND, TA=25°C 1.5 3 EN = VI, LBI=GND, TPS62051 only 5 µA µA ENABLE VIH EN high level input voltage VIL EN low level input voltage 1.3 V 0.3 EN trip point hysteresis 100 Ilkg EN input leakage current EN = GND or VIN, VI = 7.2 V I(EN) EN input current 0.6 V ≤ V(EN)≤ 4 V V(UVLO) Undervoltage lockout threshold 0.01 V mV 0.2 µA 2 µA 1.6 V POWER SWITCH rDS(on) rDS(on) P-channel MOSFET on-resistance VI ≥ 5.4 V; IO = 300 mA 400 650 VI = 2.7 V; IO = 300 mA 600 850 1 µA 1200 1400 mA VI ≥ 5.4 V; IO = 300 mA 300 450 VI = 2.7 V; IO = 300 mA 450 550 P-channel MOSFET leakage current VDS = 10 V P-channel MOSFET current limit VI = 7.2V, VO = 3.3 V N-channel MOSFET on-resistance N-channel MOSFET leakage current 1000 VDS = 6 V 1 mΩ mΩ µA POWER GOOD OUTPUT, LBI, LBO V(PG) Power good trip voltage Vml -2% Power good delay time VOL VO ramping positive 50 VO ramping negative 200 PG, LBO output low voltage V(FB) = 0.8 x VO nominal, I(sink) = 1 mA PG, LBO output leakage current V(FB) = VO nominal, V(LBI) = VI 0.01 Minimum supply voltage for valid power good, LBO signal V(LBI) Low battery input trip voltage µs 0.3 V 0.25 µA 2.3 Input voltage falling V 1.21 Low battery input trip point accuracy V(LBI,HY V V 1.5% Low battery input hysteresis 15 mV S) Ilkg(LBI) LBI leakage current 0.01 0.1 µA 850 1000 kHz 1200 kHz OSCILLATOR fS Oscillator frequency 600 f(SYNC) Synchronization range 600 VIH SYNC high level input voltage 1.5 VIL SYNC low level input voltage Ilkg SYNC input leakage current SYNC = GND or VIN 0.01 SYNC trip point hysteresis Duty cycle of external clock signal Copyright © 2002–2011, Texas Instruments Incorporated V 0.3 V 0.1 µA 100 20% mV 90% Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 3 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VI = 7.2 V, VO = 3.3 V, IO = 300 mA, EN = VI, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Adjustable output voltage range TPS62050, TPS62051 V(FB) Feedback voltage TPS62050, TPS62051 0.5 FB leakage current TPS62050, TPS62051 0.02 Feedback voltage tolerance TPS62050, TPS62051 VI = 2.7 V to 10 V, 0 mA< IO< 600 mA -3% 3% TPS62052 VI = 2.7 V to 10 V, 0 mA< IO< 600 mA -3% 3% TPS62054 VI = 2.7 V to 10 V, 0 mA< IO< 600 mA -3% 3% TPS62056 VI = 3.75 V to 10 V, 0 mA< IO< 600 mA -3% 3% Fixed output voltage tolerance (1) 0.7 Resistance of internal voltage divider for fixed-voltage versions η 700 Line regulation VO = 3.3 V, VI = 5 V to 10 V, IO = 600 mA Load regulation Efficiency 1000 0.1 µA V 1300 kΩ mV/V VI = 7.2 V; IO = 10 mA to 600 mA 0.0045 %/mA VI = 5 V; VO = 3.3 V; IO = 300 mA 93% VI = 3.6 V; VO = 2.5 V; IO = 200 mA 93% 100% Minimum ton time for main switch 100 ns Shutdown temperature 145 °C 1 ms IO = 200 mA, VI = 5 V, Vo = 3.3 V, Co = 22 µF, L = 10 µH Start-up time 4 V 5.2 Duty cycle range for main switches (1) 6.0 The worst case rDS(on) of the PMOS in 100% mode for an input voltage of 3.3 V is 0.75 Ω. This value can be used to determine the minimum input voltage if the output current is less than 600 mA with the TPS62056. Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 PIN ASSIGNMENTS DGS PACKAGE (TOP VIEW) VIN LBO GND PG FB 1 10 2 9 3 8 4 7 5 6 PGND SW EN SYNC LBI Pin Functions PIN NAME NO. I/O DESCRIPTION EN 8 I Enable. A logic high enables the converter, logic low forces the device into shutdown mode, reducing the supply current to less than 2 µA. FB 5 I Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. GND 3 I Ground LBO 2 O Open drain low battery output. Logic low signal indicates a low battery voltage. LBI 6 I Low battery input PG 4 O Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG and VOUT. The output floats when the output voltage is greater than 95% of the nominal value. PGND 10 I Power ground. Connect all power grounds to this pin. SW 9 O Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal power MOSFETS. SYNC 7 I Input for synchronization to the external clock signal. This input can be connected to an external clock or pulled to GND or VI. When an external clock signal is applied, the device synchronizes to this external clock and the device operates in fixed PWM mode. When the pin is pulled to either GND or VI, the internal oscillator is used and the logic level determines if the device operates in fixed PWM or PWM/PFM mode.SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forcedSYNC = LOW (GND): Power-save mode enabled, PFM/PWM mode enabled. VIN 1 I Supply voltage input Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 5 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VI Current Limit Comparator + Undervoltage Lockout Bias Supply – REF SYNC + Soft Start I(AVG) Comparator REF – V I 850 kHz Oscillator V(COMP) P-Channel Power MOSFET Comparator + Saw Tooth Generator S R – Driver Shoot-Through Logic Control Logic Comparator High Comparator Low Comparator High2 SW N-Channel Power MOSFET Load Comparator + SKIP Comparator PG – Error Amp Comparator High + LBO Compensation Comparator Low Comparator Low2 – VREF = 0.5 V – R1 + _ R2 See Note + 1.21 V EN FB LBI PGND GND NOTE: For the adjustable versions (TPS62050, TPS62051), the internal feedback driver is disabled and the FB pin is directly connected to the GM amplifier. 6 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 PARAMETER MEASUREMENT INFORMATION All graphs were generated using the circuit as shown unless otherwise noted. For output voltages other than 5 V, the fixed voltage versions are used. The resistors R1, R2, and the feedforward capacitor (Cff) are removed and the feedback pin is directly connected to the output. WE PD 744 777 10 VI 1 R5 130 kΩ Ci = 10 µF TDK C3216X5R1A106M VIN SW EN FB 5 8 TPS62050 6 R6 100 kΩ 9 L1 = 10 µH 4 LBI PG 7 R3 1M VO = 5 V R4 1M C(ff) = 6.8 pF R1 = 820 kΩ Co = 22 µF 2 SYNC GND 3 LBO R2 = 91 kΩ Taiyo Yuden JMK316BJ226ML PGND 10 Quiescent Current Measurements and Efficiency Were Taken With: R5 = Open, R4 = Open, LBI Connected to GND. Figure 1. Standard Circuit for Adjustable Version Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 7 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS Table 1. TABLE OF GRAPHS FIGURE 1-8 9 10 11 12 13 14 15 Efficiency vs load current Switching frequency vs temperature Output voltage ripple in SKIP mode Output voltage ripple in PWM mode Line transient response in PWM mode Load transient V(switch) and IL (inductor current) in skip mode Start-up timing TPS62050 EFFICIENCY vs LOAD CURRENT TPS62052 EFFICIENCY vs LOAD CURRENT 100 90 VI = 6.5 V Efficiency − % 40 VI = 10 V 30 SYNC = L VO = 5 V TA = 25°C 10 0.1 1 60 40 VI = 7.2 V 10 100 SYNC = L VO = 1.5 V TA = 25°C VI = 10 V 10 0 0.01 1k VI = 10 V 0.1 1 10 100 SYNC = L VO = 1.8 V TA = 25°C 10 0 0.01 1k 0.1 1 10 100 Figure 4. TPS62056 EFFICIENCY vs LOAD CURRENT TPS62050 EFFICIENCY vs LOAD CURRENT TPS62052 EFFICIENCY vs LOAD CURRENT 100 VI = 5.5 V 90 70 Efficiency − % 70 VI = 7.2 V 50 VI = 10 V 30 70 VI = 7.2 V VI = 8.4 V VI = 10 V 40 SYNC = L VO = 3.3 V TA = 25°C 10 1 10 100 IL − Load Current − mA Figure 5. SYNC = H VO = 5 V TA = 25°C 20 10 1k 0 0.01 VI = 5 V 60 VI = 7.2 V 50 40 VI = 10 V 30 30 20 VI = 3.3 V 80 60 50 VI = 2.7 V 90 VI = 6.5 V 80 VI = 5 V 0.1 1 10 100 SYNC = H VO = 1.5 V TA = 25°C 20 10 1k 0 0.01 0.1 1 10 100 1k IL − Load Current − mA IL − Load Current − mA Figure 6. Submit Documentation Feedback 1k IL − Load Current − mA Figure 3. 80 0.1 40 20 100 0 0.01 VI = 7.2 V Figure 2. VI = 3.5 V 40 VI = 5 V 50 IL − Load Current − mA 100 60 VI = 3.3 V 60 30 20 IL − Load Current − mA Efficiency − % VI = 5 V 50 30 20 0 0.01 70 VI = 3.3 V Efficiency − % Efficiency − % VI = 8.4 V VI = 2.7 V 80 70 60 50 90 80 VI = 7.2 V 70 VI = 2.7 V Efficiency − % 80 8 100 100 VI = 5.5 V 90 90 TPS62054 EFFICIENCY vs LOAD CURRENT Figure 7. Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 TPS62054 EFFICIENCY vs LOAD CURRENT TPS62056 EFFICIENCY vs LOAD CURRENT 100 VI = 2.7 V 90 VI = 3.3 V 80 80 VI = 5 V 60 VI = 7.2 V 50 40 VI = 10 V VI = 7.2 V 60 50 40 VI = 10 V 30 30 SYNC = H VO = 1.8 V TA = 25°C 20 10 0.1 1 10 100 10 0 0.01 1k 0.1 1 10 100 3.6 V 880 870 5V 860 850 7.2 V 840 830 820 810 800 1k −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C IL − Load Current − mA IL − Load Current − mA Figure 8. Figure 9. Figure 10. OUTPUT VOLTAGE RIPPLE IN SKIP MODE OUTPUT VOLTAGE RIPPLE IN PWM MODE LINE TRANSIENT RESPONSE IN PWM MODE VI = 7.2 V, VO = 3.3 V VI = 7.2 V VO = 3.3 V IO = 800 mA Output Voltage VI = 4.5 V to 5.5 V to 4.5 V IO = 20 mA Voltage at SW Pin VO 10 mV/div 2 V/div 2 V/div 10 mV/div 10 mV/div Output Voltage Voltage at SW Pin 10 µs/div 1 µs/div 1 µs/div Figure 11. Figure 12. Figure 13. LOAD TRANSIENT V(SWITCH) AND IL (INDUCTOR CURRENT) IN SKIP MODE VI = 5 V VO = 3.3 V START-UP TIMING Voltage at SW Pin 5 V/div EN 5 V/div 50 mV/div Output Voltage 100 500 mv/div 0 0.01 SYNC = H VO = 3.3 V TA = 25°C 20 2.7 V 890 VI = 5 V 70 Efficiency − % 70 900 VI = 3.5 V 90 Switching Frequency − kHz 100 Efficiency − % SWITCHING FREQUENCY vs FREE-AIR TEMPERATURE VI = 5 V IO = 100 mA VO 50 µs/div 5 µs/div Figure 14. Figure 15. Copyright © 2002–2011, Texas Instruments Incorporated II VI = 5 V RL = 2.7 Ω 100 mA/div 100 mA/div Load Step = 60 mA to 540 mA 500 mA/div 1 V/div Inductor Current 200 µs/div Figure 16. Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 9 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION Operation The TPS6205x is a synchronous step-down converter that operates with a 850-kHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents and enters the power-save mode at light load current. During PWM operation the converter uses a unique fast response voltage mode control scheme with input voltage feed forward to achieve good line and load regulation with the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switch is turned on and the inductor current ramps up until the voltage-comparator trips and the control logic turns the switch off. Also the switch is turned off by the current limit comparator in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again, turning off the N-channel rectifier and turning on the P-channel switch. The error amplifier as well as the input voltage determines the rise time of the saw tooth generator; therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a very good line and load transient regulation. Constant Frequency Mode Operation (SYNC = HIGH) In the constant frequency mode, the output voltage is regulated by varying the duty cycle of the PWM signal in the range of 100% to 10%. Connecting the SYNC pin to a voltage greater than 1.5 V forces the converter to operate permanently in the PWM mode even at light or no load currents. The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads (see Figure 17). The N-MOSFET of the devices stays on even when the current into the output drops to zero. This prevents the device from going into discontinuous mode. The device transfers unused energy back to the input. Therefore, there is no ringing at the output that usually occurs in the discontinuous mode. The duty cycle range in constant frequency mode is 100% to 10%. It is possible to switch from forced PWM mode to the power-save mode during operation by pulling the SYNC pin low. The flexible configuration of the SYNC pin during operation of the device allows efficient power management by adjusting the operation of the TPS6205x to the specific system requirements. Power-Save Mode Operation (SYNC = LOW) As the load current decreases, the converter enters the power-save mode operation. During power-save mode the converter operates with reduced switching frequency in PFM and with a minimum quiescent current to maintain high efficiency. Whenever the average output current goes below the skip threshold, the converter enters the power-save mode. The average current depends on the input voltage. It is 100 mA at low input voltages and up to 200 mA with maximum input voltage. The average output current must be below the threshold for at least 32 clock cycles (tcy) to enter the power-save mode. During the power-save mode the output voltage is monitored with a comparator. When the output voltage falls below the comp low threshold set to 0.8% above VO nominal, the P-channel switch turns on. The P-channel switch turns off as the peak switch current of typically 200 mA is reached. The N-channel rectifier turns on and the inductor current ramps down. As the inductor current approaches zero, the N-channel rectifier is turned off and the switch is turned on starting the next pulse. When the output voltage can not be reached with a single pulse, the device continues to switch with its normal operating frequency, until the comparator detects the output voltage to be 1.6% above the nominal output voltage. The converter wakes up again when the output voltage falls below the comp low threshold. This control method reduces the quiescent current to typically to 12 µA and the switching frequency to a minimum achieving the highest converter efficiency. Having these skip current thresholds 0.8% and 1.6% above the nominal output voltage gives a lower absolute voltage drop during a load transient as anticipated with a standard converter operating in this mode. Feedforward Capacitor The feedforward capacitor, C(ff) shown in Figure 21, improves the performance in SKIP mode. The comparator is faster, therefore, there is less voltage ripple at the output in SKIP mode. Use the values listed in Table 2. Larger values decrease stability in fixed frequency PWM mode. If the TPS6205x is only operated in fixed frequency PWM mode, the feedforward capacitor is not needed. 10 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 1.6% 0.8% VO, nominal –1.6% t Figure 17. Power-Save Mode Output Voltage Thresholds The converter enters the fixed frequency PWM mode again as soon as the output voltage falls below the comp low 2 threshold set to 1.6% below VO, nominal. Soft-Start The TPS6205x has an internal soft-start circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage if a battery or a high impedance power source is connected to the input of the TPS6205x. The soft-start is implemented as a digital circuit increasing the switch current in steps of 200 mA, 400 mA, 800 mA and then the typical switch current limit of 1.2 A. Therefore the start-up time mainly depends on the output capacitor and load current. Typical start-up time with a 22-µF output capacitor and a 200-mA load current is 1 ms. 100% Duty Cycle Low Dropout Operation The TPS6205x offers the lowest possible input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range, i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as: V I(min) + V (max) ) I (max) O O ǒrDS(on)(max) ) RLǓ IO(max) = Maximum output current plus inductor ripple current rDS(on)(max) = Maximum P-Channel switch rDS(on) RL = DC resistance of the inductor VO(max) = Nominal output voltage plus maximum output voltage tolerance Enable and Overtemperature Protection Logic low on EN forces the TPS6205x into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than 2 µA in the shutdown mode. When the device is in thermal shutdown, the bandgap is forced to stay on even if the device is set into shutdown by pulling EN to GND. As soon as the temperature drops below the threshold, the device automatically starts again. If an output voltage is present when the device is disabled, which could be an external voltage source or super cap, the reverse leakage current is specified under electrical characteristics. Pulling the enable pin high starts up the TPS6205x with the soft-start as described under the paragraph soft-start. If the EN pin is connected to any voltage other than VI or GND, an increased leakage current of typically 10 µA and up to 20 µA can occur. Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 11 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com VIN VIN 0 µA for VEN < 0.6 V Typically 0.3 µA to 5 µAfor VEN < 4 V 5V Vt = 0.7 V EN Enable to Internal Circuitry Figure 18. Internal Circuit of the ENABLE Pin The EN pin can be used in a pushbutton configuration as shown in Figure 19. The external resistor to GND must be capable of sinking 0.3 µA with a minimum voltage drop of 1.3 V to keep the system enabled when both switches are open. When the ON-button is pressed, the device is enabled and the current through the external resistor keeps the voltage level high to ensure that the device stays on when the ON-button is released. When the OFF-button is pressed, the device is switched off and the current through the external resistor is zero. The device therefore stays off even when the OFF-button is released. VIN TPS6205x ON EN OFF 0.3 µA, min R >1.3 V/0.3 µA Figure 19. Pushbutton Configuration for the EN-Pin Undervoltage Lockout The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. Synchronization If no clock signal is applied, the converter operates with a typical switching frequency of 850 kHz. It is possible to synchronize the converter to an external clock within a frequency range from 600 kHz to 1200 kHz. The device automatically detects the rising edge of the first clock and synchronizes to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation. The switchover is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 8.3 µs if the internal clock has its minimum frequency of 600 kHz. During this time, there is no clock signal available. The device stops switching until the internal circuitry is switched to the internal clock source. When the device is switched between internal synchronization and external synchronization during operation, the output voltage may show transient over/undershoot during switchover. The voltage transients are minimized by using 850 kHz as an initial external frequency, and changing the frequency slowly (>1 ms) to the value desired. The voltage drop at the output when the device is switched from external synchronization to internal synchronization can be reduced by increasing the output capacitor value. If the device is synchronized to an external clock, the power-save mode is disabled and the device stays in forced PWM mode. 12 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 Connecting the SYNC pin to the GND pin enables the power-save mode. The converter operates in the PWM mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide load current range. Power Good Comparator The power good (PG) comparator has an open drain output capable of sinking typically 1 mA. The PG function is only active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is pulled to GND. The PG output is only valid after a 250 µs delay after the device is enabled and the supply voltage is greater than 2.7 V. Power good is low during the first 250 µs after shutdown and in shutdown. The PG pin floats high when the output voltage exceeds typically 98.5% of its nominal value. Leave the PG pin unconnected, or connect to GND when not used. Low-Battery Detector (Standard Version) The low-battery output (LBO) is an open drain type which goes low when the voltage at the low battery input (LBI) falls below the trip point of 1.21 V ±1.5%. The voltage at which the low-battery warning is issued is adjusted with a resistive divider as shown in Figure 21. The sum of the resistors R1 and R2 is recommended to be in the 100-kΩ to 1-MΩ range for high efficiency at low output current. An external pullup resistor at LBO can either be connected to OUT, or any other voltage rail in the voltage range of 0 V to 6 V. During start-up, the LBO output signal is invalid for the first 500 µs. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used, connect LBI to ground. The low-battery detector is disabled when the device is disabled. Leave the LBO pin unconnected, or connect to GND when not used. ENABLE/Low-Battery Detector (Enhanced Version) TPS62051 Only The TPS62051 offers an enhanced LBI functionality to provide a precise, user programmable undervoltage shutdown. No additional supply voltage supervisor (SVS) is needed to provide this function. When the enable (EN) pin is pulled high, only the internal bandgap voltage reference is switched on to provide a reference source for the LBI comparator. As long as the voltage at LBI is less than the LBI trip point, all other internal circuits are shut down, reducing the supply current to 5 µA. As soon as input voltage at LBI rises above the LBI trip point of 1.21 V, the device is completely enabled and starts switching. VIN ENABLE Bandgap Enable to Internal Circuitry LBI LBI Comparator LBO Figure 20. Block Diagram of ENABLE/LBI Functionality for TPS62051 The logic level of the LBO pin is not defined for the first 500 µs after EN is pulled high. When the enhanced LBI is used to supervise the battery voltage and shut down the TPS62051 at low input voltages, the battery voltage rises again when the current drops to zero. The implemented hysteresis on the LBI pin may not be sufficient for all types of batteries. Figure 21 shows how an additional external hysteresis can be implemented. Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 13 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com 1 8 VIN SW EN FB L1 = 10 µH VO = 2.5 V / 600 mA 5 R3 R4 R1 C(ff) = 6.8 pF TPS62051 R5 6 Ci = 10 µF 1 Cell Li-lon 9 PG 4 LBI 7 SYNC R6 GND 3 LBO R2 2 Co = 22 µF PGND 10 R7 Figure 21. Enhanced LBI With Increased Hysteresis A MATHCAD® file to calculate R7 can be downloaded from the product folder on the TI web. No Load Operation If the converter operates in the forced PWM mode and there is no load connected to the output, the converter regulates the output voltage by allowing the inductor current to reverse for a short period of time. STANDARD CIRCUIT FOR ADJUSTABLE VERSION WE PD 744 777 10 VI 1 R5 130 kΩ Ci = 10 µF VIN SW EN FB 5 8 R6 100 kΩ R3 1M VO = 5 V R4 1M C(ff) = 6.8 pF TPS62050 6 TDK C3216X5R1A106M 9 L1 = 10 µH R1 = 820 kΩ 4 LBI PG 7 Co = 22 µF 2 SYNC GND 3 LBO Taiyo Yuden JMK316BJ226ML R2 = 91 kΩ PGND 10 Quiescent Current Measurements and Efficiency Were Taken With: R5 = Open, R4 = Open, LBI Connected to GND. V 14 O +V FB R1 ) R2 R2 Submit Documentation Feedback ǒ Ǔ V R1 + R2 O –R2 V FB V FB + 0.5V Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 Table 2. Values NOMINAL OUTPUT VOLTAGE EQUATION POSSIBLE RESISTOR COMBINATION TYPICAL FEEDBACK CAPACITOR 0.7 V R1 = 0.4 x R2 R1 = 270 k, R2 = 680 k C(ff) = 22 pF 1.2 V R1 = 1.4 x R2 R1 = 510 k, R2 = 360 k (1.21 V) C(ff) = 6.8 pF 1.5 V R1 = 2 x R2 R1 = 300 k, R2 = 150 k (1.50 V) C(ff) = 6.8 pF 1.8 V R1 = 2.6 x R2 R1 = 390 k, R2 = 150 k (1.80 V) C(ff) = 6.8 pF 2.5 V R1 = 4 x R2 R1 = 680 k, R2 = 169 k (2.51 V) C(ff) = 6.8 pF 3.3 V R1 = 5.6 x R2 R1 = 560 k, R2 = 100 k (3.30 V) C(ff) = 6.8 pF 5V R1 = 9 x R2 R1 = 820 k, R2 = 91 k (5.0 V) C(ff) = 6.8 pF STANDARD CIRCUIT FOR FIXED VOLTAGE VERSION VI = 2.7 V to 10 V 1 R5 VIN SW EN FB 9 L1 = 10 µH 5 8 R3 VO = 1.8 V / 600 mA R4 TPS62054 Ci = 10 µF 6 4 R6 PG LBI 7 SYNC LBO Co = 22 µF 2 PGND GND 3 10 CONVERTER FOR 0.7-V OUTPUT VOLTAGE VI = 2.7 V to 7 V 1 SW VIN R1 = 270 kΩ 8 EN Ci = 10 µF 9 L1 = 10 µH FB 5 VO = 0.7 V / 600 mA C(ff) = 22 pF TPS62050 6 4 LBI PG 7 R2 = 680 kΩ Co = 47 µF 2 SYNC GND 3 LBO PGND 10 The TPS62050 is used to generate output voltages as low as 0.7 V. With such low output voltages, the inductor discharges very slowly. This leads to a high output voltage ripple in power-save mode (SYNC = GND). It is therefore recommended to use a larger output capacitor to keep the output ripple low. With an output capacitor of 47 µF, the output voltage ripple is less than 40 mVPP. Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 15 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com LAYOUT AND BOARD SPACE All capacitors should be soldered as close as possible to the IC. For information on the PCB layout see the user's guideSLVU081. Keep the feedback track as short as possible. Any coupling to the FB pin may cause additional output voltage ripple. INDUCTOR SELECTION A 10-µH minimum inductor should be used with the TPS6205x. Values larger than 22 µH or smaller than 10 µH may cause stability problems due to the internal compensation of the regulator. After choosing the inductor value of typically 10 µH, two additional inductor parameter should be considered: the current rating of the inductor and the dc resistance. The dc resistance of the inductance directly influences the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus half the inductor ripple current which is calculated as: DI L + V O V 1* O V I L f I L(max) + I (max) ) DIL O 2 f = Switching frequency (850 kHz typical) L = Inductor value ∆IL = Peak-to-peak inductor ripple current IL(max) = Maximum inductor current The highest inductor current occurs at maximum VIN . A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS6205x which is 1.4 A maximum. See Table 3 for inductors that have been tested for operation with the TPS6205x. Table 3. Inductors MANUFACTURER TYPE INDUCTANCE DC RESISTANCE SATURATION CURRENT TDK SLF7032T100M1R4SLF7032T220M96SLF7045T100M1R3SLF7045T100MR90 10 µH ±20% 22 µH ±20% 10 µH ±20% 22 µH ±20% 53 mΩ ±20% 110 mΩ ±20% 36 mΩ ±20% 61 mΩ ±20% 1.4 A 0.96 A 1.3 A 0.9 A CDR74B 10 µH 70 mΩ 1.65 A CDR74B 22 µH 130 mΩ 1.12 A CDH74 10 µH 49 mΩ 1.8 A CDH74 22 µH 110 mΩ 1.23 A CDR63B 10 µH 140 mΩ 1A CDRH4D28 10 µH 128 mΩ 1A CDRH5D28 10 µH 48 mΩ 1.3 A CDRH5D18 10 µH 92 mΩ 1.2 A DT3316P-153 15 µH 60 mΩ 1.8 A DT3316P-223 22 µH 84 mΩ 1.5 A WE-PD 744 778 10 10 µH 72 mΩ 1.68 A 1.84 A Sumida Coilcraft Wuerth 16 WE-PD 744 777 10 10 µH 49 mΩ WE-PD 744 778 122 22 µH 190 mΩ 1.07A WE-PD 744 777 122 22 µH 110 mΩ 1.23 A Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 OUTPUT CAPACITOR SELECTION The output capacitor should have a minimum value of 22µF. For best performance, a low ESR ceramic output capacitor is needed. For completeness, the RMS ripple current is calculated as: I RMS(Co) +V O V 1– O V I L f 1 Ǹ3 2 The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charge and discharging the output capacitor: DV O +V O V 1* O V I L f ǒ 8 1 Co f )R ESR Ǔ The highest output voltage ripple occurs at the highest input voltage VI. INPUT CAPACITOR SELECTION Because the buck converter has a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The input capacitor should have a minimum value of 10 µF and can be increased without any limit for better input voltage filtering. The input capacitor should be rated for the maximum input ripple current calculated as: Ǹ ǒ Ǔ V I + I (max) RMS O O V I V 1* O V I The worst case RMS ripple current occurs at D = 0.5 and is calculated as: IRMS = IO/2. Ceramic capacitors have a good performance because of their low ESR value and they are less sensitive to voltage transients compared to tantalum capacitors. Place the input capacitor as close as possible to the input pin of the IC for best performance. Table 4. Capacitors MANUFACTURER Taiyo Yuden Kemet TDK (1) PART NUMBER SIZE VOLTAGE CAPACITANCE TYPE JMK212BJ106MG 0805 6.3 V 10 µF Ceramic JMK316BJ106ML 1206 6.3 V 10 µF Ceramic JMK316BJ226ML 1206 6.3 V 22 µF Ceramic LMK316BJ475ML 1206 10 V 4.7 µF (1) Ceramic (1) Ceramic EMK316BJ475ML 1206 16 V EMK325BJ106KN-T 1210 16 V 4.7 µF 10 µF Ceramic C1206C106M9PAC 1206 6.3 V 10 µF Ceramic C2012X5R0J106M 0805 6.3 V 10 µF Ceramic C3216X5R0J226M 1206 6.3 V 22 µF Ceramic C3216X5R1A106M 1206 10 V 10 µF Ceramic Connect two in parallel. Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 17 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 www.ti.com Table 5. Capacitor Manufacturers 18 MANUFACTURER CAPACITOR TYPE INTERNET Taiyo Yuden X7R/X5R ceramic www.t-yuden.com TDK X7R/X5R ceramic www.component.tdk.com Vishay X7R/X5R ceramic www.vishay.com Kemet X7R/X5R ceramic www.kemet.com Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 TPS62052, TPS62054 TPS62056, TPS62050, TPS62051 www.ti.com SLVS432E – SEPTEMBER 2002 – REVISED JUNE 2011 REVISION HISTORY Note: Page numbers of current version may differ from previous versions. Changes from Revision D (October 2003) to Revision E Page • Changed to Revision E, June 2011 ...................................................................................................................................... 1 • Changed formatting. ............................................................................................................................................................. 1 • Changed "goes active high" to "floats" in Terminal Functions table, row PG, description. .................................................. 5 • Changed "becomes active" to "floats" in last paragraph of Power Good Comparator section. .......................................... 13 Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62052 TPS62054 TPS62056 TPS62050 TPS62051 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS62050DGS ACTIVE VSSOP DGS 10 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 85 BFM TPS62050DGSG4 ACTIVE VSSOP DGS 10 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 85 BFM TPS62050DGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 85 BFM TPS62050DGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 85 BFM TPS62051DGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGB TPS62051DGSG4 ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGB TPS62051DGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGB TPS62051DGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGB TPS62052DGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGC TPS62052DGSG4 ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGC TPS62052DGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGC TPS62052DGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGC TPS62054DGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGE TPS62054DGSG4 ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGE TPS62054DGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGE TPS62054DGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGE TPS62056DGS ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGG Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS62056DGSG4 ACTIVE VSSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGG TPS62056DGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGG TPS62056DGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BGG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62050DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS62051DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS62052DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS62054DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS62056DGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62050DGSR VSSOP DGS 10 2500 367.0 367.0 35.0 TPS62051DGSR VSSOP DGS 10 2500 367.0 367.0 35.0 TPS62052DGSR VSSOP DGS 10 2500 367.0 367.0 35.0 TPS62054DGSR VSSOP DGS 10 2500 367.0 367.0 35.0 TPS62056DGSR VSSOP DGS 10 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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