TI TPS62000SHKK

TPS62000-HT
www.ti.com .......................................................................................................................................................... SLVS917A – MARCH 2009 – REVISED JUNE 2009
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
High-Efficiency Synchronous Step-Down
Converter With Greater Than 95% Efficiency
2 V to 5.5 V Operating Input Voltage Range
Adjustable Output Voltage Range From 0.8 V
to VI
Synchronizable to External Clock Signal up to
1 MHz
Up to 300 mA Output Current
Pin-Programmable Current Limit
High Efficiency Over a Wide Load Current
Range in Power Save Mode
100% Maximum Duty Cycle for Lowest
Dropout
Low-Noise Operation Antiringing Switch and
PFM/PWM Operation Mode
Internal Softstart
50-µA Quiescent Current (TYP)
Evaluation Module Available for Commercial
Temperature Range
APPLICATIONS
•
•
Down-Hole Drilling
High Temperature Environments
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
Custom temperature ranges available
DESCRIPTION
The TPS62000 device is a low-noise synchronous step-down dc-dc converter that is ideally suited for systems
powered from a 1-cell Li-ion battery or from a 2- to 3-cell NiCd, NiMH, or alkaline battery. The TPS62000
operates typically down to an input voltage of 1.8 V, with a specified minimum input voltage of 2 V.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS62000-HT
SLVS917A – MARCH 2009 – REVISED JUNE 2009 .......................................................................................................................................................... www.ti.com
EFFICIENCY
vs
LOAD CURRENT
10 mH
VI = 2 V
to 5.5 V
100
10 mF
VIN
L
EN
FB
†
PGND
80
70
Efficiency − %
10 mF
TPS6200x
90
VO = 0.8 V
to VI
SYNC
GND
SYNC = Low
FC
60
SYNC = High
50
0.1 mF
40
†
30
With VO ≥1.8 V; Co = 10 mF, VO <1.8 V; Co = 47 mF
20
VI = 3.6 V,
VO = 2.5 V
10
0
0.1
1
10
100
IO − Load Current − mA
1000
Figure 1.
Figure 2. Typical Application Circuit for Fixed Output
Voltage Option
DESCRIPTION (CONTINUED)
The TPS62000 is a synchronous current-mode PWM converter with integrated N- and P-channel power
MOSFET switches. Synchronous rectification is used to increase efficiency and to reduce external component
count. To achieve the highest efficiency over a wide load current range, the converter enters a power-saving
pulse-frequency modulation (PFM) mode at light load currents. Operating frequency is typically 750 kHz, allowing
the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the
range of 500 kHz to 1 MHz. For low-noise operation, the converter can be operated in the PWM mode and the
internal antiringing switch reduces noise and EMI. In the shutdown mode, the current consumption is reduced to
less than 1 µA. The TPS62000-HT is available in the 10-pin (HKK). The dvice operates a free-air temperature
range of –55°C to 210°C.
HKK PACKAGE
(TOP VIEW)
VIN
FC
GND
NC
FB
1
10
2
9
3
8
4
7
5
6
PGND
L
EN
SYNC
NC
AVAILABLE OPTIONS (1)
TA
VOLTAGE OPTIONS
–55°C to 210°C
(1)
(2)
2
Adjustable
PACKAGE (2)
ORDERING PART NUMBER
KGD
TPS62000SKGD1
HKK
TPS62000SHKK
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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FUNCTIONAL BLOCK DIAGRAM
FC (See Note B)
Undervoltage
Lockout
Bias Supply
VIN
10 Ω
EN
+
_
R1
PFM/PWM
Comparator
_
+
Soft
Start
+
PFM/PWM
Control Logic
Current Limit
Logic
Driver
Shoot-Through
Logic
N-Channel
Power MOSFET
EN
+
_
L
Compensation
R2
R1 + R2 ≈ 1 MΩ
P-Channel
Power MOSFET
PFM/PWM
Mode Select
Error Amplifier
_
FB
(See
Note A)
Current
Sense
Slope Compensation
Power Good
Vref = 0.45 V
Sync
+
Oscillator
Load Comparator
+
_
Current Sense
+
Offset
PGND
Antiringing
FB
GND
SYNC
A.
The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly
connected to the error amplifier.
B.
Do not connect the FC pin to an external power source
PIN FUNCTIONS
PIN
NAME
I/O
DESCRIPTION
EN
I
Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current
to less than 1 µA.
FB
I
An external resistive divider is connected to FB. The internal voltage divider is disabled.
Supply bypass pin. A 0.1 µF coupling capacitor should be connected as close as possible to this pin for good high
frequency input voltage supply filtering.
FC
GND
L
Ground.
I/O
PGND
Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.
Power ground. Connect all power grounds to PGND.
SYNC
I
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock
signal with CMOS level:
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced.
SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled.
VIN
I
Supply voltage input.
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BARE DIE INFORMATION
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
15 mils.
Silicon with backgrind
GND
Al-Si-Cu (0.5%)
Origin
a
c
b
d
Bond Pad Coordinates in Microns - Rev A
4
DESCRIPTION
PAD NUMBER
a
b
c
d
FB
1
142.15
92.40
227.15
177.40
Do not use
2
142.15
194.40
227.15
279.40
Do not use
3
907.35
104.05
983.35
180.05
Do not use
4
1001.35
104.05
1077.35
180.05
Do not use
5
1095.35
104.05
1171.35
180.05
Do not use
6
1189.35
104.05
1265.35
180.05
Do not use
7
1296.85
90.60
1381.85
175.60
SYNC
8
1296.85
192.60
1381.85
277.60
EN
9
1296.85
835.10
1381.85
920.10
L
10
1128.20
1194.55
1213.20
1279.55
L
11
1128.20
1296.55
1213.20
1381.55
Do not use
12
1350.50
1806.50
1435.50
1891.50
PGND
13
1350.50
1908.50
1435.50
1993.50
PGND
14
1350.50
2010.50
1435.50
2095.50
Vin
15
92.40
1956.85
177.40
2041.85
Vin
16
92.40
1854.85
177.40
1939.85
Do not use
17
92.40
1687.70
177.40
1772.70
FC
18
92.40
1529.00
177.40
1614.00
GND
19
90.60
1295.70
175.60
1380.70
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1524 mm
FB
SYNC
EN
2184 mm
L
L
GND
FC
PGND
PGND
Vin
Vin
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DETAILED DESCRIPTION
Operation
The TPS62000 is a step down converter operating in a current mode PFM/PWM scheme with a typical switching
frequency of 750 kHz.
At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the
converter enters a power save mode (pulse frequency modulation) to keep the efficiency high.
In the PWM mode operation, the part operates at a fixed frequency of 750 kHz. At the beginning of each clock
cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an
internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator to
trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM).
After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and
the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next
clock cycle starts.
In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle.
In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current
becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and low
side MOSFET to ground that would cause additional losses.
As the load current decreases and the peak inductor current does not reach the power save mode threshold of
typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM) mode.
In
•
•
•
the PFM mode, the converter operates with:
Variable frequency
Constant peak current that reduces switching losses
Quiescent current at a minimum
Thus maintaining the highest efficiency at light load currents. In this mode, the output voltage is monitored with
the error amplifier. As soon as the output voltage falls below the nominal value, the high side switch is turned on
and the inductor current ramps up. When the inductor current reaches the peak current of typical: 150 mA +
50 mA/V × (VI – VO), the high side switch turns off and the low side switch turns on. As the inductor current
ramps down, the low side switch is turned off before the inductor current becomes negative which completes the
cycle. When the output voltage falls below the nominal voltage again, the next cycle is started.
The converter enters the PWM mode again as soon as the output voltage can not be maintained with the typical
peak inductor current in the PFM mode.
The control loop is internally compensated reducing the amount of external components.
The switch current is internally sensed and the maximum current limit can be set to typical 600 mA by connecting
ILIM to ground; or, to typically 1.2 A by connecting ILIM to VIN.
100% Duty Cycle Operation
As the input voltage approaches the output voltage and the duty cycle exceeds typical 95%, the converter turns
the P-channel high side switch continuously on. In this mode, the output voltage is equal to the input voltage
minus the voltage drop across the P-channel MOSFET.
Synchronization, Power Save Mode and Forced PWM Mode
If no clock signal is applied, the converter operates with a typical switching frequency of 750 kHz. It is possible to
synchronize the converter to an external clock within a frequency range from 500 kHz to 1000 kHz. The device
automatically detects the rising edge of the first clock and is synchronizes immediately to the external clock. If
the clock signal is stopped, the converter automatically switches back to the internal clock and continues
operation without interruption. The switch over is initiated if no rising edge on the SYNC pin is detected for a
duration of four clock cycles. Therefore, the maximum delay time can be 8 µs in case the internal clock has a
minimum frequency of 500 kHz.
In case the device is synchronized to an external clock, the power save mode is disabled and the device stays in
forced PWM mode.
6
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Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM
mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide
load current range.
Connecting the SYNC pin to the VIN pin forces the converter to operate permanently in the PWM mode even at
light or no load currents. The advantage is the converter operates with a fixed switching frequency that allows
simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower
compared to the power save mode during light loads (see Figure 1).
It is possible to switch from forced PWM mode to the power save mode during operation.
The flexible configuration of the SYNC pin during operation of the device allows efficient power management by
adjusting the operation of the TPS62000 to the specific system requirements.
Low Noise Antiringing Switch
An antiringing switch is implemented in order to reduce the EMI radiated from the converter during discontinuous
conduction mode (DCM). In DCM, the inductor current ramps to zero before the end of each switching period.
The internal load comparator turns off the low side switch at that instant thus preventing the current flowing
backward through the inductance which increases the efficiency. An antiringing switch across the inductor
prevents parasitic oscillation caused by the residual energy stored in the inductance (see Figure 12).
NOTE:
The antiringing switch is only activated in the fixed output voltage versions. It is not
enabled for the adjustable output voltage version TPS62000.
Soft Start
As the enable pin (EN) goes high, the soft-start function generates an internal voltage ramp. This causes the
start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start
duration is typical 1 ms (see Figure 13). When the soft-start function is completed, the error amplifier is
connected directly to the internal voltage reference.
Enable
Logic low on EN forces the TPS62000 into shutdown. In shutdown, the power switch, drivers, voltage reference,
oscillator, and all other functions are turned off. The supply current is reduced to less than 1 µA in the shutdown
mode.
Undervoltage Lockout
An undervoltage lockout circuit provides the save operation of the device. It prevents the converter from turning
on when the voltage on VIN is less than typically 1.6 V.
No Load Operation
In case the converter operates in the forced PWM mode and there is no load connected to the output, the
converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
Supply voltages on pin VIN and FC (2)
–0.3 to 6
V
Voltages on pins EN, SYNC, FB, L (2)
–0.3 to VIN + 0.3
V
1.6
A
Peak switch current
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
TA = –55°C to 125°C
MIN
VI
Supply voltage
VO
Output voltage range for adjustable output voltage version
IO
Output current for 3-cell operation (VI ≥ 2.5 V; L = 10 µH, f = 750 kHz)
IO
Output current for 2-cell operation (VI ≥ 2 V; L = 10 µH, f = 750 kHz)
L
Inductor (2) (see Note 2)
TYP
2
0.8
TA = 210°C (1)
MAX
MIN
5.5
2
VI
0.8
TYP
5.5
VI
300
200
10
MAX
UNIT
V
V
300
mA
200
mA
µH
10
CI
Input capacitor
(2)
10
10
µF
Co
Output capacitor (2) (VO ≥ 1.8 V)
10
10
µF
Co
Output capacitor (2) VO < 1.8 V)
47
47
µF
TA
Operating ambient temperature
–55
(1)
(2)
8
210
–55
210
°C
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Refer to application section for further information.
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless oherwise noted), VI = 3.6 V, VO = 2.5 V,
IO = 300 mA (TA = –55°C to 125°C), IO = 50 mA (TA = 210°C), EN = VIN
TEST
CONDITIONS
PARAMETER
TA = 210°C (1)
TA = –55°C to 125°C
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IO = 0 mA to 300 mA
2.5
5.5
2.5
5.5
IO = 0 mA to 200 mA
2
5.5
2
5.5
VI
Input voltage range
V
I(Q)
Operating quiescent
current
IO = 0 mA, SYNC = GND
(PFM-mode enabled)
50
75
1400
4000
µA
I(SD)
Shutdown current
EN = GND
0.1
1
90
200
µA
ENABLE
VIH
EN high-level input voltage
VIL
EN low level input voltage
Ilkg
EN input leakage current
V(UVLO)
Undervoltage lockout
threshold
1.5
1.5
V
0.4
EN = GND or VIN
1.2
0.1
1.1
1.6
2
1.2
0.4
V
0.1
1.1
µA
1.6
2
V
POWER SWITCH AND CURRENT LIMIT
P-channel MOSFET
on-resistance
VI = VGS = 3.6 V, I = 200 mA
580
670 (2)
VI = VGS = 2 V, I = 200 mA
790
850 (2)
N-channel MOSFET
on-resistance
VI = VGS = 3.6 V, IO = 200 mA
580
670 (2)
VI = VGS = 2 V, IO = 200 mA
790
800 (2)
rDS(on)
mΩ
mΩ
OSCILLATOR
fs
Oscillator frequency
f(SYNC)
Synchronization range
VIH
SYNC high level input
voltage
VIL
SYNC low level input
voltage
Ilkg
SYNC input leakage
current
500
CMOS-logic clock signal
on SYNC pin
(2)
500
1000
200
1000
500
1.3
320
SYNC = GND or VIN
600
kHz
1000
kHz
1.3
V
0.4
Duty cycle of external clock
signal
(1)
750
0.1
20%
1.1
60%
0.1
20%
0.4
V
1.1
µA
60%
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
Measured at 50 mA.
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted), VI = 3.6 V, VO = 2.5 V,
IO = 300 mA (TA = –55°C to 125°C), IO = 50 mA (TA = 210°C), EN = VIN, ILIM = VIN
PARAMETER
VO
Adjustable
output voltage
range
TPS62000
Vref
Reference
voltage
TPS62000
VO
Fixed output
voltage (2)
TPS62000
adjustable
η
(2)
(3)
(4)
10
MIN
TYP
MAX
MIN
5.5
0.8
0.45
–5.5
5
10 mA < IO ≤ 300 mA
–5.5
5
Load regulation
VI = 5.5 V; IO = 10 mA to 300 mA
VI = 5 V; VO = 3.3 V; IO = 300 mA
VI = 3.6 V; VO = 2.5 V; IO = 200 mA
IO = 0 mA, time from active EN to VO
0.4
TYP
15 (3)
0.05
13 (4)
0.6%
23% (4)
85%
73%
2
MAX
5.5
0.38
VI = 2.5 V to 5.5 V; 0 mA ≤ IO ≤ 100 mA
VI = VO + 0.5 V (min. 2 V) to 5.5 V, IO = 10 mA
Efficiency
TA = 210°C (1)
TA = –55°C to 125°C
0.8
Line regulation
Start-up time
(1)
TEST CONDITIONS
0.75
UNIT
V
V
%V
%/V
ms
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
The output voltage accuracy includes line and load regulation over the full temperature range, TA = –55°C to 125°C.
VIN = 5.5 V
VIN = 3.3 V to 5.5 V, IO = 100 mA to 300 mA
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
η
Efficiency
vs Load current
3, 4, 5
V(drop)
Dropout voltage
vs Load current
6
IQ
Operating quiescent current
vs Input voltage (power save mode)
7
vs Input voltage (forced PWM)
8
fOSC
Oscillator frequency
vs Free-air temperature
9
Load transient response
10
Line transient response
11
Power save mode operation
VO
12
Start-up
vs Time
13
Output voltage
vs Load current
14
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
VO = 2.5 V
Efficiency − %
90
80
VI = 3.6 V
70
VI = 5 V
60
50
40
0.1
Figure 3.
1
10
100
IO − Load Current − mA
1000
Figure 4.
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DROPOUT VOLTAGE
vs
LOAD CURRENT
Figure 5.
Figure 6.
OPERATING QUIESCENT CURRENT
vs
INPUT VOLTAGE (POWER SAVE MODE)
OPERATING QUIESCENT CURRENT
vs
INPUT VOLTAGE (FORCED PWM)
I(Q) - Operating Quescent Current - mA
I(Q) - Operating Quescent Current - mA
EFFICIENCY
vs
LOAD CURRENT
Figure 7.
12
Figure 8.
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OSCILLATOR FREQUENCY
vs
FREE-AIR TEMPERATURE
LOAD TRANSIENT RESPONSE
800
750
VI = 3.6 V
F - Frequency - kHz
700
650
600
550
500
450
400
350
300
-60 -30
0
30
60
90 120 150 180 210
TA - Free Air Temperature - °C
200 ms/div
Figure 9.
Figure 10.
LINE TRANSIENT RESPONSE
POWER SAVE MODE OPERATION
400 ms/div
10 ms/div
Figure 11.
Figure 12.
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START-UP
vs
TIME
EN
2 V/div
VO
1 V/div
Power Good
1 V/div
II
200 mA/div
250 ms/div
Figure 13.
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.55
2.54
VO − Output Voltage − V
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
0
100
200
300
400
500
600
IO − Load Current − mA
Figure 14.
14
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APPLICATION INFORMATION (1)
ADJUSTABLE OUTPUT VOLTAGE VERSION
When the adjustable output voltage version (TPS62000DGS) is used, the output voltage is set by the external
resistor divider (see Figure 15).
The output voltage is calculated as:
R1 ö
æ
VO = 0.45 V ´ ç 1 +
R2 ÷ø
è
(1)
With R1 + R2 ≤ 1 MΩ
R1 + R2 should not be greater than 1 MW because of stability reasons.
For stability reasons, a small bypass capacitor (C(ff)) is required in parallel to the upper feedback resistor, refer to
Figure 15. The bypass capacitor value can be calculated as:
1
C(ff) =
for Co < 47 mF
2p ´ 30000 ´ R1
(2)
1
C(ff) =
for Co ³ 47 mF
2p ´ 5000 ´ R1
(3)
R1 is the upper resistor of the voltage divider. For C(ff), choose a value which comes closest to the computed
result.
L1 = 10 mH
VI = 2.7 V to 5.5 V
VIN
VO = 2.5 V/300 mA
L
+
Ci = 10 mF
FB
EN
R1 = 820 kΩ
TPS62000
C(ff) =
6.8 pF
+
Co = 10 mF
SYNC
GND
PGND
FC
R2 = 180 kΩ
C3 = 0.1 mF
Figure 15. Typical Application Circuit for Adjustable Output Voltage Option
INDUCTOR SELECTION
A 10-µH minimum output inductor is used with the TPS62000. Values larger than 22 µH or smaller than 10 µH
may cause stability problems because of the internal compensation of the regulator.
For output voltages greater than 1.8 V, a 22-µH inductance might be used in order to improve the efficiency of
the converter.
After choosing the inductor value of typically 10 µH, two additional inductor parameters should be considered:
first the current rating of the inductor and second the dc resistance.
The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with
lowest dc resistance should be selected for highest efficiency.
In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current
plus the inductor ripple current which is calculated as:
(1)
Application information is provided for commercial temperature as a reference and not for high temperature.
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TPS62000-HT
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VO
VI
L ´ f
1 DIL = VO ´
IL(max) = IO(max) +
DIL
2
(4)
Where:
ƒ = Switching frequency (750 kHz typical)
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
IL(max) = Maximum inductor current
The highest inductor current occurs at maximum VI.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS62000 which is 1.6 A with ILIM = VIN and 900 mA with ILIM = GND. See Table 1 for recommended
inductors.
Table 1. Tested Inductors (1)
OUTPUT CURRENT
INDUCTOR VALUE
COMPONENT SUPPLIER
COMMENTS
High efficiency
10 µH
Coilcraft DO3316P-103
Coilcraft DT3316P-103
Sumida CDR63B-100
Sumida CDRH5D28-100
Coilcraft DO1608C-103
Sumida CDRH4D28-100
Smallest solution
Coilcraft DO1608C-103
High efficiency
Murata LQH4C100K04
Smallest solution
0 mA to 600 mA
10 µH
0 mA to 300 mA
(1)
Parts are valid for –40°C to 85°C.
OUTPUT CAPACITOR SELECTION
For best performance, a low ESR output capacitor is needed. At output voltages greater than 1.8 V, ceramic
output capacitors can be used to show the best performance. Output voltages below 1.8 V require a larger output
capacitor and ESR value to improve the performance and stability of the converter.
Table 2. Capacitor Selection
OUTPUT VOLTAGE RANGE
OUTPUT CAPACITOR
OUTPUT CAPACITOR ESR
1.8 V ≤ VI ≤ 5.5 V
Co ≥ 10 µF
ESR ≤ 120 mΩ
0.8 V ≤ VI < 1.8 V
Co ≥ 47 µF
ESR > 50 mΩ
See Table 3 for recommended capacitors.
If an output capacitor is selected with an ESR value ≤ 120 mΩ, its RMS ripple current rating always meets the
application requirements. Just for completeness, the RMS ripple current is calculated as:
V
1 - O
VI
1
IRMS(CO ) = VO ´
´
L ´ f
2´ 3
(5)
The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the
voltage ripple caused by charge and discharging the output capacitor:
VO
VI
L ´ f
1 DVO = VO ´
æ
ö
1
´ ç
+ ESR ÷
è 8 ´ CO ´ f
ø
(6)
Where the highest output voltage ripple occurs at the highest input voltage VI.
16
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Table 3. Tested Capacitors (1)
CAPACITOR VALUE
ESR/mΩ
COMPONENT SUPPLIER
10 µF
50
Taiyo Yuden JMK316BJ106KL
Ceramic
47 µF
100
Sanyo 6TPA47M
POSCAP
68 µF
100
Spraque 594D686X0010C2T
Tantalum
(1)
COMMENTS
Parts are valid for –40°C to 85°C.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes.
The input capacitor should have a minimum value of 10 µF and can be increased without any limit for better input
voltage filtering.
The input capacitor should be rated for the maximum input ripple current calculated as:
VO æ VO ö
´ ç 1÷
VI è
VI ø
IRMS = IO(max) ´
(7)
The worst case RMS ripple current occurs at D = 0.5 and is calculated as:
IRMS =
IO
2
Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against
voltage transients compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin of the IC for best performance.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design especially at high peak currents
and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well
as EMI problems.
Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input
capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Place
the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground,
PGND, need to be separated. Use a common ground node as shown in Figure 16 to minimize the effects of
ground noise.
L1
VI
VIN
VO
L
+
Ci
EN
FB
R1
TPS62000
C(ff)
+
Co
R2
SYNC
GND
PGND
FC
C3
Figure 16. Layout Diagram
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TYPICAL APPLICATION
10 mH
3
(2)
470 kW
10 mF
47 mF
326 kW
524 kW
0.1 mF
Sumida CDRH5D28-100
10 mF Ceramic Taiyo Yuden
JMK316BJ106KL
Sanyo 6TPA47M
0.1 mF Ceramic
(1)
Use a small R-C filter to filter wrong reset signals during output voltage transitions.
(2)
A large value is used for C(ff) to compensate for the parasitic capacitance introduced into the regulation loop by Q1.
Figure 17. Dynamic Output Voltage Programming As Used in Low Power DSP Applications
18
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1000
Years of Estimated Life
100
Electromigration Fail Mode
10
1
110
130
150
170
190
210
230
Continous TJ - °C
Figure 18. TPS62000SKGD1 Operating Life Derating Chart
Notes:
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
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19
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS62000SHKK
ACTIVE
CFP
HKK
10
1
TBD
AU
N / A for Pkg Type
Contact TI Distributor
or Sales Office
TPS62000SKGD1
ACTIVE
XCEPT
KGD
0
100
TBD
Call TI
N / A for Pkg Type
Contact TI Distributor
or Sales Office
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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