TPS62692, TPS62693 TPS62694, TPS62698 CSP-6 www.ti.com SLVSAZ1 – DECEMBER 2012 800-mA , 3-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER Check for Samples: TPS62692, TPS62693, TPS62694, TPS62698 FEATURES 1 • • • • • • • • • • • • 23 • • • • • 95% Efficiency at 3MHz Operation 21 μA Quiescent Current 3 MHz Regulated Frequency Operation Spread Spectrum, PWM Frequency Dithering High Duty-Cycle Operation ±2% Total DC Voltage Accuracy Best in Class Load and Line Transient Excellent AC Load Regulation Low Ripple Light-Load PFM Mode ≥40 dB VIN PSRR (1 kHz to 10 kHz) Internal Soft Start, 350-μs Start-Up Time Integrated Active Power-Down Sequencing (Optional) Current Overload and Thermal Shutdown Protection Three Surface-Mount External Components Required (One 2012 MLCC Inductor, Two 0402 Ceramic Capacitors) Complete Sub 1-mm Component Profile Solution Total Solution Size <12 mm2 (CSP) Available in a 6-Pin NanoFree™ (CSP) DESCRIPTION The TPS62693 device is a high-frequency synchronous step-down dc-dc converter optimized for battery-powered portable applications. Intended for low-power applications, the TPS62693 supports up to 800-mA load current, and allows the use of low cost chip inductor and capacitors. The device is ideal for mobile phones and similar portable applications powered by a single-cell Li-Ion battery. Different fixed output voltage versions are available in the range from 2.2 V up to 3.3 V. The TPS62693 operates at a regulated 3-MHz switching frequency and enters the power-save mode operation at light load currents to maintain high efficiency over the entire load current range. The PFM mode extends the battery life by reducing the quiescent current to 21 μA (typical) during light load operation. For noise-sensitive applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. This feature, combined with high PSRR and AC load regulation performance, make this device suitable to replace a linear regulator to obtain better power conversion efficiency. APPLICATIONS Memory Cards LDO Replacement Cell Phones, Smart-Phones WLAN, Bluetooth™ Applications VIN 3.15 V ... 4.8 V CI TPS62693 L VIN SW EN FB 90 80 70 VOUT 2.85 V @ 800mA Efficiency (%) • • • • 100 60 50 40 30 1.0 mH 20 2.2 mF CO 4.7 mF GND MODE VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 3.6V (PWM) 10 VOUT = 2.85V 0 0.1 1 10 Current (mA) 100 1000 G000 Figure 1. Smallest Solution Size Application Figure 2. Efficiency vs. Load Current 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. Bluetooth is a trademark of Bluetooth SIG. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) (3) (4) TA PART NUMBER OUTPUT VOLTAGE (2) DEVICE SPECIFIC FEATURE ORDERING (3) PACKAGE MARKING CHIP CODE -40°C to 85°C TPS62692 2.2 (4) 800 mA peak output current Output Discharge Spread Spectrum Frequency Modulation TPS62692YFD TW -40°C to 85°C TPS62693 2.85 800 mA peak output current Output Discharge Spread Spectrum Frequency Modulation TPS62693YFD UD -40°C to 85°C TPS62694 2.95 (4) 800 mA peak output current Output Discharge Spread Spectrum Frequency Modulation TPS62694YFD B6 -40°C to 85°C TPS62698 3.0 800 mA peak output current Output Discharge TPS62698YFD B7 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Internal tap points are available to facilitate output voltages in 25mV increments. The YFD package is available in tape and reel. Add a R suffix (e.g. TPS62692YFDR) to order quantities of 3000 parts. Add a T suffix (e.g. TPS62692YFDT) to order quantities of 250 parts. Product preview. Contact TI factory for more information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input Voltage MIN MAX UNIT Voltage at VIN (2) (3), SW (3) –0.3 6 V Voltage at FB (4) –0.3 3.6 V –0.3 VI + 0.3 V 800 (4) mA Voltage at EN, MODE (3) Peak output current, IO Power dissipation Operating temperature range, TA Internally limited (5) –40 Operating junction temperature, TJ Storage temperature range, Tstg ESD (6) (1) (2) (3) (4) (5) (6) 2 –65 85 °C 150 °C 150 °C Human body model 2 kV Charge device model 1 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operation above 4.8V input voltage is not recommended over an extended period of time. All voltage values are with respect to network ground terminal. Limited to 50% Duty Cycle over Lifetime. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 105°C. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 THERMAL INFORMATION TPS6269x THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 1.2 θJB Junction-to-board thermal resistance 22.7 ψJT Junction-to-top characterization parameter 5.7 ψJB Junction-to-board characterization parameter 22.4 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) UNITS YFD (6 PINS) 132.5 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. _ RECOMMENDED OPERATING CONDITIONS VIN Input voltage range IO Output current range L Inductance CO Output capacitance TA Ambient temperature TJ Operating junction temperature (1) MIN NOM MAX 2.3 4.8 (1) 0 800 mA 0.5 1.8 µH 10 µF –40 85 °C –40 125 °C 1 5 UNIT V Operation above 4.8V input voltage is not recommended over an extended period of time. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 50 UNIT SUPPLY CURRENT μA IQ Operating quiescent current IO = 0mA. Device not switching 21 IO = 0mA, PWM mode 3.5 I(SD) Shutdown current EN = GND 0.2 7 μA UVLO Undervoltage lockout threshold 2.05 2.1 V mA ENABLE, MODE VIH High-level input voltage VIL Low-level input voltage Ilkg Input leakage current 1 V 0.4 V Input connected to GND or VIN 0.01 1.5 μA VIN = V(GS) = 3.6V. PWM mode 165 275 mΩ VIN = V(GS) = 2.9V. PWM mode 185 350 mΩ 6 μA POWER SWITCH rDS(on) P-channel MOSFET on resistance Ilkg P-channel leakage current, PMOS rDS(on) N-channel MOSFET on resistance Ilkg N-channel leakage current, NMOS rDIS Discharge resistor for power-down sequence V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C VIN = V(GS) = 3.6V. PWM mode 140 250 mΩ VIN = V(GS) = 2.9V. PWM mode 160 330 mΩ 6 μA V(DS) = 5.5V, -40°C ≤ TJ ≤ 85°C Ω 120 2.3V ≤ VIN ≤ 4.8V. Open loop P-MOS current limit 1100 VIN = 3.6V. Closed loop Input current limit under short-circuit conditions VO shorted to ground Copyright © 2012, Texas Instruments Incorporated 1250 1500 mA 15 mA Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 mA 900 3 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 2.85V, EN = 1.8V, AUTO mode and TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Thermal shutdown 140 °C Thermal shutdown hysteresis 10 °C OSCILLATOR fSW Oscillator frequency IO = 0mA, PWM mode. 2.7 3 3.3 MHz 2.65V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 2.65V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.04×VNOM V 2.65V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PWM operation 0.98×VNOM VNOM 1.02×VNOM V 3.15V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 3.15V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.04×VNOM V 3.15V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PWM operation 0.98×VNOM VNOM 1.02×VNOM V 3.25V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 3.25V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.04×VNOM V 3.25V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PWM operation 0.98×VNOM VNOM 1.02×VNOM V 3.3V ≤ VIN ≤ 4.8V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 3.3V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V 3.3V ≤ VIN ≤ 5.5V, 0mA ≤ IO ≤ 800 mA PFM/PWM operation 0.98×VNOM VNOM 1.03×VNOM V OUTPUT TPS62692 TPS62693 Regulated DC output voltage TPS62694 VOUT TPS62698 Line regulation VIN = VO + 0.5V (min 3.3V) to 5.5V IO = 200 mA Load regulation IO = 0mA to 800 mA 0.18 %/V -0.0003 %/mA 450 kΩ IO = 1mA CO = 4.7μF X5R 6.3V 0402 65 mVPP IO = 1mA CO = 10μF X5R 6.3V 0603 25 mVPP TPS62692 IO = 1mA CO = 10μF X5R 6.3V 0603 22 mVPP TPS6269x IO = 0mA, Time from active EN to start switching 60 μs TPS62693 TPS62694 TPS62698 IO = 0mA, Time to ramp from 5% to 95% of VOUT 250 μs TPS62692 IO = 0mA, Time to ramp from 5% to 95% of VOUT 200 μs Feedback input resistance ΔVO Power-save mode ripple voltage Start-up time 4 TPS62693 TPS62694 TPS62698 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 PIN ASSIGNMENTS TPS62692 TPS62692 CSP-6 (TOP VIEW) TPS62692 CSP-6 (BOTTOM VIEW) MODE A1 A2 VIN VIN A2 A1 MODE SW B1 B2 EN EN B2 B1 SW FB C1 C2 GND GND C2 C1 FB PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. FB C1 I Output feedback sense input. Connect FB to the converter’s output. VIN A2 I Power supply input. SW B1 I/O EN B2 I This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs. This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be terminated. This is the mode selection pin of the device. This pin must not be left floating and must be terminated. MODE A1 I MODE = LOW: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced. GND C2 – Ground pin. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 5 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM MODE VIN Undervoltage Lockout Bias Supply Bandgap EN VIN Soft-Start Negative Inductor Current Detect V REF = 0.8 V Power Save Mode Switching Logic Thermal Shutdown Current Limit Detect Frequency Control R1 FB Gate Driver R2 SW Anti Shoot-Through VREF + GND PARAMETER MEASUREMENT INFORMATION TPS62693 VIN CI L VIN SW EN FB VOUT CO GND MODE List of components: • L = TOKO MDT2012CR1R0 • CI = MURATA GRM155R60J225ME15 (2.2μF, 6.3V, 0402, X5R) • CO = 2 x MURATA GRM155R60J475ME97 (4.7μF, 6.3V, 0402, X5R) 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE vs Load current (TPS62693, VOUT = 2.85V) η Efficiency vs Load current (TPS62698, VOUT = 3.0V) 5 vs Load current (TPS62692, VOUT = 2.2V) 6, 7 vs Input voltage (TPS62693, VOUT = 2.85V) vs Input voltage (TPS62692, VOUT = 2.2V) Peak-to-peak output ripple voltage vs Load current AC load transient response IQ fs rDS(on) DC output voltage 9 12 TPS62693, VOUT = 2.85V 13, 14, 15 TPS62692, VOUT = 2.2V 16, 17 TPS62693, VOUT = 2.85V 18, 19 TPS62692, VOUT = 2.2V 20, 21 vs Load current, TPS62693, VOUT = 2.85V (MODE = low) VO 8 10, 11 Combined line/load transient response Load transient response 3, 4 vs Load current, TPS62692, VOUT = 2.2V (MODE = hi) 22 23, 24 vs Load current, TPS62693, VOUT = 2.2V (MODE = low) 25 PFM/PWM boundaries vs Input voltage (TPS62693, VOUT = 2.85V) 26 Quiescent current vs Input voltage 27 PWM switching frequency vs Input voltage (TPS62693, VOUT = 2.85V) 28 PFM switching frequency vs Load current (TPS62693, VOUT = 2.85V) 29 P-channel MOSFET rDS(on) vs Input voltage 30 N-channel MOSFET rDS(on) vs Input voltage 31 PWM operation TPS62693, VOUT = 2.85V 32 Power-save mode operation TPS62693, VOUT = 2.85V 33 Spread Spectrum Frequency Modulation TPS62692, VOUT = 2.2V 34 Start-up TPS62693, VOUT = 2.85V 35, 36 Shut-Down TPS62693, VOUT = 2.85V 37 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 7 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs LOAD CURRENT 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) EFFICIENCY vs LOAD CURRENT 50 40 50 40 30 30 20 20 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 3.6V (PWM) 10 VOUT = 2.85V 0 0.1 1 10 Current (mA) 100 10 0 0.1 1000 VIN = 3.0V VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 4.5V VOUT = 2.85V MODE = Low 1 10 Current (mA) 100 1000 G000 G000 Figure 3. Figure 4. EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100.0 100.0 90.0 90.0 80.0 Efficiency (%) Efficiency (%) 80.0 70.0 60.0 50.0 70.0 VIN = 2.7V VIN = 3.0V VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 4.5V VIN = 4.8V 60.0 40.0 VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 3.6V (PWM) 30.0 VOUT = 3.0V 20.0 0.1 1 10 Current (mA) 100 50.0 VOUT = 2.2V MODE = Low 1000 40.0 0.1 1 10 Current (mA) G000 Figure 5. 8 Submit Documentation Feedback 100 1000 G000 Figure 6. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs LOAD CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 VOUT = 2.2V MODE = High 90.0 80.0 Efficiency (%) 70.0 60.0 50.0 40.0 VIN = 2.7V VIN = 3.0V VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 4.5V VIN = 4.8V 30.0 20.0 10.0 0.0 1 10 100 1000 Current (mA) G000 Figure 7. Figure 8. EFFICIENCY vs INPUT VOLTAGE PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT Figure 9. Figure 10. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 9 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE vs LOAD CURRENT COMBINED LINE/LOAD TRANSIENT RESPONSE VO = 2.85V 10mA to 400mA Load Step 3.3 to 3.9V Line Step MODE = Low Figure 11. Figure 12. LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION VI = 3.6 V, VO = 2.85V VI = 3.6 V, VO = 2.85V 5mA to 200mA Load Step 5mA to 400mA Load Step MODE = Low MODE = Low Figure 13. 10 Submit Documentation Feedback Figure 14. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION VI = 3.6 V, VO = 2.2V VI = 3.15 V, VO = 2.85V 5mA to 400mA Load Step 5mA to 400mA Load Step MODE = Low MODE = Low Figure 15. Figure 16. LOAD TRANSIENT RESPONSE IN PFM/PWM OPERATION AC LOAD TRANSIENT RESPONSE VI = 3.6 V, VO = 2.85 V VI = 2.7 V, VO = 2.2V 5mA to 400mA Load Step 5mA to 800mA Load Sweep MODE = Low MODE = Low Figure 17. Copyright © 2012, Texas Instruments Incorporated Figure 18. Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 11 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) AC LOAD TRANSIENT RESPONSE AC LOAD TRANSIENT RESPONSE VI = 3.6 V, VO = 2.2 V VI = 3.15 V, VO = 2.85 V 5mA to 800mA Load Sweep 5mA to 800mA Load Sweep MODE = Low MODE = Low Figure 19. Figure 20. AC LOAD TRANSIENT RESPONSE DC OUTPUT VOLTAGE vs LOAD CURRENT 2.93 VI = 2.7 V, VO = 2.2 V VOUT = 2.85V MODE = Low 2.91 2.90 Voltage (V) 2.88 5mA to 800mA Load Sweep 2.87 2.85 2.84 2.82 MODE = Low 2.81 2.79 0.1 VIN = 3.2V VIN = 3.6V VIN = 4.2V VIN = 4.5V 1 10 Current (mA) 100 1000 G000 Figure 21. 12 Submit Documentation Feedback Figure 22. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) DC OUTPUT VOLTAGE vs LOAD CURRENT 2.93 VOUT = 2.85V MODE = High 2.91 2.91 2.90 2.90 2.88 2.88 Voltage (V) Voltage (V) 2.93 DC OUTPUT VOLTAGE vs LOAD CURRENT 2.87 2.85 2.84 2.82 2.81 2.79 0.1 VOUT = 2.85V MODE = High 2.87 2.85 2.84 VIN = 2.9V VIN = 3.2V VIN = 3.6V VIN = 4.2V VIN = 4.8V 1 2.82 2.81 10 Current (mA) 100 1000 2.79 0.1 VIN = 2.9V (+25C) VIN = 2.9V (+85C) VIN = 3.1V (+25C) VIN = 3.1V (+85C) VIN = 3.2V (+25C) VIN = 3.2V (+85C) 1 10 Current (mA) 100 G000 2.26 G000 Figure 23. Figure 24. DC OUTPUT VOLTAGE vs LOAD CURRENT PFM/PWM BOUNDARIES VOUT = 2.2V MODE = Low Always PWM 2.24 Voltage (V) 1000 PFM to PWM Mode Change 2.22 2.20 PWM to PFM Mode Change 2.18 2.16 0.1 VIN = 2.7V VIN = 3.6V VIN = 4.2V VIN = 4.8V 1 Always PFM 10 Current (mA) 100 1000 G000 Figure 25. Copyright © 2012, Texas Instruments Incorporated Figure 26. Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 13 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) QUIESCENT CURRENT vs INPUT VOLTAGE PWM SWITCHING FREQUENCY vs INPUT VOLTAGE 50 3.2 45 3 40 2.8 Switching Frequency (MHz) Quiescent Current (µA) VOUT = 2.85V 35 30 25 20 15 10 2.4 2.2 2 1.8 1.6 Iload = 50mA Iload = 100mA Iload = 200mA Iload = 400mA Iload = 600mA Iload = 800mA 1.4 T = −40C T = +25C T = +85C 5 0 3.0 2.6 3.5 4.0 Supply Voltage (V) 4.5 1.2 1 2.9 5.0 3.1 3.3 3.5 3.7 3.9 Input Voltage (V) 4.1 4.3 4.5 G000 G000 Figure 27. Figure 28. PFM SWITCHING FREQUENCY vs INPUT VOLTAGE P-CHANNEL rDS(ON) vs INPUT VOLTAGE 275 T = −40C T = +25C T = +85C 250 R_DSON (mΩ) 225 200 175 150 125 100 75 2.5 3.0 3.5 4.0 Supply Voltage (V) 4.5 5.0 G000 Figure 29. 14 Submit Documentation Feedback Figure 30. Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) N-CHANNEL rDS(ON) vs INPUT VOLTAGE PWM OPERATION 250 T = −40C T = +25C T = +85C 225 VI = 3.6 V, VO = 2.85 V, IO = 200mA R_DSON (mΩ) 200 175 150 125 100 MODE = High 75 50 2.5 3.0 3.5 4.0 Supply Voltage (V) 4.5 5.0 G000 Figure 31. Figure 32. POWER SAVE MODE OPERATION SPREAD SPECTRUM FREQUENCY MODULATION BEHAVIOR VI = 3.6 V, VO = 2.2V IO = 200mA VI = 3.6 V, VO = 2.85 V, IO = 60mA MODE = High MODE = Low Figure 33. Copyright © 2012, Texas Instruments Incorporated Figure 34. Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 15 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) START-UP START-UP VI = 3.6 V, VO = 2.85V, Load = 8.2Ohm VI = 3.6 V, VO = 2.85V, IO = 0mA MODE = Low MODE = Low Figure 35. Figure 36. SHUT-DOWN VI = 3.6 V, VO = 2.85V, Load = 0mA MODE = High Figure 37. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 DETAILED DESCRIPTION OPERATION The TPS62692 is a synchronous step-down converter typically operates at a regulated 3-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS62692 converter operates in power-save mode with pulse frequency modulation (PFM). The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the output voltage until the main comparator trips, then the control logic turns off the switch. One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response to change in VO is essentially instantaneous, which explains the transient response. The absence of a traditional, high-gain compensated linear loop means that the TPS62692 is inherently stable over a range of L and CO. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of operating conditions. Combined with best in class load and line transient response characteristics, the low quiescent current of the device (ca. 23 μA) allows to maintain high efficiency at light load, while preserving fast transient response for applications requiring tight output regulation. SWITCHING FREQUENCY The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of 50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The intrinsic maximum operating frequency of the converter is about 5MHz to 7MHz, which is controlled to circa. 3 MHz by a frequency locked loop. When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls below 3 MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at low duty cycles. When the converter is required to operate towards the 3 MHz nominal at extreme duty cycles, the application can be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL). This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation delay, hence increasing the switching frequency. POWER-SAVE MODE If the load current decreases, the converter will enter Power Save Mode operation automatically. During powersave mode the converter operates in discontinuous current (DCM) single-pulse PFM mode, which produces low output ripple compared with other PFM architectures. When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state. PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode. As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and the transition between PFM and PWM is seamless. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 17 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com PFM Mode at Light Load PFM Ripple Nominal DC Output Voltage PWM Mode at Heavy Load Figure 38. Operation in PFM Mode and Transfer to PWM Mode MODE SELECTION The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide load current range. Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter modulates its switching frequency according to a spread spectrum PWM modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. SPREAD SPECTRUM, PWM FREQUENCY DITHERING The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that is focused on specific frequencies. Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or regulated, based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). The spread spectrum architecture varies the switching frequency by ca. ±10% of the nominal switching frequency thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 0 dBV FENV,PEAK Dfc Dfc Non-modulated harmonic F1 Side-band harmonics window after modulation 0 dBVref B = 2 × fm × (1 + mf ) = 2 × ( Dfc + fm ) Bh = 2 × fm × (1 + mf × h ) B = 2 × fm × (1 + mf ) = 2 × ( Dfc + fm ) Figure 39. Spectrum of a Frequency Modulated Sin. Wave with Sinusoidal Variation in Time Figure 40. Spread Bands of Harmonics in Modulated Square Signals (1) The above figures show that after modulation the sideband harmonic is attenuated compared to the nonmodulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the modulation index (mf) the larger the attenuation. mƒ = δ ´ ƒc ƒm (1) With: fc is the carrier frequency fm is the modulating frequency (approx. 0.008*fc) δ is the modulation ratio (approx 0.1) d= D ƒc ƒc (2) The maximum switching frequency fc is limited by the process and finally the parameter modulation ratio (δ), together with fm , which is the side-band harmonics bandwidth around the carrier frequency fc . The bandwidth of a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as: ( B = 2 ´ ¦m ´ 1 + m ¦ )=2 ´ (D ¦c + ¦m ) (3) fm < RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are added in the input filter and the measured value is higher than expected in theoretical calculations. fm > RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the measurements match with the theoretical calculations. LOW DROPOUT, 100% DUTY CYCLE OPERATION The device starts to enter 100% duty cycle mode once input and output voltage come close together. In order to maintain the output voltage, the P-channel MOSFET is turned on 100% for one or more cycles. With further decreasing VIN the high-side switch is constantly turned on, thereby providing a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: ( VINmin = VOUT max + IOUT max ´ RDS(on)max + RL (1) ) (4) Spectrum illustrations and formulae (Figure 39 and Figure 40 ) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005. See REFERENCES Section for full citation. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 19 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com With: IOUTmax = Maximum output current, plus inductor ripple current. RDS(on)max = Maximum P-channel MOSFET RDS(on). RL = Inductor DC resistance. VOUTmax = Nominal output voltage, plus maximum output voltage tolerance. ENABLE The TPS62692 device starts operation when EN is set high and starts up with the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.2 μA. In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. The TPS62692 device can actively discharge the output capacitor when it turns off. The integrated discharge resistor has a typical resistance of 100 Ω. The required time to discharge the output capacitor at the output node depends on load current and the output capacitance value. SOFT START The TPS62692 has an internal soft-start circuit that limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter. In the TPS62692, the soft start is implemented as a digital circuit increasing the switch current in steps of typically 300 mA, 700 mA, 1000 mA, and the typical switch current limit of 1250 mA. During the first phase the soft-start system progressively increases the on-time from a minimum pulse-width of 35 ns as a function of the output voltage, resulting in an current limit of approximately 300mA in this phase. The current limit transitions to the next step every 256 clocks (≈ 88us). To be able to switch from 700 mA to 1000 mA current limit step, the output voltage needs to be higher than 0.6 V (otherwise the parts keeps operating at 700 mA current limit). After the soft-start time has exceeded and the output voltage settled at its nominal value, the converter supports the full load curent. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS62692 device has an UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1 V input voltage. SHORT-CIRCUIT PROTECTION The TPS62692 integrates a P-channel MOSFET current limit to protect the device against heavy load or short circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle basis. As soon as the output voltage falls below ca. 0.4 V, the converter current limit is reduced to half of the nominal value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds approximately 0.5 V. This needs to be considered when a load acting as a current sink is connected to the output of the converter. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature again falls below typically 130°C. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 APPLICATION INFORMATION INDUCTOR SELECTION The TPS62692 series of step-down converters have been optimized to operate with an effective inductance value in the range of 0.5μH to 1.8μH and with output capacitors in the range of 4.7 μF to 10 μF. The internal compensation is optimized to operate with an output filter of L = 1 μH and CO = 4.7 μF. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the CHECKING LOOP STABILITY section. The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. V V *V DI I O DI + O DI +I ) L L L(MAX) O(MAX) 2 V L ƒ sw I with: fSW = switching frequency (4 MHz typical) L = inductor value ΔIL = peak-to-peak inductor ripple current IL(MAX) = maximum inductor current (5) In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance (DC)) and the following frequencydependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses The following inductor series from different suppliers have been used with the TPS6269x converters. Table 1. List of Inductors MANUFACTURER MURATA SERIES DIMENSIONS (in mm) LQM21PN1R0NGC 2.0 x 1.2 x 1.0 max. height LQM21PN1R5MC0 2.0 x 1.2 x 0.55 max. height FDK MIPS2012D1R0-X2 2.0 x 1.2 x 1.0 max. height TAIYO YUDEN NM2012N1R0M 2.0 x 1.2 x 1.0 max. height MDT2012-CH1R0A 2.0 x 1.2 x 1.0 max. height MDT2012-CR1R0 2.0 x 1.2 x 1.0 max. height TOKO Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 21 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com OUTPUT CAPACITOR SELECTION The advanced fast-response voltage mode control scheme of the TPS62692 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. For best performance, the device should be operated with a minimum effective output capacitance of 2μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions. A 4.7 μF or 10 μF ceramic capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions. The typical output voltage ripple is ca. 0.5% to 1.5% of the nominal output voltage VO. The output voltage ripple during PFM mode operation can be kept small. The PFM pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage. INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2 or 4.7-μF capacitor is sufficient. If the application exhibits a noisy or erratic switching frequency, the remedy should be found by experimenting with the value of the input capacitor. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between CI and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6269x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The ground pins of the dc/dc converter must be strongly connected to the PCB ground (i.e. reference potential across the system). These ground pins serve as the return path for both the control circuitry and the synchronous rectifier. Furthermore, due to its high frequency switching circuitry, it is imperative for the input capacitor to be as close to the SMPS device as possible, and that there is an unbroken ground plane under the TPS6269x and its external passives. Additionally, minimizing the area between the SW pin trace and inductor will limit high frequency radiated energy. The feed-back line should be routed away from noisy components and traces (e.g. SW line). The output capacitor carries the inductor ripple current. While not as critical as the input capacitor, an unbroken ground connection from this capacitor’s ground return to the inductor, input capacitor and SMPS device will reduce the output voltage ripple and it’s associated ESL step. This is a critical aspect to achieve best loop and frequency stability. High frequency currents tend to find their way on the ground plane along a mirror path directly beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias in the surrounding of the dc/dc converter leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the PCB (i.e. onto which the components are located). MODE CI L VIN ENABLE CO GND VOUT Figure 41. Suggested Layout (Top) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 23 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the powerdissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow into the system The maximum recommended junction temperature (TJ) of the TPS62692 devices is 105°C. The thermal resistance of the 6-pin CSP package (YFD-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum steady-state ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 160 mW. PD(MAX) = TJ(MAX) - TA 105°C - 85°C = = 160mW RqJA 125°C/W (6) REFERENCES "EMI Reduction in Switched Power Converters Using Frequency Modulation Techniques", in IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 4, NO. 3, AUGUST 2005, pp 569-576 by Josep Balcells, Alfonso Santolaria, Antonio Orlandi, David González, Javier Gago. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 PACKAGE SUMMARY CHIP SCALE PACKAGE (BOTTOM VIEW) D A2 A1 B2 B1 CHIP SCALE PACKAGE (TOP VIEW) YMDS CC A1 C1 C2 Code: E • YM — Year Month date Code • D — Day of laser mark • S — Assembly site code • CC— Chip code CHIP SCALE PACKAGE DIMENSIONS The TPS62692 device is available in an 6-bump chip scale package (YFD, NanoFree™). The package dimensions are given as: D E Max = 1.33 mm Max = 0.956 mm Min = 1.27 mm Min = 0.896 mm Spacer Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 25 PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish MSL Peak Temp Samples (3) (Requires Login) (2) TPS62693YFDR ACTIVE DSBGA YFD 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62693YFDT ACTIVE DSBGA YFD 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS626985YFDR PREVIEW DSBGA YFD 6 3000 TBD Call TI Call TI TPS626985YFDT PREVIEW DSBGA YFD 6 250 TBD Call TI Call TI TPS62698YFDR ACTIVE DSBGA YFD 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62698YFDT ACTIVE DSBGA YFD 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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