Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 TPS6213x 3V-17V 3A Step-Down Converter In 3x3 QFN Package 1 Features 3 Description • • • • • • • • • • • • • • The TPS6213X family is an easy to use synchronous step down DC-DC converter optimized for applications with high power density. A high switching frequency of typically 2.5MHz allows the use of small inductors and provides fast transient response as well as high output voltage accuracy by use of the DCSControl™ topology. 1 DCS-Control™ Topology Input Voltage Range: 3 to 17V Up to 3A Output Current Adjustable Output Voltage from 0.9 to 6V Pin-Selectable Output Voltage (nominal, + 5%) Programmable Soft Start and Tracking Seamless Power Save Mode Transition Quiescent Current of 17µA (typ.) Selectable Operating Frequency Power Good Output 100% Duty Cycle Mode Short Circuit Protection Over Temperature Protection Available in a 3 × 3 mm, QFN-16 Package With their wide operating input voltage range of 3V to 17V, the devices are ideally suited for systems powered from either a Li-Ion or other batteries as well as from 12V intermediate power rails. It supports up to 3A continuous output current at output voltages between 0.9V and 6V (with 100% duty cycle mode). The output voltage startup ramp is controlled by the soft-start pin, which allows operation as either a standalone power supply or in tracking configurations. Power sequencing is also possible by configuring the Enable and open-drain Power Good pins. In Power Save Mode, the devices draw quiescent current of about 17μA from VIN. Power Save Mode, entered automatically and seamlessly if load is small, maintains high efficiency over the entire load range. In Shutdown Mode, the device is turned off and shutdown current consumption is less than 2μA. 2 Applications • • • • • • Standard 12V Rail Supplies POL Supply from Single or Multiple Li-Ion Battery Solid-State Disk Drives Embedded Systems LDO replacement Mobile PCs, Tablet, Modems, Cameras The device, available in adjustable and fixed output voltage versions, is packaged in a 16-pin VQFN package measuring 3 × 3 mm (RGT). Device Information(1) PART NUMBER TPS6213x PACKAGE VQFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic Efficiency vs Output Current (3 .. 17)V 10μF 1.8V / 3A 1 / 2.2 µH PVIN SW AVIN VOS 0.1μF PG EN TPS62131 SS/TR 100kΩ 22μF FB 3.3nF DEF AGND FSW PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 4 8.1 8.2 8.3 8.4 8.5 8.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 9.1 Overview ................................................................... 7 9.2 Functional Block Diagram ......................................... 7 9.3 Feature Description................................................... 8 9.4 Device Functional Modes........................................ 10 10 Application and Implementation........................ 12 10.1 Application Information.......................................... 12 10.2 Typical Application ............................................... 12 10.3 System Examples ................................................. 23 11 Power Supply Recommendations ..................... 26 12 Layout................................................................... 27 12.1 Layout Guidelines ................................................. 27 12.2 Layout Example .................................................... 27 12.3 Thermal Information .............................................. 28 13 Device and Documentation Support ................. 29 13.1 13.2 13.3 13.4 13.5 Device Support .................................................... Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 30 14 Mechanical, Packaging, and Orderable Information ........................................................... 30 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2013) to Revision C Page • Added Device Information and ESD Rating tables, Feature Description section, Device Functional Modes, Programming section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 • Added "(PWM mode operation)" text string to VUVLO spec Test Conditions for clarification. ................................................. 5 • Changed second paragraph of SS/TR description for clarification. ...................................................................................... 9 Changes from Revision A (September 2012) to Revision B Page • Added device TPS62130A to data sheet Header................................................................................................................... 1 • Added device TPS62130A to Device Comparison table. ....................................................................................................... 3 • Added text to Power Good section regarding TPS63130A. ................................................................................................... 9 • Added pin option to Footnote statement for Pin-Selectable Output Voltage (DEF) section................................................... 9 • Added text to Frequency Selection (FSW) section regarding pin control............................................................................... 9 • Added text to Tracking Function section for clarification. ..................................................................................................... 16 • Added application example regarding TPS62130A device. ................................................................................................. 23 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 6 Device Comparison Table PART NUMBER (1) OUTPUT VOLTAGE (1) (2) adjustable TPS62130 adjustable TPS62130A (2) 1.8 V TPS62131 3.3 V TPS62132 5.0 V TPS62133 Contact the factory to check availability of other fixed output voltage versions. While TPS6213X has PG=High Z, TPS62130A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown. 7 Pin Configuration and Functions SW 3 PG 4 PGND VOS EN 13 Exposed Thermal Pad 5 6 7 8 DEF 2 14 FSW SW 15 AGND 1 16 FB SW PGND 16-Pin VQFN With Exposed Thermal Pad (RGT) Top View 12 PVIN 11 PVIN 10 AVIN 9 SS/TR space Pin Functions PIN (1) NO. (1) (2) (3) NAME I/O DESCRIPTION 1,2,3 SW O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. 4 PG O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pull-up resistor) 5 FB I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to connect FB to AGND on fixed output voltage versions for improved thermal performance. 6 AGND 7 FSW I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz (2) for typical operation) (3) 8 DEF I Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3) 9 SS/TR I Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing. 10 AVIN I Supply voltage for control circuitry. Connect to same source as PVIN. 11,12 PVIN I Supply voltage for power stage. Connect to same source as AVIN. Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. For more information about connecting pins, see Detailed Description and Application and Implementation sections. Connect FSW to VOUT or PG in this case. An internal pull-down resistor keeps logic level low, if pin is floating. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN NO. (1) NAME I/O DESCRIPTION 13 EN I Enable input (High = enabled, Low = disabled) (3) 14 VOS I Output voltage sense pin and connection for the control loop circuitry. 15,16 PGND Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. Exposed Thermal Pad Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability. 8 Specifications 8.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Pin voltage range (2) MIN MAX AVIN, PVIN –0.3 20 EN, SS/TR –0.3 VIN+0.3 SW –0.3 VIN+0.3 DEF, FSW, FB, PG, VOS –0.3 7 V 10 mA Power Good sink current PG UNIT V V Operating junction temperature, TJ –40 125 °C Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network ground terminal. 8.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge (1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (3) ±500 UNIT V ESD testing is performed according to the respective JESD22 JEDEC standard. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions Supply Voltage, VIN (at AVIN and PVIN) MIN MAX UNIT 3 17 V Operating free air temperature, TA –40 85 °C Operating junction temperature, TJ –40 125 °C 8.4 Thermal Information THERMAL METRIC (1) TPS6213X RGT 16 PINS RθJA Junction-to-ambient thermal resistance RθJCtop Junction-to-case(top) thermal resistance 15 RθJB Junction-to-board thermal resistance 11 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 10 RθJCbot Junction-to-case(bottom) thermal resistance 3.5 (1) 4 UNITS 29.1 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 8.5 Electrical Characteristics over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=12V and TA=25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range (1) 17 V IQ Operating quiescent current EN=High, IOUT=0mA, device not switching 17 25 µA ISD Shutdown current (2) EN=Low 1.5 4 µA 2.7 2.8 VUVLO TSD 3 Undervoltage lockout threshold Falling Input Voltage (PWM mode operation) 2.6 Hysteresis 200 Thermal shutdown temperature 160 Thermal shutdown hysteresis V mV °C 20 CONTROL (EN, DEF, FSW, SS/TR, PG) VH High level input threshold voltage (EN, DEF, FSW) VL Low level input threshold voltage (EN, DEF, FSW) ILKG Input leakage current (EN, DEF, FSW) VTH_PG Power good threshold voltage VOL_PG Power good output low IPG=–2mA ILKG_PG Input leakage current (PG) VPG=1.8V ISS/TR SS/TR pin source current 0.9 0.65 0.45 EN=VIN or GND; DEF, FSW=VOUT or GND V 0.3 V 0.01 1 µA Rising (%VOUT) 92% 95% 98% Falling (%VOUT) 87% 90% 94% 0.07 0.3 V 1 400 nA 2.5 2.7 µA VIN≥6V 90 170 VIN=3V 120 VIN≥6V 40 VIN=3V 50 2.3 POWER SWITCH High-side MOSFET ON-resistance RDS(ON) Low-side MOSFET ON-resistance ILIMF High-side MOSFET forward current limit (3) VIN =12V, TA= 25°C 3.6 4.2 70 4.9 mΩ mΩ A OUTPUT VREF Internal reference voltage (4) ILKG_FB Input leakage current (FB) TPS62130, VFB=0.8V Output voltage range (TPS62130) VIN ≥ VOUT DEF (Output voltage programming) DEF=0 (GND) VOUT DEF=1 (VOUT) VOUT+5% VOUT (1) (2) (3) (4) (5) (6) Initial output voltage accuracy 0.8 (5) 1 0.9 V 100 nA 6.0 V PWM mode operation, VIN ≥ VOUT +1V –1.8% 1.8% PWM mode operation, VIN ≥ VOUT +1V, TA = –10°C to 85°C –1.5% 1.6% Power Save Mode operation, COUT=22µF –2.3% 2.8% Load regulation (6) VIN=12V, VOUT=3.3V, PWM mode operation 0.05 %/A Line regulation (6) 3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM mode operation 0.02 %/V The device is still functional down to Under Voltage Lockout (see parameter VUVLO). Current into AVIN+PVIN pin. This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short Circuit Protection section). This is the voltage regulated at the FB pin. This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the (internal) resistive divider is included. Line and load regulation depend on external component selection and layout (see Figure 22 and Figure 23). Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 50.0 5.0 45.0 4.5 40.0 4.0 Input Current (µA) Input Current (µA) 8.6 Typical Characteristics 35.0 30.0 25°C 25.0 85°C 20.0 15.0 10.0 85°C 3.0 2.5 2.0 1.5 1.0 −40°C 5.0 0.0 0.0 3.5 3.0 6.0 −40°C 25°C 0.5 9.0 12.0 Input Voltage (V) 15.0 0.0 0.0 18.0 20.0 3.0 6.0 G001 Figure 1. Quiescent Current 9.0 12.0 Input Voltage (V) 15.0 18.0 20.0 G001 Figure 2. Shutdown Current 100.0 200.0 160.0 125°C RDSon Low−Side (mΩ) RDSon High−Side (mΩ) 180.0 140.0 120.0 85°C 100.0 25°C 80.0 60.0 −10°C −40°C 40.0 80.0 125°C 60.0 40.0 85°C 25°C −10°C 20.0 −40°C 20.0 0.0 0.0 3.0 6.0 9.0 12.0 Input Voltage (V) 15.0 18.0 20.0 Figure 3. High-Side Switch Resistance 6 Submit Documentation Feedback G001 0.0 0.0 3.0 6.0 9.0 12.0 Input Voltage (V) 15.0 18.0 20.0 G001 Figure 4. Low-Side Switch Resistance Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 9 Detailed Description 9.1 Overview The TPS6213X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5MHz or 1.25MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 4 external components. An internal current limit supports nominal output currents of up to 3A. The TPS6213X family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. 9.2 Functional Block Diagram PG Soft start Thermal Shtdwn UVLO AVIN PVIN PVIN PG control HS lim comp EN* SW SS/TR power control control logic DEF gate drive SW * SW FSW* comp LS lim VOS direct control & compensation ramp _ FB comparator + timer tON error amplifier DCS - ControlTM * This pin is connected to a pull down resistor internally (see Detailed Description section). AGND PGND PGND Figure 5. TPS62130 and TPS62130A (Adjustable Output Voltage) Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com Functional Block Diagram (continued) PG Soft start Thermal Shtdwn UVLO AVIN PVIN PVIN PG control HS lim comp EN* SW SS/TR power control control logic gate drive SW DEF* SW FSW* comp LS lim VOS direct control & compensation ramp _ FB* comparator + timer tON error amplifier DCS - ControlTM * This pin is connected to a pull down resistor internally (see Detailed Description section). AGND PGND PGND Figure 6. TPS62131/2/3 (Fixed Output Voltage) 9.3 Feature Description 9.3.1 Enable / Shutdown (EN) When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must be set externally to High or Low. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High. Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails. 9.3.2 Soft Start / Tracking (SS/TR) The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See Figure 34 and Figure 35 for typical startup operation. 8 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 Feature Description (continued) Using very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. The TPS6213X can start into a pre-biased output. During monotonic pre-biased startup, both the power MOSFETs are not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias voltage. As long as the output is below about 0.5V a reduced current limit of typically 1.6A is set internally. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup sequence as set by the SS/TR connection. A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage in both directions up and down (see Application and Implementation). 9.3.3 Power Good (PG) The TPS6213X has a built in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and maintain its specified logic low level. With TPS62130 it is high impedance when the device is turned off due to EN, UVLO or thermal shutdown. TPS62130A features PG=Low in this case and can be used to actively discharge Vout (see Figure 41). VIN must remain present for the PG pin to stay Low. See SLVA644 for application details. 9.3.4 Pin-Selectable Output Voltage (DEF) The output voltage of the TPS6213X devices can be increased by 5% above the nominal voltage by setting the DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed information on voltage margining using TPS6213X can be found in SLVA489. A pull down resistor of about 400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after initially set to Low. The resistor is disconnected if the pin is set High. 9.3.5 Frequency Selection (FSW) To get high power density with very small solution size, a high switching frequency allows the use of small external components for the output filter. However switching losses increase with the switching frequency. If efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally connected to the pin, acting the same way as at the DEF Pin (see above). 9.3.6 Under Voltage Lockout (UVLO) If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV. 9.3.7 Thermal Shutdown The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C (typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal shut down temperature. (1) Maximum allowed voltage is 7V. Therefore it's recommended to connect it to VOUT or PG, not VIN. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 9.4 Device Functional Modes 9.4.1 Pulse Width Modulation (PWM) Operation The TPS6213X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current. 9.4.2 Power Save Mode Operation The TPS6213X enters its built in Power Save Mode seamlessly if the load current decreases. This secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor current is discontinuous. In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions. TPS6213X includes a fixed on-time circuitry. An estimate for this on-time, in steady-state operation, is: t ON = VOUT × 400ns V IN (1) For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical peak inductor current in Power Save Mode can be approximated by: I LPSM ( peak ) = (V IN - VOUT ) × t ON L (2) When VIN decreases to typically 15% above VOUT, the TPS6213X won't enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode. 9.4.3 100% Duty-Cycle Operation The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off. The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as: spacing VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL ) (3) where IOUT is the output current, RDS(on) is the RDS(on) of the high-side FET and RL is the DC resistance of the inductor used. 10 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 Device Functional Modes (continued) 9.4.4 Current Limit And Short Circuit Protection The TPS6213X devices have protection against heavy load and short circuit events. If a short circuit is detected (VOUT drops below 0.5V), the current limit is reduced to 1.6A typically. If the output voltage rises above 0.5V, the device runs in normal operation again. At heavy loads, the current limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot through current, then the low-side FET switches on to allow the inductor current to decrease. The low-side current limit is typically 3.5A. The high-side FET turns on again only if the current in the low-side FET has decreased below the low side current limit threshold. The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit can be calculated as follows: spacing I peak ( typ ) = I LIMF + VL × t PD L (4) where ILIMF is the static current limit, specified in the Electrical Characteristics, L is the inductor value, VL is the voltage across the inductor (VIN - VOUT) and tPD is the internal propagation delay. spacing The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high side switch peak current can be calculated as follows: spacing I peak (typ ) = I LIMF + (VIN - VOUT )× 30ns L Copyright © 2011–2015, Texas Instruments Incorporated (5) Submit Documentation Feedback 11 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The TPS6213X is a switched mode step-down converter, able to convert a 3V to 17V input voltage into a 0.9V to 6V output voltage, providing up to 3A. It needs a minimum amount of external components. Apart from the LC output filter and the input capacitors, only the TPS62130 (TPS62130A) with adjustable output voltage needs an additional resistive divider to set the output voltage level. 10.2 Typical Application 1 / 2.2 µH (3 .. 17)V 10uF PVIN SW AVIN VOS VOUT / 3A 100k 0.1uF EN PG R1 22uF TPS62130 SS/TR FB 3.3nF DEF AGND FSW PGND R2 Figure 7. 3A Step-Down Converter for Point-Of-Load Power Supply Using TPS62130 10.2.1 Design Requirements The following design guideline provides a component selection to operate the device within the recommended operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution size and lowest output voltage ripple. For highest efficiency set FSW=High and the device operates at the lower switching frequency. For smallest solution size and lowest output voltage ripple set FSW=Low and the device operates with higher switching frequency. The typical values for all measurements are VIN=12V, VOUT=3.3V and T=25°C, using the external components of Table 1. The component selection used for measurements is given as follows: Table 1. List Of Components (1) REFERENCE DESCRIPTION IC 17V, 3A Step-Down Converter, QFN L1 2.2µH, 0.165 x 0.165 in Cin 10µF, 25V, Ceramic Standard Cout 22µF, 6.3V, Ceramic Standard Cs 3300pF, 25V, Ceramic R1 depending on Vout R2 depending on Vout R3 100kΩ, Chip, 0603, 1/16W, 1% (1) See Third-Party Products Disclaimer. 12 Submit Documentation Feedback MANUFACTURER TPS62130RGT, Texas Instruments XFL4020-222MEB, Coilcraft Standard Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 10.2.2 Detailed Design Procedure 10.2.2.1 Programming The Output Voltage While the output voltage of the TPS62130 (TPS62130A) is adjustable, the TPS62131/2/3 are programmed to fixed output voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed for output voltages from 0.9V to 6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from Equation 6. It is recommended to choose resistor values which allow a current of at least 2uA, meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy and most robust design. For applications requiring lowest current consumption, the use of fixed output voltage versions is recommended. æV ö R1 = R 2 çç OUT - 1÷÷ è V REF ø (6) In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V. 10.2.2.2 External Component Selection The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TPS6213X is optimized to work within a range of external components. The LC output filter's inductance and capacitance have to be considered together, creating a double pole, responsible for the corner frequency of the converter (see Output Filter And Loop Stability). Table 2 can be used to simplify the output filter component selection. Table 2. Recommended LC Output Filter Combinations (1) 4.7µF 10µF 22µF 47µF 100µF 200µF √ √ √ √ 2.2µH √ √ (2) √ √ √ 3.3µH √ √ √ √ 400µF 0.47µH 1µH 4.7µH (1) (2) The values in the table are nominal values. This LC combination is the standard value and recommended for most applications. spacing The TPS6213X can be run with an inductor as low as 1µH. FSW should be set Low in this case. However, for applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is recommended. More detailed information on further LC combinations can be found in SLVA463. 10.2.2.2.1 Inductor Selection The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static load conditions. spacing I L(max) = I OUT (max) + DI L(max) 2 (7) spacing Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 DI L(max) = VOUT V æ ç 1 - OUT ç V IN (max) ×ç L ×f ç (min) SW ç è www.ti.com ö ÷ ÷ ÷ ÷ ÷ ø (8) where IL(max) is the maximum inductor current, ΔIL is the Peak to Peak Inductor Ripple Current, L(min) is the minimum effective inductor value and fSW is the actual PWM Switching Frequency. spacing Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and size as well. The following inductors have been used with the TPS6213X and are recommended for use: Table 3. List Of Inductors (1) (1) (2) Type Inductance [µH] Current [A] (2) Dimensions [LxBxH] mm MANUFACTURER XFL4020-102ME_ 1.0 µH, ±20% 4.7 4 x 4 x 2.1 Coilcraft XFL4020-152ME_ 1.5 µH, ±20% 4.2 4 x 4 x 2.1 Coilcraft XFL4020-222ME_ 2.2 µH, ±20% 3.8 4 x 4 x 2.1 Coilcraft IHLP1212BZ-11 1.0 µH, ±20% 4.5 3 x 3.6 x 2 Vishay IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay SRP4020-3R3M 3.3µH, ±20% 3.3 4.8 x 4 x 2 Bourns VLC5045T-3R3N 3.3µH, ±30% 4.0 5 x 5 x 4.5 TDK See Third-Party Products Disclaimer Lower of IRMS at 40°C rise or ISAT at 30% drop. spacing The inductor value also determines the load current at which Power Save Mode is entered: I load ( PSM ) = 1 DI L 2 (9) Using Equation 8, this current level can be adjusted by changing the inductor value. 10.2.2.2.2 Capacitor Selection 10.2.2.2.2.1 Output Capacitor The recommended value for the output capacitor is 22uF. The architecture of the TPS6213X allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see SLVA463). Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low ripple. 14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 10.2.2.2.2.2 Input Capacitor For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied from the same input source, it's required to place a capacitance of 0.1uF from AVIN to AGND, to avoid potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required. 10.2.2.2.2.3 Soft Start Capacitor A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor required for a given soft-start ramp time for the output voltage is given by: spacing C SS = t SS × 2.5mA 1.25V [F ] (10) where CSS is the capacitance (F) required at the SS/TR pin and tSS is the desired soft-start ramp time (s). spacing NOTE DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. spacing 10.2.2.3 Tracking Function If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 8. spacing VFB » 0.64 × VSS / TR (11) VSS/TR [V] 1.2 0.8 0.4 0.2 0.4 0.6 0.8 VFB [V] Figure 8. Voltage Tracking Relationship Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V. If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero, independent of the tracking voltage. Figure 9 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function. spacing VOUT1 PVIN SW AVIN VOS EN PG TPS62130 SS/TR FB DEF AGND FSW PGND PVIN SW AVIN VOS VOUT2 R1 EN PG TPS62130 SS/TR R2 FB DEF AGND FSW PGND Figure 9. Sequence For Ratiometric And Simultaneous Startup spacing The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as VOUT1. A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing circuits are found in SLVA470. Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider tolerance than specified. 10.2.2.4 Output Filter And Loop Stability The devices of the TPS6213X family are internally compensated to be stable with L-C filter combinations corresponding to a corner frequency to be calculated with Equation 12: f LC = 1 2p L × C (12) Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for use. Different values may work, but care has to be taken on the loop stability which will be affected. More information including a detailed LC stability matrix can be found in SLVA463. 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 The TPS6213X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and Equation 14: spacing f zero = 1 2p × R1 × 25 pF (13) spacing f pole = 1 2p × 25 pF æ 1 1 ö ÷÷ × çç + è R1 R 2 ø (14) spacing Though the TPS6213X devices are stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in Power Save mode and/or improved transient response. An external feedforward capacitor can also be added. A more detailed discussion on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 10.2.3 Application Curves VIN=12V, VOUT=3.3V, TA=25°C, (unless otherwise noted) 100.0 100.0 90.0 90.0 80.0 70.0 VIN=12V VIN=17V Efficiency (%) Efficiency (%) 80.0 60.0 50.0 40.0 70.0 60.0 30.0 20.0 20.0 10.0 10.0 0.001 0.01 0.1 Output Current (A) 1 0.0 10 IOUT=1mA 7 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 VIN=17V 50.0 VIN=12V 40.0 20.0 10.0 10.0 1 0.0 10 IOUT=1mA 7 100.0 100.0 90.0 90.0 80.0 80.0 VIN=12V 60.0 VIN=17V VIN=5V 50.0 40.0 20.0 10.0 1 Submit Documentation Feedback IOUT=1A IOUT=100mA 8 9 10 11 12 13 14 Input Voltage (V) 15 16 17 10 IOUT=1A IOUT=100mA IOUT=10mA IOUT=1mA 40.0 10.0 0.01 0.1 Output Current (A) 17 50.0 30.0 Figure 14. Efficiency with 1.25Mhz, Vout=3.3V 18 60.0 20.0 0.001 16 70.0 30.0 0.0 0.0001 15 Figure 13. Efficiency with 2.5Mhz, Vout=5V Efficiency (%) Efficiency (%) Figure 12. Efficiency with 2.5Mhz, Vout=5V 70.0 11 12 13 14 Input Voltage (V) 40.0 30.0 0.01 0.1 Output Current (A) 10 IOUT=10mA 50.0 20.0 0.001 9 60.0 30.0 0.0 0.0001 8 Figure 11. Efficiency with 1.25MHz, Vout=5V Efficiency (%) Efficiency (%) Figure 10. Efficiency with 1.25MHz, Vout=5V 60.0 IOUT=1A IOUT=100mA 40.0 30.0 0.0 0.0001 IOUT=10mA 50.0 0.0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 15. Efficiency with 1.25Mhz, Vout=3.3V Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 60.0 VIN=12V 50.0 Efficiency (%) Efficiency (%) VIN=12V, VOUT=3.3V, TA=25°C, (unless otherwise noted) VIN=17V VIN=5V 40.0 60.0 30.0 20.0 20.0 10.0 10.0 0.001 0.01 0.1 Output Current (A) 1 0.0 10 4 100.0 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V 50.0 VIN=17V VIN=5V 40.0 20.0 10.0 0.0 10 3 100.0 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V VIN=17V 50.0 VIN=5V 40.0 20.0 10.0 Figure 20. Efficiency with 1.25Mhz, Vout=0.9V Copyright © 2011–2015, Texas Instruments Incorporated 6 7 IOUT=10mA IOUT=1mA 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) 10 IOUT=1A IOUT=100mA 40.0 10.0 1 5 50.0 20.0 0.01 0.1 Output Current (A) 4 60.0 30.0 0.001 IOUT=100mA 70.0 30.0 0.0 0.0001 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 19. Efficiency with 1.25Mhz, Vout=1.8V Efficiency (%) Efficiency (%) Figure 18. Efficiency with 1.25Mhz, Vout=1.8V 60.0 8 40.0 10.0 1 7 50.0 30.0 0.01 0.1 Output Current (A) 6 IOUT=1A 60.0 20.0 0.001 5 70.0 30.0 0.0 0.0001 IOUT=1A Figure 17. Efficiency with 2.5Mhz, Vout=3.3V Efficiency (%) Efficiency (%) Figure 16. Efficiency with 2.5Mhz, Vout=3.3V 60.0 IOUT=1mA IOUT=10mA 40.0 30.0 0.0 0.0001 IOUT=100mA 50.0 0.0 3 4 5 6 7 IOUT=10mA IOUT=1mA 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 21. Efficiency with 1.25Mhz, Vout=0.9V Submit Documentation Feedback 19 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com VIN=12V, VOUT=3.3V, TA=25°C, (unless otherwise noted) 3.40 3.40 Output Voltage (V) Output Voltage (V) VIN=17V 3.35 VIN=12V 3.30 VIN=5V 3.25 3.20 0.0001 0.001 0.01 0.1 Output Current (A) 1 Figure 22. Output Voltage Accuracy (Load Regulation) IOUT=1A IOUT=100mA 3.25 4 7 10 13 Input Voltage (V) 16 Figure 23. Output Voltage Accuracy (Line Regulation) 4 4 IOUT=2A 3.5 IOUT=3A Switching Frequency (MHz) 3.5 Switching Frequency (MHz) IOUT=10mA 3.30 3.20 10 IOUT=1mA 3.35 3 2.5 2 IOUT=0.5A IOUT=1A 1.5 1 0.5 3 2.5 2 1.5 1 0.5 0 4 6 8 10 12 Input Voltage (V) 14 16 0 18 FSW = Low 0 0.5 1 1.5 2 Output Current (A) 2.5 3 FSW = Low Figure 24. Switching Frequency vs Input Voltage Figure 25. Switching Frequency vs Output Current 6 0.05 0.04 Output Current (A) Output Voltage Ripple (V) 5.5 0.03 VIN=17V VIN=5V 0.02 4 3.5 3 2.5 25°C 85°C 2 1 VIN=12V 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 Output Current (A) 2.4 Figure 26. Output Voltage Ripple 20 −40°C 1.5 0.01 0 5 4.5 Submit Documentation Feedback 2.7 3 0.5 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) Figure 27. Maximum Output Current Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 VIN=12V, VOUT=3.3V, TA=25°C, (unless otherwise noted) 100 100 90 70 VIN=17V PSRR (dB) PSRR (dB) VIN=5V 80 VIN=12V 70 60 50 40 30 VIN=17V 60 50 40 30 20 20 VOUT=3.3V, IOUT=1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 0 VIN=12V 90 VIN=5V 80 10 100 1k 10k Frequency (Hz) VOUT=3.3V, IOUT=0.1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 100k 1M G000 0 10 100 1k 10k Frequency (Hz) 100k 1M G000 Figure 28. Power Supply Rejection Ratio, FSW=2.5Mhz Figure 29. Power Supply Rejection Ratio, FSW= 2.5MHz Figure 30. PWM-PSM-Transition (VIN=12V, VOUT=3.3 V with 50 mV/Div) Figure 31. Load Transient Response (IOUT= 0.5 to 3 to 0.5 A) Figure 32. Load Transient Response of Figure 31, Rising Edge Figure 33. Load Transient Response of Figure 31, Falling Edge Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com Figure 34. Startup Into 100mA Figure 35. Startup Into 3A Figure 36. Typical Operation In PWM Mode (IOUT=1A) Figure 37. Typical Operation In Power Save Mode (IOUT=10mA) 125 125 115 115 Free−Air Temperature (°C) Free−Air Temperature (°C) VIN=12V, VOUT=3.3V, TA=25°C, (unless otherwise noted) 105 95 85 75 0 0.5 1 1.5 2 2.5 Output Current (A) 3 3.5 TPS62130EVM L = 2.2 µH (XFL4020) Figure 38. Maximum Ambient Temperature (FSW= 2.5MHz) 22 95 85 75 65 65 55 105 Submit Documentation Feedback 55 0 2 4 6 8 Output Power (W) 10 12 TPS62130EVM L = 2.2 µH (XFL4020) Figure 39. Maximum Ambient Temperature (FSW= 2.5MHz) Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 10.3 System Examples 10.3.1 LED Power Supply The TPS62130 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62130. Figure 40 shows an application circuit, tested with analog dimming: spacing (4 .. 17) V 2.2µH 10uF PVIN SW AVIN VOS EN ADIM PG 22uF TPS62130 SS/TR 187k FB DEF AGND FSW PGND 0.1R Figure 40. Single Power LED Supply spacing The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15. spacing V FB = 0.64 × 2.5mA × R SS / TR (15) spacing The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used. More information is available in the Application Note SLVA451. spacing 10.3.2 Active Output Discharge The TPS62130A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown. Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 41). The discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability, keep the maximum current into the PG pin less than 10mA. spacing (3 .. 17)V 1 / 2.2 µH PVIN Vout / 3A SW TPS62130A AVIN 10uF 3.3nF VOS EN PG SS/TR FB DEF AGND FSW PGND R3 R1 22uF R2 Figure 41. Discharge Vout Through PG Pin with TPS62130A Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com System Examples (continued) 10.3.3 –3.3V Inverting Power Supply The TPS62130 can be used as inverting power supply by rearranging external circuitry as shown in Figure 42. As the former GND node now represents a voltage level below system ground, the voltage difference between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16). spacing V IN + VOUT £ V IN max (16) spacing 10uF 2.2µH (3 .. 13.7)V PVIN SW AVIN VOS 10uF PG EN 1.21M TPS62130 22uF FB SS/TR 3.3nF DEF AGND FSW PGND 383k -3.3V Figure 42. –3.3V Inverting Power Supply spacing The transfer function of the inverting power supply configuration differs from the buck mode transfer function, incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469. spacing 10.3.4 Various Output Voltages The following example circuits show how to use the various devices and configure the external circuitry to furnish different output voltages at 3A. spacing spacing (5 .. 17)V 10uF 5V / 3A 1 / 2.2 µH PVIN SW AVIN VOS 100k 0.1uF PG EN 22uF TPS62133 SS/TR FB 3.3nF DEF AGND FSW PGND Figure 43. 5V/3A Power Supply spacing spacing spacing 24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 System Examples (continued) (3.3 .. 17)V 3.3V / 3A 1 / 2.2 µH 10uF PVIN SW AVIN VOS 100k 0.1uF PG EN 22uF TPS62132 FB SS/TR 3.3nF DEF AGND FSW PGND Figure 44. 3.3V/3A Power Supply spacing spacing 1 / 2.2 µH (3 .. 17)V 10uF PVIN SW AVIN VOS 2.5V / 3A 100k 0.1uF PG EN 390k 22uF TPS62130 FB SS/TR 3.3nF DEF AGND FSW PGND 180k Figure 45. 2.5V/3A Power Supply spacing spacing (3 .. 17)V 10uF 1.8V / 3A 1 / 2.2 µH PVIN SW AVIN VOS 0.1uF PG EN 100k 22uF TPS62131 SS/TR FB 3.3nF DEF AGND FSW PGND Figure 46. 1.8V/3A Power Supply spacing spacing spacing Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com System Examples (continued) 1 / 2.2 µH (3 .. 17)V 10uF PVIN SW AVIN VOS 1.5V / 3A 100k 0.1uF PG EN 130k 22uF TPS62130 FB SS/TR 3.3nF DEF AGND FSW PGND 150k Figure 47. 1.5V/3A Power Supply spacing spacing 1 / 2.2 µH (3 .. 17)V 10uF PVIN SW AVIN VOS 1.2V / 3A 100k 0.1uF PG EN 75k 22uF TPS62130 FB SS/TR 3.3nF DEF AGND FSW PGND 150k Figure 48. 1.2V/3A Power Supply spacing spacing 1 / 2.2 µH (3 .. 17)V 10uF PVIN SW AVIN VOS 1V / 3A 100k 0.1uF PG EN 51k 22uF TPS62130 SS/TR FB 3.3nF DEF AGND FSW PGND 200k Figure 49. 1V/3A Power Supply spacing 11 Power Supply Recommendations The TPS6213X are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's output current needs to be rated according to the output voltage and the output current of the power rail application. 26 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 12 Layout 12.1 Layout Guidelines A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS6213X demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 50 for the recommended layout of the TPS6213X, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power line/plane as shown in Layout Example. Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g. SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the EVM Gerber data are available for download here, SLVC394. 12.2 Layout Example GND C PVIN AVIN R2 8 C 7 R1 6 5 9 4 10 3 11 2 12 1 13 CIN 14 15 PG 16 EN L1 to GND plane VOUT COUT to AGND GND Figure 50. Layout Example Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 12.3 Thermal Information Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad • Introducing airflow in the system For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and (SPRA953). The TPS6213X is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed, increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance. If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation. Experimental data, taken from the TPS62130 EVM, shows the maximum ambient temperature (without additional cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see Figure 38). 28 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 www.ti.com SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 13 Device and Documentation Support 13.1 Device Support 13.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 13.2 Documentation Support • • • • • • • • • • • Application Report, Voltage Margining Using the TPS62130 SLVA489 Application Report, Using the TPS62150 as Step-Down LED Driver With Dimming SLVA451 Application Report, Using the TPS6215x in an Inverting Buck-Boost Topology SLVA469 Application Report, Optimizing the TPS62130/40/50/60/70 Output Filter SLVA463 Application Report, TPS62130/40/50 Sequencing and Tracking SLVA470 Application Report, Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor SLVA289 Application Report, Using a Feedforward Capacitor to Improve Stability and Bandwidth of TPS62130/40/50/60/70 SLVA466 Application Report, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs SZZA017 Application Report, Semiconductor and IC Package Thermal Metrics SPRA953 User's Guide, TPS62130EVM-505, TPS62140EVM-505, and TPS62150EVM-505 Evaluation Modules SLVU437 EVM Gerber Data, SLVC394 13.2.1 Related Documentation 13.2.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS62130 Click here Click here Click here Click here Click here TPS62130A Click here Click here Click here Click here Click here TPS62131 Click here Click here Click here Click here Click here TPS62132 Click here Click here Click here Click here Click here TPS62133 Click here Click here Click here Click here Click here 13.3 Trademarks DCS-Control is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133 SLVSAG7C – NOVEMBER 2011 – REVISED JANUARY 2015 www.ti.com 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS62130ARGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PA6I TPS62130ARGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PA6I TPS62130RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PTSI TPS62130RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PTSI TPS62131RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVX TPS62131RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVX TPS62132RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVY TPS62132RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVY TPS62133RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVZ TPS62133RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62130ARGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62130RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62130RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62130RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62130RGTT QFN RGT 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 TPS62131RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62131RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62132RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62132RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62133RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS62133RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62130ARGTR QFN RGT 16 3000 552.0 367.0 36.0 TPS62130RGTR QFN RGT 16 3000 338.0 355.0 50.0 TPS62130RGTR QFN RGT 16 3000 552.0 367.0 36.0 TPS62130RGTT QFN RGT 16 250 552.0 185.0 36.0 TPS62130RGTT QFN RGT 16 250 338.0 355.0 50.0 TPS62131RGTR QFN RGT 16 3000 552.0 367.0 36.0 TPS62131RGTT QFN RGT 16 250 552.0 185.0 36.0 TPS62132RGTR QFN RGT 16 3000 552.0 367.0 36.0 TPS62132RGTT QFN RGT 16 250 552.0 185.0 36.0 TPS62133RGTR QFN RGT 16 3000 552.0 367.0 36.0 TPS62133RGTT QFN RGT 16 250 552.0 185.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated