DBV−5 D−8 www.ti.com DGQ−10 DGN−8 THS4221, THS4225 THS4222, THS4226 DGK−8 SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 LOW-DISTORTION, HIGH-SPEED, RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS FEATURES APPLICATIONS D Low-Voltage Analog-to-Digital Converter D Rail-to-Rail Output Swing D D − VO = −4.8/4.8 (RL = 2 kΩ) D High Speed Preamplifier Active Filtering Video Applications − 230 MHz Bandwidth (−3 dB, G= 1) − 975 V/µs Slew Rate THS4222 D, DGN, OR DGK PACKAGE (TOP VIEW) D Ultra-Low Distortion − HD2 = −90 dBc (f = 5 MHz, RL = 499Ω) − HD3 = −100 dBc (f = 5 MHz, RL = 499Ω) 1OUT 1IN− 1IN+ VS− D High Output Drive, IO = 100 mA (typ) D Excellent Video Performance − 40 MHz Bandwidth (0.1 dB, G = 2) − 0.007% Differential Gain − 0.007° Differential Phase 1 8 2 7 3 6 4 5 VS+ 2OUT 2IN− 2IN+ RELATED DEVICES D Wide Range of Power Supplies − VS = 3 V to 15 V D Power-Down Mode (THS4225/6) D Evaluation Module Available DESCRIPTION DEVICE DESCRIPTION THS4211 1 GHz, 800 V/µs, Vn = 7 nV/√Hz THS4271 1.4 GHz, 900 V/µs, Vn = 3 nV/√Hz OPA354 250 MHz, 150 V/µs, Vn = 6.5 nV/√Hz OPA690 500 MHz, 1800 V/µs, Vn = 5.5 nV/√Hz The THS4222 family is a set of rail-to-rail output single, and dual low-voltage, high-output swing, low-distortion high-speed amplifiers ideal for driving data converters, video switching or low distortion applications.This family of voltage feedback amplifiers can operate from a single 15-V power supply down to a single 3-V power supply while consuming only 14 mA of quiescent current per channel. In addition, the family offers excellent ac performance with 230-MHz bandwidth, 975-V/µs slew rate and harmonic distortion (THD) at –90 dBc at 5 MHz. SLEW RATE vs DIFFERENTIAL OUTPUT VOLTAGE STEP DIFFERENTIAL DRIVE CIRCUIT 1.3 kΩ 1800 5V IN+ 0.1 µF 10 µF − 2.5 V Vout− + 1.3 kΩ IN− 1 kΩ 650 Ω 1400 1200 Rise 1000 800 600 400 − 2.5 V Fall 1600 SR − Slew Rate − V/ µ s 650 Ω + THS4222 Vout+ 200 0 0 1 2 3 4 5 6 7 8 9 10 VO − Differential Output Voltage Step − V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002 − 2004, Texas Instruments Incorporated THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT 16.5 V Supply voltage, VS ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ±VS Input voltage, VI 100 mA Output current, IO 4V Differential input voltage, VID Continuous power dissipation See Dissipation Rating Table PACKAGE DISSIPATION RATINGS Maximum junction temperature, TJ 150°C Maximum junction temperature, continuous operation, long term reliability TJ (2) 125°C PACKAGE −65°C to 150°C 300°C Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds HBM ESD ratings: THS4221/5 2500 V THS4222/6 3000 V CDM MM POWER RATING(2) ΘJC (°C/W) ( ) ΘJA(1) (°C/W) TA ≤ 25°C TA = 85°C DBV (5) 55 255.4 391 mW 156 mW D (8) 38.3 97.5 1.02 W 410 mW DGN (8) (3) 4.7 58.4 1.71 W 685 mW DGK (8) 54.2 260 385 mW 154 mW 4.7 58 1.72 W 690 mW DGQ (10) (3) 1500 V (1) THS4221/5 150 V This data was taken using the JEDEC standard High-K test PCB. (2) THS4222/6 200 V Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long term reliability. (1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. (3) The THS422x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. RECOMMENDED OPERATING CONDITIONS Supply voltage voltage, (VS+ S and VS−) S ) MIN MAX Dual supply ±1.35 ±7.5 Single supply 2.7 15 VS− + 1.1 VS+ − 1.1 Input common-mode voltage range UNIT V V THS4221 AND THS4225 SINGLE PACKAGE/ORDERING INFORMATION PACKAGED DEVICES PLASTIC SMALL OUTLINE (D) PLASTIC MSOP(2) PowerPADE SOT-23(1) (DBV) SYM (DGN) THS4221D THS4221DBV BFS THS4225D — — PLASTIC MSOP(2) SYM (DGK) SYM THS4221DGN BFT THS4221DGK BHX THS4225DGN BFU THS4225DGK BFY (1) All packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (e.g., THS4221DBVT). (2) All packages are available taped and reeled. The R suffix standard quantity is 2500 (e.g., THS4221DGNR). PowerPAD is a trademark of Texas Instruments. 2 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 THS4222 AND THS4226 DUAL PACKAGE/ORDERING INFORMATION PACKAGED DEVICES (1) PLASTIC MSOP PowerPADE(1) PLASTIC MSOPE(1) PLASTIC SMALL OUTLINE (D)(1) (DGN) SYM (DGQ) SYM (DGK) SYM THS4222D THS4222DGN BFO — — THS4222DGK BHW — — — THS4226DGQ BFP — — All packages are available taped and reeled. The R suffix standard quantity is 2500 (e.g., THS4222DGNR). ELECTRICAL CHARACTERISTICS VS = ±5 V, RL = 499 Ω, and G = 1 unless otherwise noted PARAMETER TEST CONDITIONS TYP OVER TEMPERATURE 25°C 0°C to 70°C 25°C −40°C to 85°C UNITS MIN/ MAX AC PERFORMANCE G = 1, PIN = −7 dBm 230 MHz Typ G = 2, PIN = −13 dBm, Rf = 1.3 kΩ 100 MHz Typ G = 5, PIN = −21 dBm, Rf = 2 kΩ 25 MHz Typ G = 10, PIN = −27 dBm, Rf = 2 kΩ 12 MHz Typ 0.1 dB flat bandwidth G = 2, PIN = −13 dBm, Rf = 1.3 kΩ 40 MHz Typ Gain bandwidth product G > 10, f = 1 MHz, Rf = 2 kΩ 120 MHz Typ Full-power bandwidth G = 1, VO = ±2.5 V 65 MHz Typ G = −1, VO = ±2.5 Vpp 990 V/µs Min G = 1, VO = ±2.5 Vpp 975 V/µs Min Settling time to 0.1% G = −1, VO = ±2 Vpp 25 ns Typ Settling time to 0.01% G = −1, VO = ±2 Vpp 52 ns Typ Harmonic distortion G = 1, VO = 2 VPP, f = 5 MHz RL = 499 Ω −90 dBc Typ RL = 150 Ω −92 dBc Typ RL = 499 Ω −100 dBc Typ RL = 150 Ω −96 dBc Typ % Typ Small signal bandwidth Slew rate Second harmonic distortion Third harmonic distortion Differential gain (NTSC, PAL) G = 2, R = 150 Ω 0.007 Differential phase (NTSC, PAL) G = 2, R = 150 Ω 0.007 ° Typ Input voltage noise f = 1 MHz 13 nV/√Hz Typ Input current noise f = 1 MHz 0.8 pA/√Hz Typ Crosstalk (dual only) f = 5 MHz Ch-to-Ch −90 dB Typ Open-loop voltage gain (AOL) VO = ±2 V 100 80 75 75 dB Min Input offset voltage VCM = 0 V 3 10 16 16 mV Max ±20 ±20 µV/_C Typ Max DC PERFORMANCE Average offset voltage drift Input bias current Average offset voltage drift Input offset current Average offset current drift VCM = 0 V VCM = 0 V 0.9 3 VCM = 0 V VCM = 0 V 100 500 VCM = 0 V 5 5 µA ±10 ±10 µV/_C Typ 700 700 nA Max ±10 ±10 nA/_C Typ V Min 69 69 dB Min INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio VCM = ±2 V Input resistance Input capacitance Common-mode / differential −4 / 4 −3.9 / 3.9 94 74 33 MΩ Typ 1 / 0.5 pF Max 3 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = ±5 V, RL = 499 Ω, and G = 1 unless otherwise noted TYP OVER TEMPERATURE 25°C 25°C 0°C to 70°C −40°C to 85°C UNITS MIN/ MAX RL = 499 Ω −4.7 / 4.7 −4.5 / 4.5 −4.4 / 4.4 −4.4 / 4.4 V Min PARAMETER TEST CONDITIONS OUTPUT CHARACTERISTICS Output voltage swing RL = 2 kΩ −4.8 / 4.8 V Min Output current (sourcing) RL = 10 Ω 100 92 88 88 mA Min Output current (sinking) RL = 10 Ω −100 −92 −88 −88 mA Min Output impedance f = 1 MHz 0.02 Ω Typ POWER SUPPLY Specified operating voltage Maximum quiescent current Per channel Power supply rejection (±PSRR) ±5 ±7.5 ±7.5 ±7.5 V Max 14 18 20 22 mA Max 75 62 60 60 dB Min 700 900 1000 1000 µA Max POWER-DOWN CHARACTERISTICS Maximum power-down current Power down voltage level(1) Power-down PD ≤ REF +1.0 V, REF = 0 V, Per channel REF = 0 V V, or VS− S REF = VS+ S or floating Enable Power down Enable Power down REF+1.8 V Min REF+1 V Max REF−1 V Min REF−1.5 V Max Turnon time delay 50% of final value 200 ns Typ Turnoff time delay 50% of final value 500 ns Typ 58 Ω Typ 80 dB Typ Input impedance Isolation (1) 4 f = 5 MHz For detail information on the power-down circuit, refer to the powerdown section in the application information of this data sheet. THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = 5 V, RL = 499 Ω, and G = 1 unless otherwise noted TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C to 70°C −40°C to 85°C UNITS MIN/ MAX AC PERFORMANCE Small signal bandwidth G = 1, PIN = −7 dBm 200 MHz Typ G = 2, PIN = −13 dBm, Rf = 1.3 kΩ 100 MHz Typ G = 5, PIN = −21 dBm, Rf = 2 kΩ 25 MHz Typ G = 10, PIN = −27 dBm, Rf = 2 kΩ 12 MHz Typ 0.1 dB flat bandwidth G = 2, PIN = −13 dBm, Rf = 1.3 kΩ 50 MHz Typ Gain bandwidth product G > 10, f = 1 MHz, Rf = 2 kΩ 120 MHz Typ Full-power bandwidth G = 1, VO = ±2 V 40 MHz Typ G = −1, VO = ±2 Vpp 500 V/µs Min G = 1, VO = ±2 Vpp 550 V/µs Min Settling time to 0.1% G = −1, VO = ±1 Vpp 27 ns Typ Settling time to 0.01% G = −1, VO = ±1 Vpp 48 ns Typ Harmonic distortion G = 1, VO = 2 VPP, f = 5 MHz RL = 499 Ω −90 dBc Typ RL = 150 Ω −93 dBc Typ RL = 499 Ω −89 dBc Typ Slew rate Second harmonic distortion Third harmonic distortion −91 dBc Typ Differential gain (NTSC, PAL) RL = 150 Ω G = 2, R = 150 Ω 0.014 % Typ Differential phase (NTSC, PAL) G = 2, R = 150 Ω 0.011 ° Typ Input voltage noise f = 1 MHz 13 nV/√Hz Typ Input current noise f = 1 MHz 0.8 pA/√Hz Typ Crosstalk (dual only) f = 5 MHz Ch-to-Ch −90 dB Typ Open-loop voltage gain (AOL) VO = 1.5 V to 3.5 V 100 80 75 75 dB Min Input offset voltage VCM = 2.5 V 3 10 16 16 mV Max ±20 ±20 µV/_C Typ 0.9 3 5 5 µA Max ±10 ±10 µV/_C Typ 100 500 700 700 nA Max ±10 ±10 nA/_C Typ V Min 69 69 dB Min DC PERFORMANCE Average offset voltage drift Input bias current Average offset voltage drift Input offset current Average offset current drift VCM = 2.5 V VCM = 2.5 V VCM = 2.5 V VCM = 2.5 V VCM = 2.5 V INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio VCM = 1.5 V to 3.5 V Input resistance Input capacitance Common-mode / differential 1/4 1.1 / 3.9 96 74 33 MΩ Typ 1 / 0.5 pF Max V Min V Min OUTPUT CHARACTERISTICS Output voltage swing RL = 499 Ω 0.2 / 4.8 RL = 2 kΩ 0.1 / 4.9 0.3 / 4.7 0.4 / 4.6 0.4 / 4.6 Output current (sourcing) RL = 10 Ω 95 85 80 80 mA Min Output current (sinking) RL = 10 Ω −95 −85 −80 −80 mA Min Output impedance f = 1 MHz 0.02 Ω Typ 5 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS (continued) VS = 5 V, RL = 499 Ω, and G = 1 unless otherwise noted TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE 25°C 25°C 0°C to 70°C −40°C to 85°C UNITS MIN/ MAX POWER SUPPLY Specified operating voltage Maximum quiescent current Per channel Power supply rejection (±PSRR) 5 15 15 15 V Max 12 15 17 19 mA Max 70 62 60 60 dB Min 500 750 900 900 µA Max POWER-DOWN CHARACTERISTICS Maximum power-down current Power down voltage level(1) Power-down PD ≤ REF +1.0 V, REF = 0 V, Per channel REF = 0 V V, or VS− S REF = VS+ S or floating Enable Power down Enable Power down REF+1.8 V Min REF+1 V Max REF−1 V Min REF−1.5 V Max Turnon time delay 50% of final value 200 ns Typ Turnoff time delay 50% of final value 500 ns Typ 58 Ω Typ 80 dB Typ Input impedance Isolation (1) 6 f = 5 MHz For detail information on the power-down circuit, refer to the powerdown section in the application information of this data sheet. THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS VS = 3.3 V, RL = 499 Ω, and G = 1 unless otherwise noted TYP PARAMETER TEST CONDITIONS 25°C OVER TEMPERATURE 25°C 0°C to 70°C −40°C to 85°C UNITS MIN/ MAX AC PERFORMANCE Small signal bandwidth G = 1, PIN = −7 dBm 200 MHz Typ G = 2, PIN = −13 dBm, Rf = 1 kΩ 100 MHz Typ G = 5, PIN = −21 dBm, Rf = 2 kΩ 15 MHz Typ G = 10, PIN = −27 dBm, Rf = 2 kΩ 12 MHz Typ 0.1 dB flat bandwidth G = 2, PIN = −13 dBm, Rf = 1 kΩ 50 MHz Typ Gain bandwidth product G > 10, f = 1 MHz, Rf = 1.5 kΩ 120 MHz Typ Full-power bandwidth G = 1, VO = 1.3 V to 2 V 50 MHz Typ G = −1, VO = 1.3 V to 2 V 120 V/µs Min G = 1, VO = 1.3 V to 2V 250 V/µs Min RL = 499 Ω −80 dBc Typ RL = 150 Ω −79 dBc Typ RL = 499 Ω −91 dBc Typ RL = 150 Ω −92 dBc Typ Input voltage noise f = 1 MHz 13 nV/√Hz Typ Input current noise f = 1 MHz 0.8 pA/√Hz Typ Crosstalk (dual only) f = 5 MHz Ch-to-Ch −90 dB Typ Open-loop voltage gain (AOL) VO = 1.35 V to 1.95 V 98 80 75 75 dB Min Input offset voltage VCM = 1.65 V 3 10 16 16 mV Max ±20 ±20 µV/_C Typ 0.9 3 5 5 µA Max ±10 ±10 µV/_C Typ 100 500 700 700 nA Max ±10 ±10 nA/_C Typ V Min 69 69 dB Min Slew rate Harmonic distortion Second harmonic distortion Third harmonic distortion G = 2, VO = 1 VPP, f = 5 MHz DC PERFORMANCE Average offset voltage drift Input bias current Average offset voltage drift Input offset current Average offset current drift VCM = 1.65 V VCM = 1.65 V VCM = 1.65 V VCM = 1.65 V VCM = 1.65 V INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio VCM = 1.35 V to 1.95 V Input resistance Input capacitance Common-mode / differential 1 / 2.3 1.1/2.2 92 74 33 MΩ Typ 1 / 0.5 pF Max OUTPUT CHARACTERISTICS Output voltage swing RL = 499 Ω 0.15/3.15 0.3/3.0 0.35/2.95 0.35/2.95 V Min Output voltage swing RL = 2 kΩ 0.1 / 3.2 Output current (sourcing) RL = 20 Ω V Min 50 45 40 40 mA Output current (sinking) Min RL = 20 Ω −50 −45 −40 −40 mA Output impedance Min f = 1 MHz 0.02 Ω Typ 7 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS (continued) VS = 3.3 V, RL = 499 Ω, and G = 1 unless otherwise noted TYP PARAMETER TEST CONDITIONS OVER TEMPERATURE 25°C 25°C 0°C to 70°C −40°C to 85°C 3.3 15 15 11 13 16 65 60 500 700 UNITS MIN/ MAX 15 V Max 17 mA Max 55 55 dB Min 800 800 µA Max POWER SUPPLY Specified operating voltage Maximum quiescent current Per channel Power supply rejection (±PSRR) POWER-DOWN CHARACTERISTICS Maximum power-down current Power down voltage level(1) Power-down PD ≤ REF +1.0 V, REF = 0 V, Per channel REF = 0 V V, or VS− S REF = VS+ S or floating Enable Power down Enable Power down REF+1.8 V Min REF+1 V Max REF−1 V Min REF−1.5 V Max Turnon time delay 50% of final value 200 ns Typ Turnoff time delay 50% of final value 500 ns Typ 58 Ω Typ 80 dB Typ Input impedance Isolation (1) 8 f = 5 MHz For detail information on the power-down circuit, refer to the powerdown section in the application information of this data sheet. THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 PIN ASSIGNMENTS NON-POWER DOWN PACKAGE DEVICES THS4221 D, DGN, OR DGK PACKAGE (TOP VIEW) THS4221 DBV PACKAGE (TOP VIEW) VOUT VS− IN+ 1 5 NC IN− IN+ VS− VS+ 2 3 4 IN − 1 8 2 7 3 6 4 5 THS4222 D, DGN, OR DGK PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VS− NC VS+ VOUT NC 1 8 2 7 3 6 4 5 VS+ 2OUT 2IN− 2IN+ NC − No internal connection POWER-DOWN PACKAGE DEVICES THS4226 DGQ PACKAGE (TOP VIEW) THS4225 D, DGN, OR DGK PACKAGE (TOP VIEW) REF IN− IN+ VS− 1 8 2 7 3 6 4 5 PD VS+ VOUT NC 1OUT 1IN− 1IN+ VS− 1PD 1 2 3 4 5 10 9 8 7 6 VS+ 2OUT 2IN− 2IN+ 2PD NC − No internal connection 9 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Small signal frequency response 1 Slew rate vs Output voltage step 2, 3 Harmonic distortion vs Frequency 4, 5, 8, 9 Harmonic distortion vs Output voltage swing 6, 7 Voltage and current noise vs Frequency 10 Differential gain vs Number of loads 11, 13 Differential phase vs Number of loads 12, 14 Quiescent current vs Supply voltage 15 Output voltage vs Load resistance 16 Open-loop gain and phase vs Frequency 17 Open-loop gain vs Supply voltage 18 Rejection ratio vs Frequency 19 Rejection ratio vs Case temperature 20 Common-mode rejection ratio vs Input common-mode range 21, 22 Input offset voltage vs Case temperature 23 Input bias and offset current vs Case temperature 24, 25 Power-down quiescent current vs Supply voltage 26 Output impedance in power down vs Frequency 27 Crosstalk vs Frequency 28 SLEW RATE vs OUTPUT VOLTAGE STEP SMALL SIGNAL FREQUENCY RESPONSE Gain = 10, Rf = 2 kΩ Small Signal Gain − dB 18 16 14 12 10 8 Gain = 2, Rf = 1.3 kΩ 6 4 800 1 Fall 600 Rise 400 0 0.1 10 100 f − Frequency − MHz Figure 1 1k Gain = −1 RL = 499 Ω Rf = 1.3 kΩ VS = ±5 V 500 200 Gain = 1, Rf = 0 0 −2 600 Gain = 1 RL = 499 Ω Rf = 1.3 kΩ VS = ±5 V 1000 Gain = 5, Rf = 2 kΩ 2 10 1200 RL = 499 Ω POUT = −7 dBm VS = ±5 V SR − Slew Rate − V/ µ s 20 SR − Slew Rate − V/ µ s 22 SLEW RATE vs OUTPUT VOLTAGE STEP 400 Fall 300 Rise 200 100 0 1 2 3 4 VO − Output Voltage Step − V Figure 2 5 0 0 0.5 1 1.5 VO − Output Voltage Step − V Figure 3 2 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY 0 Gain = 1 RL = 150 Ω VO = 2 VPP VS = ±5 V −30 −40 −50 −60 HD2 −70 −20 Harmonic Distortion − dBc −80 −30 −40 −50 −60 −70 HD2 −80 HD3 −90 HD3 −90 0.1 1 10 f − Frequency − MHz 0.1 100 1 10 f − Frequency − MHz Figure 4 −40 −50 −60 −80 100 −40 HD3, 5 V HD3, ±5 V −60 −70 HD2, ±5 V −80 −20 −30 −50 −60 −70 0 HD3 −80 4.5 5 −100 0.1 1 Hz I n − Current Noise − pA/ 10 1 In 0.20 −60 −70 10 HD3 −80 HD2 −90 100 −100 0.1 1 0.16 0.14 VS = ±5 V 1M f − Frequency − Hz 0.1 10 M 0 0.3 0.25 0.2 0.15 0.1 0.05 0.02 1 Gain = 2 Rf = 1.5 kΩ 40 IRE − NTSC Worst Case ±100 IRE Ramp 0.35 VS = 5 V 0.04 DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.4 0.10 0.06 100 Figure 9 0.12 0.08 10 f − Frequency − MHz Gain = 2 Rf = 1.5 kΩ 40 IRE − NTSC Worst Case ±100 IRE Ramp 0.18 Differential Gain − % Hz Vn − Voltage Noise − nV/ Vn Figure 10 −50 DIFFERENTIAL GAIN vs NUMBER OF LOADS 10 100 100 k −40 Figure 8 VOLTAGE AND CURRENT NOISE vs FREQUENCY 10 k −30 f − Frequency − MHz Figure 7 1k Gain = 1 RL = 499 Ω VO = 2 VPP VS = 5 V −20 HD2 −90 0.5 1 1.5 2 2.5 3 3.5 4 VO − Output Voltage Swing − V 4.5 5 0 −10 −40 HD2, 5 V −90 0.5 1 1.5 2 2.5 3 3.5 4 VO − Output Voltage Swing − V HARMONIC DISTORTION vs FREQUENCY Harmonic Distortion − dBc −30 −50 0 Figure 6 Gain = 1 RL = 150 Ω VO = 2 VPP VS = 5 V −10 Harmonic Distortion − dBc −20 HD3, ±5 V −100 0 Gain = 1 RL = 499 Ω f= 30 MHz HD2, ±5 V and 5 V HD3, 5 V −70 HARMONIC DISTORTION vs FREQUENCY 0 −10 Harmonic Distortion − dBc −30 Figure 5 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING −100 −20 −90 −100 −100 Gain = 1 RL = 499 Ω f = 8 MHz −10 Differential Phase − ° Harmonic Distortion − dBc −20 0 Gain = 1 RL = 499 Ω VO = 2 VPP VS = ±5 V −10 Harmonic Distortion − dBc 0 −10 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 0 1 2 3 Number of Loads − 150 Ω Figure 11 4 5 0 1 2 3 4 5 Number of Loads − 150 Ω Figure 12 11 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 DIFFERENTIAL GAIN vs NUMBER OF LOADS 0.14 0.12 0.10 VS = 5 V 0.08 0.06 0.04 0.2 0.15 0.1 3 4 5 10 5 110 4 100 0 1 3 2 TA = −40 to 85°C −1 −2 −3 −4 100 1k RL − Load Resistance − Ω 90 10 k 6 4 Rejection Ratio − dB CMMR PSRR 40 30 20 140 60 120 50 100 40 80 30 60 20 40 10 20 4 4.5 5 100 100 95 0 −20 1000 90 1.5 2 2.5 3 3.5 4 4.5 VS − Supply Voltage − ±V Figure 18 COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE REJECTION RATIO vs CASE TEMPERATURE VS = ±5 V, 5 V, and 3.3 V CMMR 80 PSRR 70 60 40 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 TC − Case Temperature − °C Figure 20 3.5 180 50 Figure 19 3 TA = 25°C 200 10 100 2.5 OPEN-LOOP GAIN vs SUPPLY VOLTAGE 105 220 160 90 1 10 f − Frequency − MHz 2 Figure 15 70 100 60 0 0.1 1.5 VS − Supply Voltage − ±V 80 VS = ±5 V, 5 V, and 3.3 V 80 50 0 5 Figure 17 REJECTION RATIO vs FREQUENCY 70 4 VS = ±5 V, 5 V, and 3.3 V Figure 16 100 3 0 −10 0.0001 0.001 0.01 0.1 1 10 f − Frequency − MHz −5 10 2 OPEN-LOOP GAIN AND FHASE vs FREQUENCY 90 0 TA = −40°C 8 Figure 14 Open-Loop Gain − dB VO − Output Voltage − V 12 Number of Loads − 150 Ω OUTPUT VOLTAGE vs LOAD RESISTANCE 1 TA = 25°C 14 Open-Loop Gain − dB 2 Phase − ° 1 Figure 13 12 16 2 CMRR − Common-Mode Rejection Ratio − dB 0 0 TA = 85°C 18 0.05 Number of Loads − 150 Ω Rejection Ratios − dB 20 0.25 VS = ±5 V 0.02 0 0.3 QUIESCENT CURRENT vs SUPPLY VOLTAGE 22 Gain = 2 Rf = 1.5 kΩ 40 IRE − PAL Worst Case ±100 IRE Ramp 0.35 Differential Phase − ° 0.16 Differential Gain − % 0.4 Gain = 2 Rf = 1.5 kΩ 40 IRE − PAL Worst Case ±100 IRE Ramp 0.18 Quiescent Current − mA/Ch 0.20 DIFFERENTIAL PHASE vs NUMBER OF LOADS 100 90 80 70 60 50 40 30 20 10 VS = 5 V TA = 25°C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VICR − Input Common-Mode Voltage Range − V Figure 21 5 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 100 4 90 70 60 50 40 30 20 VS = ±5 V TA = 25°C −6 −4 −2 0 2 4 3 VS = 5 V 2.5 2 1.5 1 0.5 VS = ±5 V 0 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 6 VICR − Input Common-Mode Voltage Range − V Case Temperature − °C Figure 22 Figure 23 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 0.82 IOS 0.8 10 0.9 5 0.88 0 IIB+ 0.78 −5 IIB− 0.76 −10 0.74 −15 0.72 −20 I IB − Input Bias Current − µ A VS = 5 V I OS − Input Offset Current − µ A I IB − Input Bias Current − µ A 0.84 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE −25 0.7 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 5 VS = ±5 V 0 IOS 0.86 −5 IIB+ 0.84 0.82 −15 0.8 0.78 −25 −30 0.76 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 Case Temperature − °C Figure 24 Figure 25 OUTPUT IMPEDANCE IN POWER DOWN vs FREQUENCY TA = 25°C 600 TA = −40°C 500 400 300 200 2400 2000 100 Crosstalk − dB TA = 85°C 700 1600 1200 1.5 2 2.5 3 3.5 4 VS − Supply Voltage − ±V Figure 26 4.5 5 0 0.1 PD Crosstalk all Channels 80 60 40 800 20 400 100 0 Gain = 2 RL = 499 Ω Rf = 1.5 kΩ PIN = 1 dBm VS = ±5 V 2800 800 CROSSTALK vs FREQUENCY 120 3200 900 RO − Output Impedance − Ω Power-Down Quiescent Current − µ A/Ch 1000 −20 IIB− Case Temperature − °C POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE −10 I OS − Input Offset Current − µ A 10 0 INPUT OFFSET VOLTAGE vs CASE TEMPERATURE 3.5 80 VOS − Input Offset Voltage − mV CMRR − Common-Mode Rejection Ratio − dB COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE VS = ±5 V, 5 V, and 3.3 V Gain = 1 RL = 499 Ω VIN= −1 dB TA = 25°C Crosstalk all Channels 1 10 f − Frequency − MHz Figure 27 100 1k 0 0.1 1 10 100 1k f − Frequency − MHz Figure 28 13 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 APPLICATION INFORMATION HIGH-SPEED OPERATIONAL AMPLIFIERS The THS4222 family of operational amplifiers is a family of single and dual, rail-to-rail output voltage feedback amplifiers. The THS4222 family combines both a high slew rate and a rail-to-rail output stage. 5V +VS + 100 pF 50 Ω Source + VI The THS4225 and THS4226 provides a power-down mode, providing the ability to save power when the amplifier is inactive. A reference pin is provided to allow the user the flexibility to control the threshold levels of the power-down control pin. D D D D D D D D D D Wideband, Noninverting Operation Wideband, Inverting Gain Operation Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin Power Supply Decoupling Techniques and Recommendations Driving an ADC With the THS4222 Active Filtering With the THS4222 An Abbreviated Analysis of Noise in Amplifiers Driving Capacitive Loads Printed Circuit Board Layout Techniques for Optimal Performance Power Dissipation and Thermal Considerations Evaluation Fixtures, Spice Models, and Applications Support Additional Reference Material Mechanical Package Drawings _ Figure 29 is the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. Voltage feedback amplifiers, unlike current feedback designs, can use a wide range of resistors values to set their gain with minimal impact on their stability and frequency response. Larger-valued resistors decrease the loading effect of the feedback network on the output of the amplifier, but this enhancement comes at the expense of additional noise and potentially lower bandwidth. Feedback resistor values between 1 kΩ and 2 kΩ are recommended for most situations. 14 499 Ω Rf 1.3 kΩ 1.3 kΩ Rg 0.1 µF 6.8 µF 100 pF −5 V + −VS Figure 29. Wideband, Noninverting Gain Configuration WIDEBAND, INVERTING OPERATION Since the THS4222 family are general-purpose, wideband voltage-feedback amplifiers, several familiar operational amplifier applications circuits are available to the designer. Figure 30 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 29 are retained in an inverting circuit configuration. Inverting operation is one of the more common requirements and offers several performance benefits. The inverting configuration shows improved slew rates and distortion due to the pseudo-static voltage maintained on the inverting input. 5V WIDEBAND, NONINVERTING OPERATION The THS4222 is a family of unity gain stable rail-to-rail output voltage feedback operational amplifiers, with and without power-down capability, designed to operate from a single 3-V to 15-V power supply. VO THS4222 49.9 Ω Applications Section Contents D D D D 0.1 µF 6.8 µF +VS + 100 pF 0.1 µF 6.8 µF + RT 649 Ω CT 0.1 µF 50 Ω Source VI VO THS4222 _ 499 Ω Rg Rf 1.3 kΩ RM 52.3 Ω 1.3 kΩ 0.1 µF 100 pF −5 V 6.8 µF + −VS Figure 30. Wideband, Inverting Gain Configuration THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting Rg to 49.9 Ω for input matching eliminates the need for RM but requires a 100-Ω feedback resistor. This has an advantage of the noise gain becoming equal to 2 for a 50-Ω source impedance—the same as the noninverting circuit in Figure 29. However, the amplifier output now sees the 100-Ω feedback resistor in parallel with the external load. To eliminate this excessive loading, it is preferable to increase both Rg and Rf, values, as shown in Figure 30, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of Rg and RM. The last major consideration to discuss in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input. If the resistance is set equal to the total dc resistance looking out of the inverting terminal, the output dc error, due to the input bias currents, is reduced to (input offset current) multiplied by Rf in Figure 30, the dc source impedance looking out of the inverting terminal is 1.3 kΩ || (1.3 kΩ + 25.6 Ω) = 649 Ω. To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, and power-supply feedback, RT is bypassed with a capacitor to ground. SINGLE SUPPLY OPERATION The THS4222 is designed to operate from a single 3-V to 15-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 31 demonstrate methods to configure an amplifier in a manner conducive for single supply operation. +VS 50 Ω Source + VI RT 49.9 Ω THS4222 VO _ 499 Ω +VS Rf 2 Rg 1.3 kΩ 1.3 kΩ +VS 2 50 Ω Source VI 52.3 Ω Rf VS Rg 1.3 kΩ _ 1.3 kΩ RT +VS +VS 2 2 THS4222 + VO 499 Ω Figure 31. DC-Coupled Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin The THS4225 and THS4226 feature a power-down pin (PD) which lowers the quiescent current from 14 mA/ch down to 700 µA/ch, ideal for reducing system power. The power-down pin of the amplifiers defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the negative rail. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the Enable Threshold Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a highimpedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The time delays are on the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. 15 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 Power-Down Reference Pin Operation In addition to the power-down pin, the THS4225 features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. Operation of the reference pin as it relates to the power-down pin is described below. In most split-supply applications, the reference pin is connected to ground. In some cases, the user may want to connect it to the negative or positive supply rail. In either case, the user needs to be aware of the voltage level thresholds that apply to the power-down pin. The tables below show examples and illustrate the relationship between the reference voltage and the power-down thresholds. POWER-DOWN THRESHOLD VOLTAGE LEVELS (REF ≤ Midrail) SUPPLY VOLTAGE (V) ±5 REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) GND ≥ 1.8 ≤1 −2.5 ≥ −0.7 ≤ −1.5 −5 ≥ −3.2 ≤ −4 GND ≥ 1.8 ≤1 5 1 ≥ 2.8 ≤2 2.5 ≥ 4.3 ≤ 3.5 3.3 GND ≥ 1.8 ≤1 In the above table, the threshold levels are derived by the following equations: REF + 1.8 V for enable REF + 1 V for disable Note that in order to maintain these threshold levels, the reference pin can be any voltage between Vs− or GND up to Vs/2 (mid rail). For 3.3-V operation, the reference pin must be connected to the most negative rail (for single supply this is GND). POWER-DOWN THRESHOLD VOLTAGE LEVELS (REF > Midrail) SUPPLY VOLTAGE (V) ±5 16 REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) Floating or 5 ≥4 ≤ 3.5 2.5 ≥ 1.5 ≤1 1 ≥0 ≤ −0.5 Floating or 5 ≥4 ≤ 3.5 5 4 ≥3 ≤ 2.5 3.5 ≥ 2.5 ≤2 3.3 Floating or 3.3 ≥ 2.7 ≤ 1.8 In the above table, the threshold levels are derived by the following equations: REF − 1 V for enable REF − 1.5 V for disable Note that in order to maintain these threshold levels, the reference pin can be any voltage between (Vs+/2) + 1 V to Vs+ or left floating. The reference pin is internally connected to the positive rail, therefore it can be left floating to maintain these threshold levels. For 3.3-V operation, the reference pin must be connected to the positive rail or left floating. The recommended mode of operation is to tie the reference pin to midrail, thus setting the threshold levels to midrail +1.0 V and midrail +1.8 V. NO. OF CHANNELS PACKAGES Single (8-pin) THS4225D, THS4225DGN Power Supply Decoupling Techniques and Recommendations Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. 2. Placement priority should put the smallest valued capacitors closest to the device. 3. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths, with the exception of the areas underneath the input and output pins. 4. Recommended values for power supply decoupling include a bulk decoupling capacitor (6.8 to 22 µF), a mid-range decoupling capacitor (0.1 µF) and a high frequency decoupling capacitor (1000 pF) for each supply. A 100 pF capacitor can be used across the supplies as well for extremely high frequency return currents, but often is not required. THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 APPLICATION CIRCUITS Driving an Analog-to-Digital Converter With the THS4222 The THS4222 can be used to drive high-performance analog-to-digital converters. Two example circuits are presented below. The first circuit uses a wideband transformer to convert a single-ended input signal into a differential signal. The differential signal is then amplified and filtered by two THS4222 amplifiers. This circuit provides low intermodulation distortion, suppressed even-order distortion, 14 dB of voltage gain, a 50-Ω input impedance, and a single-pole filter at 25 MHz. For applications without signal content at dc, this method of driving ADCs can be very useful. Where dc information content is required, the THS4500 family of fully differential amplifiers may be applicable. performance can sometimes be achieved with single-ended input drive. An example circuit is shown here for reference. + VI _ −5 V 1.3 kΩ 24.9 Ω ADS807 4.7 pF 237 Ω 0.1 µF _ −5 V ADS807 12-Bit, CM 53 Msps IN Rf 1.82 kΩ 0.1 µF 1.3 kΩ Rg IN 68 pf 16.5 Ω 1.3 kΩ NOTE: For best performance, high-speed ADCs should be driven differentially. See the THS4500 family of devices for more information. Figure 33. Driving an ADC With a Single-Ended Input Active Filtering With the THS4222 THS4222 50 Ω (1:4 Ω) Source 1:2 649 Ω RISO THS4222 RT 49.9 Ω 5V + +5 V 50 Ω Source 12-Bit, 53 Msps 4.7 pF 649 Ω High-frequency active filtering with the THS4222 is achievable due to the amplifier’s high slew rate, wide bandwidth, and voltage feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. A simple two-pole low pass filter is presented here as an example, with two poles at about 25 MHz. 24.9 Ω 4.7 pF 1.3 kΩ 50 Ω Source _ THS4222 + VI 1.3 kΩ 1.3 kΩ 52.3 Ω 5V _ THS4222 Figure 32. A Linear, Low Noise, High Gain ADC Preamplifier The second circuit depicts single-ended ADC drive. While not recommended for optimum performance using converters with differential inputs, satisfactory + 49.9 Ω VO 120 pF −5 V Figure 34. A Two-Pole Active Filter With Two Poles at about 25 MHz 17 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 NOISE ANALYSIS High slew rates, stable unity gain, voltage-feedback operational amplifiers usually achieve their slew rate at the expense of a higher input noise voltage. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 35 shows the amplifier noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. THS4222 FAMILY ENI + RS ERS 4kTRS Rf Rg 4kT Rg BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the THS4222 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: EO _ IBN distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. 2. Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the (1) signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat (2) farther from the device and may be shared among several devices in the same area of the PC board. 3. Careful selection and placement of external components will preserve the high frequency performance of the THS4222. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire wound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place ERF 4kTRf IBI 4kT = 1.6E−20J at 290K Figure 35. Noise Analysis Model The total output shot noise voltage can be computed as the square of all squares output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 35: EO + Ǹǒ Ǔ 2 2 ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG Dividing this expression by the noise gain (NG=(1+ Rf/Rg)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in equation 2: EO + Ǹ 2 E NI 2 ) ǒI BNRSǓ ) 4kTR S ) ǒINGR Ǔ ) 4kTR NG 2 BI f f Driving Capacitive Loads One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the THS4222 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or 18 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. It has been suggested here that a good starting point for design would be set the Rf be set to 1.3 kΩ for low-gain, noninverting applications. Doing this automatically keeps the resistor noise terms low, and minimize the effect of their parasitic capacitance. 4. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs Capacitive Load. Low parasitic capacitive loads (<4 pF) may not need an R(ISO), since the THS4222 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R(ISO) are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS4222 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of R(ISO) vs Capacitive Load. This setting does not preserve signal integrity or a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. 5. Socketing a high speed part like the THS4222 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4222 onto the board. PowerPAD™ DESIGN CONSIDERATIONS The THS4222 family is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 36(a) and Figure 36(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 36(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the heretofore awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 36. Views of Thermally Enhanced Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. 19 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 prevents solder from being pulled away from the thermal pad area during the reflow process. 0.205 0.060 0.017 Pin 1 0.030 0.025 0.094 0.035 0.040 Top View Figure 37. PowerPAD PCB Etch and Via Pattern PowerPAD PCB LAYOUT CONSIDERATIONS 1. Prepare the PCB with a top side etch pattern as shown in Figure 37. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. They help dissipate the heat generated by the THS4222 family IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered, so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This resistance makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS4222 family PowerPAD package should make their connection to the internal ground plane, with a complete connection around the entire circumference of the plated-through hole. 6. 20 Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. 0.013 0.075 0.010 vias 7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This For a given θJA , the maximum power dissipation is shown in Figure 38 and is calculated by the equation 5: PD + Tmax * T A q JA (3) where: PD = Maximum power dissipation of THS4222 (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to the case θCA = Thermal coefficient from the case to ambient air (°C/W). The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class AB), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. For a single package, the sum of the RMS output currents and voltages should be used to choose the proper package. THERMAL ANALYSIS The THS4222 family of devices does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150_ C is exceeded. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 P Dmax + DESIGN TOOLS Tmax–T A q JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (°C). TA is the ambient temperature (°C). θJA = θJC + θCA θJC is the thermal coefficient from the silicon junctions to the case (°C/W). θCA is the thermal coefficient from the case to ambient air (°C/W). For systems where heat dissipation is more critical, the THS4222 family is offered in MSOP with PowerPAD. The thermal coefficient for the MSOP PowerPAD package is substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the two packages. The data for the DGN package assumes a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application notes in the Additional Reference Material section at the end of the data sheet. Evaluation Fixtures, Spice Models, and Applications Support Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, evaluation boards have been developed for the THS4222 family of operational amplifiers. The boards are easy to use, allowing for straight-forward evaluation of the device. These evaluation boards can be ordered through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Schematics for the two evaluation boards are shown below with their default component values. Unpopulated footprints are shown to provide insight into design flexibility. R6 J2 R1 R2 VS+ U1:A R4 R3 PD − Maximum Power Dissipation − W 3.5 3 VS− PwrPad 8-Pin DGN Package R7 2.5 J4 R8 2 1.5 J1 R6 J3 8-Pin D Package R9 J6 R11 J5 U1:B 1 0 −40 R12 R10 0.5 −20 0 20 40 60 TA − Ambient Temperature − °C 80 J7 VS− θJA = 170°C/W for 8-Pin SOIC (D) θJA = 58.4°C/W for 8-Pin MSOP (DGN) ΤJ = 150°C, No Airflow Figure 38. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. GND J9 VS+ TP1 FB1 FB2 VS− C9 C7 + VS+ C6 C5 + C8 C10 Figure 39. THS4222 EVM Circuit Configuration 21 THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 Figure 40. THS4222 EVM Board Layout (Top Layer) Figure 41. THS4222 EVM Board Layout (2nd Layer, Ground) 22 Figure 42. THS4222 EVM Board Layout (3rd Layer, Power) Figure 43. THS4222 EVM Board Layout (Bottom Layer) THS4221, THS4225 THS4222, THS4226 www.ti.com SLOS399G − AUGUST 2002 − REVISED JANUARY 2004 Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4222 family is available through the Texas Instruments web site (www.ti.com). The PIC is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. ADDITIONAL REFERENCE MATERIAL D PowerPAD Made Easy, application brief (SLMA004) D PowerPAD Thermally Enhanced Package, technical brief (SLMA002) 23 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) THS4221D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4221 THS4221DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFS THS4221DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFS THS4221DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFS THS4221DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFS THS4221DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4221 THS4221DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHX THS4221DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHX THS4221DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHX THS4221DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHX THS4221DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFT THS4221DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFT THS4222D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4222 THS4222DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4222 THS4222DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHW THS4222DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BHW THS4222DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFO Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) THS4222DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFO THS4222DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFO THS4222DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFO THS4222DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4222 THS4222DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4222 THS4225D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4225 THS4225DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4225 THS4225DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFY THS4225DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFY THS4225DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFU THS4225DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFU THS4226DGQ ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFP THS4226DGQG4 ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BFP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ THS4221DBVR SOT-23 3000 180.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 9.0 3.15 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 THS4221DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 THS4221DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4222DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4222DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4221DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 THS4221DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 THS4221DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 THS4222DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4222DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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