TI THS3201DBVT

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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
FEATURES
DESCRIPTION
D Unity Gain Bandwidth: 1.8 GHz
D High Slew Rate: 10500 V/µs
D Distortion at 100 MHz: (G = 10 V/V,
The
THS3201
is
a
wide-band,
high-speed
current-feedback amplifier, designed to operate over a
wide supply range of ±3.3 V to ±7.5 V for todays high
performance applications.
RL = 100 Ω, 2-VPP envelope)
− IMD3: −80 dBc
− OIP3: 41 dBm
The wide supply range combined with distortion as low as
−74 dBc at 10 MHz, plus an extremely high slew rate of
10500 V/µs makes the THS3201 ideally suited for arbitrary
waveform driver applications. The distortion performance
also enables driving high-resolution and high-sampling
rate ADCs. Moreover, the gain of +2 bandwidth of 850
MHz, combined with a 0.1 dB flatness of 380 MHz makes
the THS3201 ideal for broadcast video and HDTV
applications. The THS3201 also offers excellent
performance
for
IF
amplification
in
wireless
communications systems by having IMD3 performance of
−80 dBc, OIP3 of 41 dBm, and a noise figure of 11 dB, all at
100 MHz with a gain +10 V/V, while driving a 2-VPP
envelope into a 100-Ω load.
D Noise Figure : 11 dB (G = 10 V/V,
RG = 28 Ω, RF = 255 Ω)
D Input Referred Noise (f > 10 MHz)
− Voltage Noise: 1.65 nV/√Hz
− Noninverting Current Noise: 13.4 pA/√Hz
− Inverting Current Noise: 20 pA/√Hz
D Output Current: +115/−100 mA
D Power Supply Voltage Range: ±3.3 V to ±7.5 V
APPLICATIONS
D Arbitrary Waveform Driver
D High-Resolution, High-Sampling Rate ADC
The THS3201 is offered in a 5-pin SOT−23, 8-pin SOIC,
and an 8-pin MSOP with PowerPAD packages.
Drivers
RELATED DEVICES AND DESCRIPTIONS
D High-Resolution, High-Sampling Rate DAC
Output Buffers
D If Amplification for Wireless Communications
Applciations
D Broadcast Video and HDTV Line Drivers
THS3202
±7.5-V 2-GHz Dual Low Distortion CFB Amplifier
THS3001
±15-V 420-MHz Low Distortion CFB Amplifier
THS3061/2
±15-V 300-MHz Low Distortion CFB Amplifier
THS3122
±15-V Dual CFB Amplifier With 350 mA Drive
THS4271
±7.5-V 1.4-GHz Low Distortion VFB Amplifier
Low-Noise, Low-Distortion, Wideband Application Circuit
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
+7.5 V
50 Ω Source
8
7
+
VI
49.9 Ω
49.9 Ω
THS3201
_
−7.5 V
768 Ω
768 Ω
NOTE: Power supply decoupling capacitors not shown
50 Ω
Noninverting Gain − dB
50 Ω
RF = 768 Ω
6
5
4
3
2
1
0
100 k
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
1M
10 M
100 M
1G
10 G
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
"#$%&'()"%# "* +,&&-#) (* %$ .,/0"+()"%# 1()- &%1,+)*
+%#$%&' )% *.-+"$"+()"%#* .-& )2- )-&'* %$ -3(* #*)&,'-#)* *)(#1(&1 4(&&(#)5
&%1,+)"%# .&%+-**"#6 1%-* #%) #-+-**(&"05 "#+0,1- )-*)"#6 %$ (00 .(&('-)-&*
Copyright  2003 − 2004, Texas Instruments Incorporated
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
16.5 V
Supply voltage, VS
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
±VS
Input voltage, VI
Output current, IO (2)
175 mA
±3 V
Differential input voltage, VID
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, TJ (3)
Maximum junction temperature, continuous
operation, long term reliability TJ (4)
−40°C to 85°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
300°C
HBM
3000 V
CDM
1500 V
MM
100 V
POWER RATING(2)
(TJ = 125°C)
TA ≤ 25°C TA = 85°C
θJC
(°C/W)
θJA(1)
(°C/W)
DBV (5)
55
255.4
391 mW
156 mW
D (8)
38.3
97.5
1.02 W
410 mW
DGN (8)
4.7
58.4
1.71 W
685 mW
PACKAGE
125°C
Operating free-air temperature range, TA
ESD ratings:
PACKAGE DISSIPATION RATINGS
150°C
DGK (8 pin)
54.2
260
385 mW
154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS3201 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
Supply voltage
MIN
MAX
Dual supply
±3.3
±7.5
Single supply
6.6
15
−40
85
Operating free-air temperature, TA
UNIT
V
°C
PACKAGE/ORDERING INFORMATION
PACKAGED DEVICES
TEMPERATURE
PLASTIC SMALL
OUTLINE
(D)(1)
(DBV)
THS3201D
THS3201DBVT
THS3201DR
THS3201DBVR
−40°C to 85°C
PLASTIC MSOP(1)
POWERPAD
SOT-23(2)
SYM
(DGN)
SYM
THS3201DGN
BEO
PLASTIC MSOP(1)
(DGK)
THS3201DGK
BEN
THS3201DGNR
THS3201DGKR
(1) Available in tape and reel. The R suffix standard quantity is 2500 (e.g. THS3201DGNR).
(2) Available in tape and reel. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (e.g. THS3201DBVT).
PIN ASSIGNMENTS
TOP VIEW
SOT−23
VOUT
VS−
IN+
1
5
VS+
2
3
4
D, DGN, DGK
TOP VIEW
IN −
NC
VIN −
VIN +
VS−
1
8
2
7
3
6
4
5
NC
VS+
VOUT −
NC
NC = No Internal Connection
NOTE: If a PowerPAD is used, it is electrically isolated from the active circuitry.
2
SYM
BGP
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±7.5 V: Rf = 768 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3201
PARAMETER
TYP
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE
Small-signal bandwidth, −3 dB
(VO = 200 mVPP)
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
Slew rate (25% to 75% level)
G = +1, RF= 1.2 kΩ
1.8
G = +2, RF = 768 Ω
850
G = +5, RF = 619 Ω
565
G = +10, RF = 487 Ω
520
G = +2, VO = 200 mVpp,
RF = 768 Ω
G = +2, VO = 2 Vpp, RF = 715 Ω
Typ
MHz
Typ
880
MHz
Typ
V/µs
Typ
ns
Typ
ns
Typ
dBc
Typ
dBc
Typ
G = +1, VO = 5-V step
6200
G = +2, VO = 10-V step
10500
G = +2, VO = 4-V step, RF = 768 Ω
0.6
Settling time to 0.1%
G = −2, VO = 2-V step
20
G = −2, VO = 2-V step
60
Harmonic distortion
MHz
380
Rise and fall time
0.01%
GHz
G = +5, f = 10 MHz, VO = 2 Vpp
2nd harmonic
RL = 100 Ω
RL = 500 Ω
−75
3rd harmonic
RL = 100 Ω
RL = 500 Ω
−91
G = +10, fc = 100 MHz,
∆f = 200 kHz,
VO(envelope) = 2 Vpp
−80
dBc
Typ
41
dBm
Typ
Third-order intermodulation
distortion (IMD3)
Third-order output intercept
point (OIP3)
−77
−93
11
dB
Typ
Input voltage noise
G = +10, fc = 100 MHz,
RF = 255 Ω, RG = 28
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Noise figure
Differential gain
Differential phase
G = +2, RL = 150 Ω,
RF = 768 Ω
NTSC
0.008%
Typ
PAL
0.004%
Typ
NTSC
0.007°
Typ
PAL
0.011°
Typ
DC PERFORMANCE
VO = ±1 V, RL = 1 kΩ
VCM = 0 V
300
200
140
120
kΩ
Min
±0.7
±3
±3.8
±4
mV
Max
VCM = 0 V
VCM = 0 V
±10
±13
µV/°C
Typ
±13
±60
±80
±85
µA
Max
VCM = 0 V
VCM = 0 V
±300
±400
nA/°C
Typ
Input bias current (noninverting)
±14
±35
±45
±50
µA
Max
Average bias current drift (+)
VCM = 0 V
±300
±400
nA/°C
Typ
Open-loop transimpedance gain
Input offset voltage
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
3
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±7.5 V: Rf = 768 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3201
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
INPUT
±5.1
±5
±5
±5
V
Min
VCM = ±3.75 V
Open loop
71
60
58
58
dB
Min
16
Ω
Typ
Noninverting
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
RL = 1 kΩ
RL = 100 Ω
±6
±5.9
±5.8
±5.8
±5.8
±5.7
±5.5
±5.5
V
Min
RL = 20 Ω
RL = 20 Ω
115
105
100
100
mA
Min
Current output, sinking
100
85
80
80
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Common-mode input range
Common-mode rejection ratio
Inverting input impedance, Zin
Input resistance
Input capacitance
OUTPUT
Voltage output swing
Current output, sourcing
POWER SUPPLY
Minimum operating voltage
Absolute minimum
±3.3
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±8.25
±8.25
±8.25
V
Max
14
18
21
21
mA
Max
69
63
60
60
dB
Min
65
58
55
55
dB
Min
Maximum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
4
VS+ = 7 V to 8 V
VS− = −7 V to –8 V
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V: Rf = 715 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3201
PARAMETER
TYP
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE
G = +1, RF= 1.2 kΩ
1.3
G = +2, RF = 715 Ω
725
G = +5, RF = 576 Ω
540
G = +10, RF = 464 Ω
480
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVpp,
RF= 715 Ω
170
MHz
Typ
Large-signal bandwidth
G = +2, VO = 2 Vpp, RF= 715 Ω
900
MHz
Typ
G = +1, VO = 5-V step
5200
G = +2, VO = 5-V step
5200
V/µs
Typ
0.7
ns
Typ
20
ns
Typ
G = −2, VO = 2-V step
60
ns
Typ
G = +5, f = 10 MHz, VO = 2 Vpp
RL = 100 Ω
−68
dBc
Typ
dBc
Typ
Small-signal bandwidth, −3dB
(VO = 200 mVPP)
Slew rate (25% to 75% level)
Rise and fall time
Settling time to 0.1%
0.01%
Harmonic distortion
2nd harmonic
3rd harmonic
Third-order intermodulation
distortion (IMD3)
Third-order output intercept
point (OIP3)
G = +2, VO = 4-V step,
RF= 715 Ω
G = −2, VO = 2-V step
GHz
MHz
Typ
RL = 500 Ω
RL = 100 Ω
−70
RL = 500 kΩ
−74
G = +10, fc = 100 MHz,
∆f = 200 kHz,
VO(envelope) = 2 Vpp
−65
dBc
Typ
33.5
dBm
Typ
−72
11
dB
Typ
Input voltage noise
G = +10, fc = 100 MHz,
RF = 255 Ω, RG = 28
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Noise figure
Differential gain
Differential phase
G = +2, RL = 150 Ω,
RF= 768 Ω
NTSC
0.006%
Typ
PAL
0.004%
Typ
NTSC
0.03°
Typ
PAL
0.04°
Typ
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
VO = +1 V, RL = 1 kΩ
VCM =0 V
VCM = 0 V
VCM = 0 V
Input bias current (noninverting)
VCM = 0 V
VCM = 0 V
Average bias current drift (+)
VCM = 0 V
300
200
140
±0.7
±3
±3.8
±10
±80
±300
±13
±14
±60
±35
120
kΩ
Min
±4
mV
Max
±13
µV/°C
Typ
±85
µA
Max
±400
nA/°C
Typ
±45
±50
µA
Max
±300
±400
nA/°C
Typ
5
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS continued
VS = ±5 V: Rf = 715 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3201
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
±2.6
±2.5
±2.5
71
60
58
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
±2.5
V
Min
58
dB
Min
INPUT
Common-mode input range
Common-mode rejection ratio
Inverting input impedance, Zin
Input resistance
Input capacitance
VCM = ±2.5 V
Open loop
17.5
Ω
Typ
Noninverting
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
RL = 1 kΩ
RL = 100 Ω
±3.65
±3.5
±3.45
±3.4
±3.45
±3.33
±3.25
±3.2
V
Min
OUTPUT
Voltage output swing
RL = 20 Ω
RL = 20 Ω
115
105
100
100
mA
Min
Current output, sinking
100
85
80
80
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Current output, sourcing
POWER SUPPLY
Minimum operating voltage
Absolute minimum
±3.3
±3.3
±3.3
V
Min
Maximum operating voltage
Absolute maximum
±8.25
±8.25
±8.25
V
Max
14
16.8
19
20
mA
Max
69
63
60
60
dB
Min
65
58
55
55
dB
Min
Maximum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
6
VS+ = 4.5 V to 5.5 V
VS− = −4.5 V to –5.5 V
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (VS = ±7.5 V)
FIGURE
Noninverting small signal frequency response
1, 2
Inverting small signal frequency response
3
Noninverting large signal frequency response
4
Inverting large signal frequency response
5
0.1 dB gain flatness frequency response
6
Capacitive load frequency response
7
Recommended switching resistance
vs Capacitive Load
2nd harmonic distortion
vs Frequency
9
3rd harmonic distortion
vs Frequency
10
Harmonic distortion
vs Output voltage swing
Third-order intermodulation distortion (IMD3)
vs Frequency
Third-order output intercept point (OIP3)
vs Frequency
14
S − Parameter
vs Frequency
15, 16
Input voltage and current noise
vs Frequency
17
Noise figure
vs Frequency
18
Transimpedance
vs Frequency
19
Input offset voltage
vs Case Temperature
20
Input bias and offset current
vs Case Temperature
21
Slew rate
vs Output voltage step
22, 23
Settling time
8
11, 12
13
24, 25
Quiescent current
vs Supply voltage
26
Output voltage
vs Load resistance
27
Rejection ratio
vs Frequency
28
Noninverting small signal transient response
29
Inverting large signal transient response
30
Overdrive recovery time
31
Differential gain
vs Number of loads
32
Differential phase
vs Number of loads
33
Closed-loop output impedance
vs Frequency
34
Table of Graphs (VS = ±5 V)
FIGURE
Noninverting small signal frequency response
35
Inverting small signal frequency response
36
37
2nd harmonic distortion
vs Frequency
38
3rd harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
Third-order intermodulation distortion (IMD3)
vs Frequency
Third-order output intercept point (OIP3)
vs Frequency
43
S − Parameter
vs Frequency
44, 45
Slew rate
vs Output voltage step
39
40, 41
42
46
Noninverting small signal transient response
47
Inverting large signal transient response
48
Overdrive recovery time
49
7
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
VS = ±7.5 V Graphs
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
24
22
8
6
5
RF = 1 kΩ
4
3
Gain = 2.
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
2
1
0
100 k
1M
10 M
100 M
1G
20
18
16
14
12
10
G = 5, RF = 619 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
8
6
4
2
0
−2
−4
G = 2, RF = 768 Ω
G =1, RF = 1.2 kΩ
100 k
10 G
1M
10 M
Figure 1
8
G = 2, RF = 715 Ω
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
2
RL = 100 Ω,
VO = 2 VPP.
VS = ±7.5 V
8
6
4
2
G = −1, RF = 576 Ω
1M
Figure 4
6
R(ISO) = 15 Ω,
CL = 100 pF
4
2
100
200
300
f − Frequency − MHz
Figure 7
100 k
400
500
1M
10 M
100 M
f − Frequency − Hz
1G
10 G
Figure 6
2nd HARMONIC DISTORTION
vs
FREQUENCY
40
30
20
_
+
RISO
CL
VO = 2 VPP,
RL = 100 Ω,
VS = ±7.5 V
−50
G = 1, RF = 1.2 kΩ
−60
−70
G = 5, RF = 619 Ω
−80
G = 2, RF = 768 Ω
−90
−100
0
0
5.8
−40
10
R(ISO) = 20 Ω,
CL = 47 pF
0
5.9
1G
Gain = 5,
RF = 619 Ω
RL = 100 Ω,
VS = ±7.5 V
50
Gain = 5
RF = 619 Ω
RL = 100 Ω
VS = ±7.5 V
8
10 M
100 M
f − Frequency − Hz
60
Recommended R
−Ω
ISO
10
6
RECOMMENDED RISO
vs
CAPACTIVE LOAD
R(ISO) = 20 Ω,
CL = 50 pF
12
6.1
Figure 5
CAPACITIVE LOAD
FREQUENCY RESPONSE
14
6.2
5.6
100 k
R(ISO) = 30 Ω, CL = 22 pF
10 G
5.7
−4
16
1G
Gain = 2,
RF = 768 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±7.5 V
6.3
10
1G
100 M
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
−2
1M
10 M
100 M
f − Frequency − Hz
10 M
Figure 3
G =−5, RF = 549 Ω
0
0
100 k
1M
f − Frequency − Hz
Noninverting Gain − dB
Inverting Gain − dB
10
4
G = −1, RF = 619 Ω
6.4
12
Inverting Gain − dB
10 G
14
12
6
G = −2, RF = 576 Ω
2
0
−2
−4
100 k
16
G =−5, RF = 576 Ω
14
G = −5, RF = 549 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±7.5 V
INVERTING LARGE SIGNAL
FREQUENCY RESPONSE
16
Gain − dB
1G
16
14
12
10
8
6
4
Figure 2
INVERTING LARGE SIGNAL
FREQUENCY RESPONSE
8
100 M
G = −10, RF = 499 Ω
20
18
f − Frequency − Hz
f − Frequency − Hz
−2
24
22
G = 10, RF = 487 Ω
2nd Harmonic Distortion − dBc
Noninverting Gain − dB
7
Noninverting Gain − dB
RF = 619 Ω
RF = 768 Ω
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
Noninverting Gain − dB
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
10
100
CL − Capacitive Load − pF
Figure 8
1
10
f − Frequency − MHz
Figure 9
100
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
G = 1, RF = 1.2 kΩ
−70
G = 2, RF = 768 Ω
−80
−70
−75
HD2, RL = 499 Ω
HD2, RL = 100 Ω
−80
−85
−90
−90
−100
10
100
0 0.5
f − Frequency − MHz
−70
Third-Order Output Intersept Point − dBm
−65
G = 2, RF = 768 Ω
−75
G = 5, RF = 619 Ω
−80
−85
−90
−95
G = 10, RF = 487 Ω
−100
10
100
200
S−Parameter − dB
1 1.5 2 2.5 3 3.5 4 4.5
VO − Output Voltage Swing − ± V
S − PARAMETER
vs
FREQUENCY
0
55
50
−20
G = 10, RF = 487 Ω
45
0
20
−40
40
60
f − Frequency − MHz
80
100
S22
S12
−60
RG
C
−100
1M
S12
S11
RG
RF
C
−
+
−80
−100
1M
50 Ω
Source
50 Ω
10 M
100 M
1G
f − Frequency − Hz
Figure 16
50 Ω
50 Ω
10 G
50 Ω
10 M
100 M
1G
f − Frequency − Hz
50 Ω
50 Ω
10 G
Figure 15
INPUT VOLTAGE
AND CURRENT NOISE
vs
FREQUENCY
S22
−40
RF
−
+
Figure 14
VS = ±7.5 V
Gain = +10
C = 3.3 pF
5
S11
50 Ω
Source
G = 2, RF = 768 Ω
35
VS = ±7.5 V
Gain = +10
C = 0 pF
−80
G = 5, RF = 619 Ω
S − PARAMETER
vs
FREQUENCY
−60
Gain = 5, RF = 619 Ω
f = 32 MHz, VS = ±7.5 V
0 0.5
5
VO = 2 VPP Envelope
RL = 100 Ω
VS = ±7.5 V
200 kHz Tone Spacing
40
HD3, RL = 100 Ω
−90
THIRD-ORDER OUTPUT
INTERCEPT POINT
vs
FREQUENCY
Figure 13
−20
−85
Figure 12
f − Frequency − MHz
0
−80
60
RL = 100 Ω
VO = 2VPP Envelope
VS = ±7.5 V
200 kHz Tone Spacing
HD3,
RL = 499 Ω
−75
Figure 11
I n − Input Current Noise Density − pA Hz
−60
−70
−100
1 1.5 2 2.5 3 3.5 4 4.5
VO − Output Voltage Swing − ± V
Figure 10
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
−65
−95
HD3, RL = 499 Ω
−100
1
HD2
RL = 100 Ω
−60
HD3, RL = 100 Ω
−95
G = 5, RF = 619 Ω
HD2, RL = 499 Ω
−55
50
Hz
−60
−65
S−Parameter − dB
−50
Gain = 5
RF = 619 Ω
f = 8 MHz
VS = ±7.5 V
Harmonic Distortion − dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±7.5 V
Harmonic Distortion − dBc
3rd Harmonic Distortion − dBc
−50
−60
−40
Third-Order Intermodulation Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
4
VS = ±7.5 V and ±5 V
TA = 25°C
45
40
3.5
3
Vn
35
30
2.5
1.5
Inverting
Noise Current
25
20
0.5
0
V n − Voltage Noise Density − nV/
3rd HARMONIC DISTORTION
vs
FREQUENCY
Noninverting
Current Noise
15
10
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 17
9
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
TRANSIMPEDANCE
vs
FREQUENCY
NOISE FIGURE
vs
FREQUENCY
14
3
120
Transimpedance Gain −dBΩ
11
10
Gain = +10
RG = 28 Ω
RF = 255 Ω
VS = ±7.5 V & ±5 V
8
7
80
60
40
20
6
0
50
10 Ω
1M
100 M
5
4
IIB+
13
3
12
2
IOS
1
11
6000
SLEW RATE
vs
OUTPUT VOLTAGE
Rise
3000
2000
0.5 1 1.5 2 2.5 3 3.5 4
VO − Output Voltage − VPP
6000
Fall
5000
4000
3000
0
4.5 5
1
Figure 22
VO − Output Voltage − V
−0.5
Falling Edge
8
10
7
8
9
10
16
1
0.5
Gain = −2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
0
−0.5
−1
−1.5
TA = 25°C
14
12
TA = −40°C
10
8
6
4
Falling Edge
2
−3
6
6
TA = 85°C
18
Rising Edge
2
1.5
−2.5
−1.5
5
20
−2
−1
4
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
2.5
1
3
Figure 23
SETTLING TIME
Rising Edge
2
VO − Output Voltage − VPP
3
Figure 24
7000
0
0
Gain = −2
RL = 100 Ω
RF = 576 Ω
f= 1 MHz
VS = ±7.5 V
Rise
1000
0
SETTLING TIME
t − Time − ns
8000
2000
1000
1.5
4
Gain = 2
RL = 100 Ω
RF = 768 Ω
VS = ±7.5 V
9000
Fall
Figure 21
10
TC − Case Temperature − °C
10000
4000
TC − Case Temperature − °C
2
0.5
Figure 20
5000
10
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
VS = ±5 V
1
11000
Gain = 1
RL = 100 Ω
RF = 1.2 kΩ
VS = ±7.5 V
7000
SR − Slew Rate − V/ µ s
IIB−
I OS − Input Offset Currents − µ A
6
16
0
1.5
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1G
8000
VS = ±7.5 V
0.5
VS = ±7.5 V
SLEW RATE
vs
OUTPUT VOLTAGE
7
17
I IB − Input Bias Currents − µ A
10 M
2
Figure 19
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
14
O
I IB
2.5
f − Frequency − Hz
Figure 18
15
V
Gain W +
+
_
0
100 k
100 150 200 250 300 350 400
f − Frequency − MHz
_
+
SR − Slew Rate − V/ µ s
9
100
Quiescent Current − mA
Noise Figure − dB
12
VOS − Input Offset Voltage − mV
VS = ±5 and ±7.5V
13
VO − Output Voltage − V
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
0
2.5
5
7.5
t − Time − ns
Figure 25
10
12.5
0
2 2.5
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
VS − Supply Voltage − ±V
Figure 26
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
REJECTION RATIO
vs
FREQUENCY
7
6
5
4
3
Output
0.2
60
−3
−4
−5
CMRR
50
40
PSRR+
30
20
100
0
100 k
1000
1M
RL − Load Resistance − Ω
Figure 27
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t − Time − µs
Figure 29
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
−2
−3
Output
−5
0.025
3
2
2
1
0
0
−2
−1
−4
−2
−6
−3
−8
−4
0.020
PAL
0.015
0.010
0.2
0.4
0.6
0.8
NTSC
0.005
0
−5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Gain = 2
RF = 768 Ω
VS = ±7.5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
4
4
−10
0.030
5
Differential Gain − %
VO − Output Voltage − V
Input
1
0
1
t − Time − µs
t − Time − µs
Figure 30
0.020
Closed-Loop Output Impedance − Ω
0.025
4
5
6
7
8
Figure 32
1000
Gain = 2
RF = 768 kΩ
VS = ±7.5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.030
3
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
0.040
0.035
2
Number of Loads − 150 Ω
Figure 31
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
°
−0.1
−0.3
100 M
G = 2,
RF = 768 Ω,
VS = ±7.5 V
6
−1
Differential Phase −
VO − Output Voltage − V
Gain = −5
RL = 100 Ω
RF = 549 Ω
VS = ±7.5 V
1
−6
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±7.5 V
OVERDRIVE RECOVERY TIME
8
−4
10 M
10
6
0
0
Figure 28
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
2
Input
f − Frequency − Hz
VI − Input Voltage − V
10
0.1
−0.2
10
−6
−7
3
VO − Output Voltage − V
VS = ±7.5 V
TA = −40 to 85°C
0
−1
−2
4
0.3
VS = ±7.5 V
70
2
1
5
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
80
Rejection Ratios − dB
VO − Output Voltage − V
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
PAL
0.015
NTSC
0.010
0.005
0
100
10
Gain = 2
RF = 715 Ω
RL = 100 Ω
VS = ±7.5 V
1
0.1
0.01
0.001
0
1
2
3
4
5
6
Number of Loads − 150 Ω
Figure 33
7
8
100 k
1M
10 M
1M
1G
f − Frequency − Hz
Figure 34
11
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
VS = ±5 V Graphs
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
G = 2, RF = 715 Ω
G =1, RF = 1.2 kΩ
18
16
14
12
G = −5, RF = 549 Ω
RL = 100 Ω,
VO = 0.2 VPP.
VS = ±5 V
10
8
6
4
2
G = −2, RF = 576 Ω
0
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 35
2nd HARMONIC DISTORTION
vs
FREQUENCY
3rd Harmonic Distortion − dBc
2nd Harmonic Distortion − dBc
G = 1, RF = 1.2 kΩ
−70
G = 5, RF = 576 Ω
−80
G = 2, RF = 715 Ω
−90
100 M
1G
10
10 M
100 M
f − Frequency − Hz
Figure 36
Figure 37
100 k
−60
G = 1, RF = 1.2 kΩ
−70
−80
G = 2, RF = 715 Ω
−90
−65
HD3, RL = 100 Ω
−70
−75
HD3, RL = 499 Ω
−80
−85
Gain = 5
RF = 576 Ω
f = 32 MHz
VS = ±5 V
−90
−95
−100
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VO − Output Voltage Swing − ± V
Figure 41
HD2, RL = 100 Ω
−65
−70
−75
HD3, RL = 499 Ω
−80
HD3, RL = 100 Ω
−85
Gain = 5
RF = 576 Ω
f = 8 MHz
VS = ±5 V
−90
−95
10
0.5 1
0
100
Figure 39
−60
−60
−100
1
−40
−50
G = 2, RF = 715 Ω
−65
−70
−75
G = 5, RF = 576 Ω
−80
−85
−90
G = 10, RF = 464 Ω
10
100
4 4.5
5
THIRD-ORDER OUTPUT
INTERCEPT POINT
vs
FREQUENCY
200
VO = 2 VPP Envelope
RL = 100 Ω
VS = ±5 V
200 kHz Tone Spacing
50
G = 10, RF = 464 Ω
45
G = 2, RF = 715 Ω
40
35
G = 5, RF = 576 Ω
30
0
f − Frequency − MHz
Figure 42
3 3.5
55
−55
−60
2 2.5
Figure 40
RL = 100 Ω
VO = 2VPP Envelope
VS = ±5 V
200 kHz Tone Spacing
−45
1.5
VO − Output Voltage Swing − ± V
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
Third-Order Intermodulation Distortion − dBc
−55
10 G
HD2, RL = 499 Ω
−55
Figure 38
HD2, RL = 100 Ω
1G
−50
f − Frequency − MHz
HD2, RL = 499 Ω
1M
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
−50
100
−40
−50
5.8
f − Frequency − Hz
f − Frequency − MHz
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−45
5.9
10 G
−100
1
Harmonic Distortion − dBc
10 M
G = 5, RF = 576 Ω
−100
12
1M
−40
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
−60
6
3rd HARMONIC DISTORTION
vs
FREQUENCY
−40
−50
6.1
5.6
100 k
10 G
6.2
5.7
G =−1, RF = 576 Ω
−2
−4
Gain = 2,
RF = 715 Ω,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
6.3
Noninverting Gain − dB
G = 5, RF = 576 Ω
6.4
G = −10, RF = 499 Ω
Harmonic Distortion − dBc
8
6
4
2
0
−2
−4
24
22
20
G = 10, RF = 464 Ω
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
Third-Order Output Intersept Point − dBm
24
22
20
18
16
14
12
10
Inverting Gain − dB
Noninverting Gain − dB
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
20
40
60
f − Frequency − MHz
Figure 43
80
100
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
S − PARAMETER
vs
FREQUENCY
S12
−60
S11
RG
RF
−40
S22
S12
−60
S11
RG
RF
C
C
−
+
−80
−100
1M
50 Ω
Source
50 Ω
10 M
100 M
1G
f − Frequency − Hz
−
+
−80
50 Ω
50 Ω
10 G
−100
1M
50 Ω
Source
50 Ω
4000
Rise
3000
Fall
2000
1000
50 Ω
50 Ω
0
10 M
100 M
1G
f − Frequency − Hz
10 G
Figure 44
Figure 45
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
0
1
2
3
4
VO − Output Voltage − VPP
OVERDRIVE RECOVERY TIME
6
3
2.5
2
Input
0
−0.1
−0.2
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±5 V
VO − Output Voltage − V
VO − Output Voltage − V
0.1
1.5
1
Gain = −5
RL = 100 Ω
RF = 549 Ω
VS = ±5 V
0.5
0
Input
−0.5
−1
−1.5
−2
Output
G = 2,
RF = 715 Ω,
VS = ±5 V
4
VO − Output Voltage − V
Output
0.2
5
Figure 46
3
0.3
Gain = 2
RL = 100 Ω
RF = 715 Ω
VS = ±5 V
5000
2
2
1
0
0
−2
−1
−4
−2
VI − Input Voltage − V
−20
S22
−40
VS = ±5 V
Gain = +10
C = 3.3 pF
SR − Slew Rate − V/ µ s
S−Parameter − dB
−20
SLEW RATE
vs
OUTPUT VOLTAGE
6000
0
VS = ±5 V
Gain = +10
C = 0 pF
S−Parameter − dB
0
S − PARAMETER
vs
FREQUENCY
−2.5
−0.3
−6
−3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t − Time − µs
Figure 47
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
t − Time −µs
Figure 48
0
0.2
0.4
0.6
0.8
−3
1
t − Time − µs
Figure 49
13
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
The THS3201 is a unity gain stable 1.8-GHz
current-feedback operational amplifiers, designed to
operate from a ±3.3-V to ±7.5-V power supply.
Figure 50 shows the THS3201 in a noninverting gain of
2V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment presenting
a 50-Ω load impedance. The 49.9-Ω shunt resistor at the
VI terminal in Figure 50 matches the source impedance of
the test generator.
100 pF
50 Ω Source
+
0.1 µF
6.8 µF
49.9 Ω
_
RG
Supply Voltage
(V)
RG (Ω)
RF (Ω)
±7.5
—
1.2 k
1
2
5
10
50 Ω
768 Ω
0.1 µF
100 pF
−7.5 V
±5
—
1.2 k
±7.5
768
768
±5
715
715
±7.5
154.9
619
±5
143
576
±7.5
54.9
487
±5
51.1
464
±7.5
619
619
±5
576
576
−2
±7.5 and ±5
287
576
−5
±7.5 and ±5
110
549
−10
±7.5 and ±5
49.9
499
WIDEBAND, INVERTING GAIN OPERATION
THS3201
RF
768 Ω
Gain
(V/V)
+VS
+
49.9 Ω
THS3201 RF for AC When Rload = 100 Ω
−1
7.5 V
VI
Table 1. Recommended Resistor Values for
Optimum Frequency Response
6.8 µF
Figure 51 shows the THS3201 is a typical inverting gain
configuration where the input and output impedances and
signal gain from Figure 50 are retained in an inverting
circuit configuration.
+
7.5 V +V
S
−VS
+
100 pF
Figure 50. Wideband, Noninverting Gain
Configuration
Unlike voltage-feedback amplifiers, current-feedback
amplifiers are highly dependent on the feedback resistor
RF for maximum performance and stability. Table 1 shows
the optimal gain setting resistors RF and RG at different
gains to give maximum bandwidth with minimal peaking in
the frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for RF.
Conversely, increasing RF decreases the bandwidth, but
stability is improved.
14
+
0.1 µF
6.8 µF
49.9 Ω
THS3201
_
50 Ω Source
VI
50 Ω
RG
RF
287 Ω
RM
60.4 Ω
576 Ω
0.1 µF
100 pF
−7.5 V
6.8 µF
+
−VS
Figure 51. Wideband, Inverting Gain
Configuration
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
768 Ω
SINGLE SUPPLY OPERATION
768 Ω
±7.5 V
The THS3201 has the capability to operate from a single
supply voltage ranging from 6.6V to 15V. When operating
from a single power supply, care must be taken to ensure
the input signal and amplifier is biased appropriately to
allow for the maximum output voltage swing. The circuits
shown in Figure 52 demonstrate methods to configure an
amplifier in a manner conducive for single supply
operation
THS3201
VI
75-Ω Transmission Line
VO(1)
75 Ω
−
+
±7.5 V
75 Ω
n Lines
75 Ω
VO(n)
75 Ω
75 Ω
+VS
Figure 53. Video Distribution Amplifier
Application
50 Ω Source
+
VI
49.9 Ω
RT
49.9 Ω
THS3201
_
50 Ω
+VS
2
RG
768 Ω
+VS
2
The THS3201 can be used as a high-performance ADC
driver in applications like radio receiver IF stages, and test
and measurement devices. All high-performance ADCs
have differential inputs. The THS3201 can be used in
conjunction with a transformer as a drive amplifier in these
applications. Figure 54 and Figure 55 show two different
approaches.
768 Ω
RF
576 Ω
50 Ω Source
VI
60.4 Ω
+VS
2
ADC DRIVER APPLICATION
RF
VS
RG
287 Ω
RT
_
49.9 Ω
THS3201
+
50 Ω
+VS
2
In Figure 54, a transformer is used after the amplifier to
convert the signal to differential. The advantage of this
approach is fewer components are required. ROUT and RT
are required for impedance matching the transformer.
VS+
Figure 52. DC-Coupled Single Supply Operation
0.1 µF
RG
VIDEO AND HDTV DRIVERS
RF
ROUT 1:n
THS3201
VIN
The exceptional bandwidth and slew rate of the THS3201
matches the demands for professional video and HDTV.
Most commercial HDTV standards requires a video
passband of 30-MHz. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain
flatness should be at least 7x the passband frequency to
minimize group delay variations—requiring 210-MHz
0.1-dB frequency flatness from the amplifier. High slew
rates ensures there is minimal distortion of the video
signal. Component video and RGB video signals require
fast transition times and fast settling times to keep a high
signal quality. The THS8135, for example, is a 240 MSPS
video DAC and has a transition time approaching 4-ns.
The THS3201 is a perfect candidate for interfacing the
output of such high-performance video components.
24.9 Ω
RT
47pF
24.9 Ω
ADC
VS−
CM
47pF
0.1 µF
0.1 µF
Figure 54. Differential ADC Driver Circuit 1
In Figure 55, a transformer is used before two amplifiers to
convert the signal to differential. The two amplifiers then
amplify the differential signal. The advantage to this
approach is each amplifier is required to drive half the
voltage as before. RT is used to impedance match the
transformer.
15
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SLOS416A − JUNE 2003 − REVISED JANUARY 2004
VS+
Placing this pole at about 10x the highest frequency of
interest insures it has no impact on the signal. Since the
resistor is typically a small value, it is very bad practice to
place the pole at (or very near) frequencies of interest. At
the pole frequency, the amplifiers sees a load with a
magnitude of:
0.1 µF
RG
VIN
RF
THS3201
1:n
24.9 Ω
Ǹ2 xR
47pF
ADC
RT
RG
THS3201
24.9 Ω
CM
47pF
RF
VS−
0.1 µF
0.1 µF
Figure 55. Differential ADC Driver Circuit 2
It is almost universally recommended to use a resistor and
capacitor between the op amp’s output and the ADC’s
input as shown in both Figures.
This resistor-capacitor (RC) combination has multiple
functions:
D
The capacitor is a local charge reservoir for ADC
D
The resistor isolates the amplifier from the ADC
D
In conjunction, they form a low-pass noise filter
During the sampling phase, current is required to charge
the ADC’s input sampling capacitors. By placing external
capacitors directly at the input pins, most of the current is
drawn from them. They are seen as a very low impedance
source. They can be thought of as serving much the same
purpose as a power supply bypass capacitor; to supply
transient current, with the amplifier then providing the bulk
charge.
Typically, a low-value capacitor in the range of 10 pF to
100 pF provides the required transient charge reservoir.
The capacitance and the switching action of the ADC is
one of the worst loading scenarios that a high-speed
amplifier encounters. The resistor provides a simple
means of isolating the associated phase shift from the
feedback network and maintaining the phase margin of the
amplifier.
Typically, a low value resistor in the range of 10 Ω to 100 Ω
provides the required isolation. Together, the R and C form
a real pole in the s-plane located at the
frequency:
fP + 1
2pRC
16
If R is only 10 Ω, the amplifier is very heavily loaded above
the pole frequency, and generates excessive distortion.
DAC DRIVER APPLICATION
The THS3201 can be used as a high-performance DAC
output driver in applications like radio transmitter stages,
and arbitrary waveform generators. All high-performance
DACs have differential current outputs. Two THS3201s
can be used as a differential drive amplifier in these
applications as shown in Figure 56.
RPU on the DAC output is used to convert the output
current to voltage. The 24.9-Ω resistor and 47-pF capacitor
between each DAC output and the op amp input is used
to reduce the images generated at multiples of the
sampling rate. The values shown form a pole a 136 MHz.
ROUT sets the output impedance of each amplifier.
VS+
0.1 µF
AVDD
RG
RF
RPU
ROUT
24.9 Ω
IOUT1
THS3201
47pF
24.9 Ω
DAC
ROUT
IOUT2
47pF
RPU
RG
VOUT1
THS3201
VOUT2
RF
AVDD
VS−
0.1 µF
Figure 56. Differential DAC Driver Circuit
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
−50
POWER SUPPLY
Gain = +2
RL = 100 Ω
VO = 2 VPP
The performance of the THS3201 is dependent upon the
power supply. Slew rate, bandwidth, and distortion are
graphed against the power supply to highlight this
dependence. As the power supply is increased from ±5 V
to ±7.5 V, the slew rate increases, the bandwidth
increases, and the distortion improves.
11000
Rise
VS = ± 7.5 V
RF = 768 Ω
10000
Slew Rate − V/ µs
9000
3 rd Harmonic Distortion − dBc
−55
−60
−65
VS = ± 5 V
RF = 715 Ω
−70
−75
−80
−85
VS = ± 7.5 V
RF = 768 Ω
−90
−95
−100
1
8000
Rise
VS = ± 5 V
RF = 715 Ω
7000
6000
4000
100
Figure 59. 3rd Harmonic Distortion vs Frequency
Fall
VS = ± 7.5 V
RF = 768 Ω
5000
10
f − Frequency − MHz
3000
Fall
VS = ± 5 V
RF = 715 Ω
2000
1000
Gain = +2
RL = 100 Ω
0
0
1
2 3 4
5 6
7 8
VO − Output Voltage Step − VPP
9
10
7
Figure 57. Slew Rate vs Output Voltage Step
2nd Harmonic Distortion − dBc
−50
−55
VS = ± 5 V
RF = 715 Ω
−60
−65
VS = ± 7.5 V
RF = 768 Ω
−70
6
Noninverting Gain − dB
−45
VS = ± 7.5 V
RF = 768 Ω
5
4
VS = ± 5 V
RF = 715 Ω
3
2
Gain = +2
RL = 100 Ω
VO = 2 VPP
1
−75
0
−80
10
Gain = +2
RL = 100 Ω
VO = 2 VPP
−85
−90
−95
1
10
f − Frequency − MHz
100
100
1k
f − Frequency − Hz
10 k
Figure 60. Noninverting Small Signal
Frequency Response
Figure 58. 2nd Harmonic Distortion vs Frequency
17
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS3201 requires careful
attention to board layout parasitic and external component
types.
resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 kΩ, this parasitic
capacitance can add a pole and/or a zero that can
effect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
D
Recommendations that optimize performance include:
D
Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
D
Minimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-µF and 100 pF decoupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces
to minimize inductance between the pins and the
decoupling capacitors. The power supply connections
should always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should also
be used on the main supply pins. These may be
placed somewhat farther from the device and may be
shared among several devices in the same area of the
PC board. The primary goal is to minimize the
impedance seen in the differential-current return
paths. For driving differential loads with the THS3201,
adding a capacitor between the power supply pins
improves 2nd order harmonic distortion performance.
This also minimizes the current loop formed by the
differential drive.
D
18
Careful selection and placement of external
components preserve
the
high
frequency
performance of the THS3201. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Again,
keep their leads and PC board trace length as short as
possible. Never use wirebound type resistors in a high
frequency application. Since the output pin and
inverting input pins are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistors, if any, as close as possible to the
inverting input pins and output pins. Other network
components, such as input termination resistors,
should be placed close to the gain-setting resistors.
Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values
can create significant time constants that can degrade
performance. Good axial metal-film or surface-mount
Connections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces
(50 mils to 100 mils) should be used, preferably with
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need an RS
since the THS3201 is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in
fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance based on
board material and trace dimensions, a matching
series resistor into the trace from the output of the
THS3201 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
D
Socketing a high speed part like the THS3201 is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS3201 parts directly onto
the board.
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
PowerPAD DESIGN CONSIDERATIONS
The THS3201 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 61(a) and Figure 61(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
Figure 61(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be
achieved by providing a good thermal path away from the
thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 62. DGN PowerPAD PCB Etch and Via
Pattern
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 61. Views of Thermally Enhanced Package
19
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
PowerPAD PCB LAYOUT CONSIDERATIONS
1.
2.
3.
Prepare the PCB with a top side etch pattern as shown
in Figure 62. There should be etch for the leads as well
as etch for the thermal pad.
Place five holes in the area of the thermal pad. These
holes should be 10 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS3201
IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can
be larger because they are not in the thermal pad area
to be soldered so that wicking is not a problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS3201
PowerPAD package should make their connection to
the internal ground plane with a complete connection
around the entire circumference of the plated-through
hole.
6.
20
The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8.
With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
To maintain maximum output capabilities, the THS3201
does not incorporate automatic thermal shutoff protection.
The designer must take care to ensure that the design
does not violate the absolute maximum junction
temperature of the device. Failure may result if the
absolute maximum junction temperature of 150°C is
exceeded. For best performance, design for a maximum
junction temperature of 125°C. Between 125°C and
150°C, damage does not occur, but the performance of the
amplifier begins to degrade.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
P Dmax +
Tmax * T A
q JA
where:
PDmax is the maximum power dissipation in the
amplifier (W).
Tmax is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
For systems where heat dissipation is more critical, the
THS3201 is offered in an 8-pin MSOP with PowerPAD and
the THS3201 is available in the SOIC−8 PowerPAD
package offering even better thermal performance. The
thermal coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in the
graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows
the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number
SLMA002. The following graph also illustrates the effect of
not soldering the PowerPAD to a PCB. The thermal
impedance increases substantially which may cause
serious heat and performance issues. Be sure to always
solder the PowerPAD to the PCB for optimum
performance.
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
DESIGN TOOLS
Evaluation Fixture, Spice Models, and
Applications Support
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal an evaluation board has been developed for the
THS3201 operational amplifier. The board is easy to use,
allowing for straightforward evaluation of the device. The
evaluation board can be ordered through the Texas
Instruments web site, www.ti.com, or through your local
Texas Instruments sales representative. The schematic
diagram, board layers, and bill of materials of the
evaluation boards are provided below.
PD
J9*
PD − Maximum Power Dissipation − W
4.0
C8*
TJ = 125°C
R5
3.5
3.0
Vs+ 768 Ω
θJA = 58.4°C/W
2.5
2.0
7 8
2 _
R3
J1
Vin −
θJA = 98°C/W
0Ω
1.5
768 Ω
R2
U1
49.9 Ω
4 1
1.0
Vs −
0.0
−40
−20
0
20
40
60
80
100
J4
Vout
R7
Not Populated
J8*
PD Ref
0.5
θJA = 158°C/W
R6
6
3 +
J2
Vin+
TA − Free-Air Temperature − °C
49.9 Ω
C7*
R4
Results are With No Air Flow and PCB Size = 3”x3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 98°C/W for 8-Pin SOIC High Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
*Does Not Apply to the THS3201
J6
GND
Figure 63. Maximum Power Dissipation vs
Ambient Temperature
J7
VS−
VS−
FB1
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
C1
+
C6
22 µF 0.1 µF
C5
100 pF
TP1
VS+
C4
100 pF
J5
VS+
FB2
C3
0.1 µF
+
C2
22 µF
Figure 64. THS3201 EVM Circuit Configuration
21
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
Figure 65. THS3201 EVM Board Layout (Top
Layer)
Figure 67. THS3201 EVM Board Layout (Third
Layer, Power)
Figure 66. THS3201 EVM Board Layout (Second
Layer, Ground)
Figure 68. THS3201 EVM Board Layout (Bottom
Layer)
22
www.ti.com
SLOS416A − JUNE 2003 − REVISED JANUARY 2004
Table 2. Bill of Materials
THS3201DGN EVM
Description
SMD
Size
Ref Des
PCB
Quantity
Manufacturer’s Part Number
1
Bead, ferrite, 3 A, 80 Ω
1206
FB1, FB2
2
(Steward) HI1206N800R−00
2
Cap, 22 µF, tanatalum, 25V, 10%
D
C1, C2
2
(AVX) TAJD226K025R
3
Cap, 100 pF, ceramic, 5%, 150V
AQ12
C4, C5
2
(AVX) AQ12EM101JAJME
4
Cap, 0.1 µF, ceramic, X7R, 50V
0805
C3, C6
2
(AVX) 08055C104KAT2A
6
Open
0805
R7
1
7
Resistor, 49.9 Ω, 1/8W, 1%
0805
R6
1
(Phycomp) 9C08052A49R9FKHFT
9
Resistor, 768 Ω, 1/8W, 1%
0805
R3, R5
2
(Phycomp) 9C08052A7680FKHFT
10
Open
1206
C7, C8
2
Item
11
Resistor, 0 Ω, 1/4W, 1%
1206
R2
1
(KOA) RK73Z2BLTD
12
Resistor, 49.9 Ω, 1/4W, 1%
1206
R4
1
(Phycomp) 9C12063A49R9FKRFT
13
Test point, black
TP1
1
(Keystone) 5001
14
Open
J8, J9
2
15
Jack, Banana Recptance, 0.25” dia. hole
J5, J6, J7
3
(HH Smith) 101
16
Connector, edge, SMA PCB jack
J1, J2, J4
3
(Johnson) 142−0701−801
17
Standoff, 4−40 hex, 0.625” length
4
(Keystone) 1804
18
Screw, Phillips, 4−40, .250”
4
SHR−0440−016−SN
19
IC, THS3201
20
Board, printed circuit
NOTE: The components shown in the BOM were used in test by TI.
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF-amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS3201 is available through
either the Texas Instruments web site (www.ti.com) or as
one model on a disk from the Texas Instruments Product
Information Center (1–800–548–6132). The PIC is also
available for design assistance and detailed product
information at this number. These models do a good job of
predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between the
package types in their small-signal ac performance.
Detailed information about what is and is not modeled is
contained in the model file itself.
U1
1
(TI) THS3201DGN
1
(TI) Edge # 6447972 Rev.A
ADDITIONAL REFERENCE MATERIAL
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief
(SLMA002)
Voltage Feedback vs. Current Feedback amplifiers,
(SLVA051)
Current Feedback
(SLOA021)
Analysis
and
Compensation
Current Feedback Amplifiers: Review, Stability, and
Application (SBOA081)
Effect of parasitic capacitance in op amp circuits
(SLOA013)
23
PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS3201D
ACTIVE
SOIC
D
8
THS3201DBVR
ACTIVE
SOT-23
DBV
5
THS3201DBVT
ACTIVE
SOT-23
DBV
THS3201DGK
ACTIVE
MSOP
THS3201DGKR
ACTIVE
THS3201DGN
75
MSL Peak Temp (3)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGK
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
MSOPPower
PAD
DGN
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3201DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3201DR
ACTIVE
SOIC
D
8
2500
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
80
Pb-Free
(RoHS)
Lead/Ball Finish
Pb-Free
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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