)6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 2.0 VSS_I2C SCL 25 24 SDA VSS 23 26 27 22 VSS VDD_I2C VDD SDRAM_17 28 21 VSS SDRAM_16 29 20 SDRAM_9 VDD SDRAM_8 VDD 30 19 VSS 31 18 SDRAM_7 32 33 SDRAM_10 VSS 34 SDRAM_11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (reserved) (reserved) VDD SDRAM_0 SDRAM_1 VSS VDD SDRAM_2 SDRAM_3 VSS CLK_IN VDD SDRAM_4 SDRAM_5 VSS VDD SDRAM_6 VSS VDD 18 35 OE 1 SDRAM_(0:1) SDRAM_(2:3) 48-pin SSOP SDRAM_(4:5) SCL 15 VSS_I2C 16 23 VSS SDRAM_13 24 SDRAM_17 VDD 25 17 VSS 26 18 SDRAM_14 27 VDD SDRAM_15 28 19 VDD SDRAM_(10:11) 20 VSS VDD SDRAM_(8:9) OE Figure 3: Pin Configuration (FS6051) VSS VDD VSS SDRAM_(6:7) CLK_IN 21 VSS VDD VSS_I2C SDRAM_12 SCL 22 Serial Interface VDD VSS 38 VDD VSS VDD SDA 36 SDRAM_12 39 FS6050 Figure 1: Block Diagram (FS6050) VDD_I2C 37 SDRAM_13 Figure 2: Pin Configuration (FS6050) 40 FS6050: 18 clock outputs in a 48-pin SSOP FS6051: 10 clock outputs in a 28-pin SOIC, SSOP FS6053: 13 clock outputs in a 28-pin SOIC FS6054: 14 clock outputs in a 28-pin SOIC 41 • • • • VSS • 2 VDD Serial interface I/O meet I C specifications; all other I/O are LVTTL/LVCMOS-compatible Five differerent pin configurations available: 42 • SDRAM_14 Less than 5ns propagation delay Output impedance: 17Ω at 0.5VDD 43 Clock outputs skew-matched to less than 250ps • • SDRAM_15 • 44 Output enable pin tristates all clock outputs to facilitate board testing VDD • 45 Supports up to four SDRAM DIMMs 2 Uses either I C-bus or SMBus serial interface with Read and Write capability for individual clock output control (reserved) • • The FS6050 family of CMOS clock fanout buffer ICs are designed for high-speed motherboard applications, such ® as Intel Pentium II PC100-based systems with 100MHz SDRAM. Up to eighteen buffered, non-inverting clock outputs are fanned-out from one clock input. Individual clocks are skew matched to less than 250ps at 100MHz. Multiple power and ground supplies reduce the effects of supply noise on device performance. 2 Under I C-bus control, individual clock outputs may be turned on or off. An active-low output enable is available to force all the clock outputs to a tristate level for system testing. 46 Generates up to eighteen low-skew, non-inverting clocks from one clock input (reserved) • Description 47 Features 48 1.0 VSS VDD SDRAM_(12:13) FS6051 SDRAM_17 VSS 4 5 6 7 8 9 10 11 12 13 14 VDD SDRAM_2 SDRAM_3 VSS CLK_IN VDD SDRAM_16 VSS VDD_I2C SDA 3 VSS SDRAM_1 VSS VDD 2 SDRAM_16 OE SDRAM_0 VSS VDD 1 SDRAM_(14:15) VDD VSS VDD 28-pin SOIC, SSOP FS6050 Additional pin configurations are noted on Page 2. Intel and Pentium are registered trademarks of Intel Corporation. I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 4.5.99 ,62 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN (FS6050) PIN (FS6051) PIN (FS6053) PIN (FS6054) TYPE NAME 11 25 24 4 5 8 9 13 14 17 18 31 32 35 36 40 41 44 45 21 28 38 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 9 15 14 2 3 6 7 22 23 26 27 11 18 20 9 15 14 2 3 6 7 10 11 18 19 22 23 26 27 12 - 9 15 14 2 3 6 7 10 11 18 19 22 23 26 27 12 17 20 DI DIU DIUO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DIU CLK_IN SCL SDA SDRAM_0 SDRAM_1 SDRAM_2 SDRAM_3 SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7 SDRAM_8 SDRAM_9 SDRAM_10 SDRAM_11 SDRAM_12 SDRAM_13 SDRAM_14 SDRAM_15 SDRAM_16 SDRAM_17 OE Output enable tristates all clock outputs when low 1, 5, 10, 19, 24, 28 1, 5, 20, 24, 28 1, 5, 24, 28 P VDD 3.3V ± 5% power supply for SDRAM clock buffers 23 13 13 13 P VDD_I2C 3.3V ± 5% power supply for serial communications 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 4, 8, 12, 17, 21, 25 4, 8, 17, 21, 25 4, 8, 21, 25 P VSS 26 16 16 16 P VSS_I2C 1, 2, 47, 48 - - - - (reserved) Ground for SDRAM clock buffers Ground for serial communications Reserved SCL 15 SDRAM_17 SDRAM_8 VSS_I2C 16 17 SDRAM_9 SDRAM_13 23 18 VDD 24 OE VSS 25 19 SDRAM_14 26 VSS SDRAM_15 27 20 VDD 28 SDRAM_12 SCL 21 VSS_I2C 15 22 VSS 16 Figure 5: Pin Configuration (FS6054) 17 VDD 20 SDRAM feedback clock outputs (Byte 2) SDRAM_9 VSS 21 SDRAM clock outputs (Byte 1) SDRAM_8 SDRAM_12 22 SDRAM clock outputs (Byte 0) 18 SDRAM_13 23 Clock input for SDRAM clock outputs Serial clock input Serial data input/output 19 VSS VDD SDRAM_14 26 24 SDRAM_15 27 25 VDD 28 Figure 4: Pin Configuration (FS6053) DESCRIPTION FS6054 7 8 9 10 11 12 13 14 VSS CLK_IN SDRAM_6 SDRAM_7 SDRAM_16 VDD_I2C SDA 14 SDA SDRAM_3 13 VDD_I2C 6 12 SDRAM_16 SDRAM_2 11 SDRAM_7 5 10 SDRAM_6 VDD 9 CLK_IN 4 8 VSS VSS 7 SDRAM_3 3 6 SDRAM_2 SDRAM_1 5 VDD 2 4 VSS 1 3 SDRAM_1 VDD 2 SDRAM_0 1 VDD SDRAM_0 FS6053 4.5.99 ,62 2 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 3.0 3.2 Programming Information A logic-one written to a valid bit location turns on the assigned output clock. Likewise, a logic-zero written to a valid bit location turns off the assigned output clock. Any unused or reserved register bits should be cleared to zero. Serial bits are written to this device in the order shown in Table 3. Table 2: Clock Enable CONTROL INPUTS CLOCK OUTPUTS (MHz) OE SDRAM_0:17 0 tristate 1 CLK_IN Register Programming Table 3: Register Summary 3.1 Power-Up Initialization All outputs are enabled and active upon power-up, and all output control register bits are initialized to one. The outputs must be configured at power-up and are not expected to be configured during normal operation. Inactive outputs are held low and are disabled from switching. SERIAL BIT DATA BYTE CLOCK OUTPUT 0 (MSB) SDRAM_7 1 SDRAM_6 2 SDRAM_5 3 Byte 0 SDRAM_4 4 SDRAM Control Register 0 SDRAM_3 5 3.1.1 Unused Outputs Outputs that are not used in versions of this device with a reduced pinout are still operational internally. To reduce power dissipation and crosstalk effects from the unloaded outputs, it is recommended that these outputs be shut off via the Control Registers. SDRAM_2 6 SDRAM_1 7 (LSB) SDRAM_0 8 (MSB) SDRAM_15 9 SDRAM_14 10 SDRAM_13 11 Byte 1 SDRAM_12 12 SDRAM Control Register 1 SDRAM_11 13 SDRAM_10 14 SDRAM_9 15 (LSB) SDRAM_8 16 (MSB) SDRAM_17 17 SDRAM_16 18 Reserved 19 Byte 2 Reserved 20 SDRAM Control Register 2 Reserved 21 Reserved 22 Reserved 23 (LSB) Reserved 4.5.99 ,62 3 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 4: Byte 0 - SDRAM Control Register 0 REGISTER BIT CLOCK OUTPUT DESCRIPTION OUTPUT PIN (FS6050) OUTPUT PIN (FS6051) OUTPUT PIN (FS6053) OUTPUT PIN (FS6054) 7 SDRAM_7 On (1) / Off (0) Pin 18 - Pin 11 Pin 11 6 SDRAM_6 On (1) / Off (0) Pin 17 - Pin 10 Pin 10 5 SDRAM_5 On (1) / Off (0) Pin 14 - - - 4 SDRAM_4 On (1) / Off (0) Pin 13 - - - 3 SDRAM_3 On (1) / Off (0) Pin 9 Pin 7 Pin 7 Pin 7 2 SDRAM_2 On (1) / Off (0) Pin 8 Pin 6 Pin 6 Pin 6 1 SDRAM_1 On (1) / Off (0) Pin 5 Pin 3 Pin 3 Pin 3 0 SDRAM_0 On (1) / Off (0) Pin 4 Pin 2 Pin 2 Pin 2 Table 5: Byte 1 - SDRAM Control Register 1 REGISTER BIT CLOCK OUTPUT DESCRIPTION OUTPUT PIN (FS6050) OUTPUT PIN (FS6051) OUTPUT PIN (FS6053) OUTPUT PIN (FS6054) 15 SDRAM_15 On (1) / Off (0) Pin 45 Pin 27 Pin 27 Pin 27 14 SDRAM_14 On (1) / Off (0) Pin 44 Pin 26 Pin 26 Pin 26 13 SDRAM_13 On (1) / Off (0) Pin 41 Pin 23 Pin 23 Pin 23 12 SDRAM_12 On (1) / Off (0) Pin 40 Pin 22 Pin 22 Pin 22 11 SDRAM_11 On (1) / Off (0) Pin 36 - - - 10 SDRAM_10 On (1) / Off (0) Pin 35 - - - 9 SDRAM_9 On (1) / Off (0) Pin 32 - Pin 19 Pin 19 8 SDRAM_8 On (1) / Off (0) Pin 31 - Pin 18 Pin 18 Table 6: Byte 2 - SDRAM Control Register 2 REGISTER BIT CLOCK OUTPUT DESCRIPTION OUTPUT PIN (FS6050) OUTPUT PIN (FS6051) OUTPUT PIN (FS6053) OUTPUT PIN (FS6054) 23 SDRAM_17 On (1) / Off (0) Pin 28 Pin 18 - Pin 17 22 SDRAM_16 On (1) / Off (0) Pin 21 Pin 11 Pin 12 Pin 12 21 Reserved (set to 0) - - - - 20 Reserved (set to 0) - - - - 19 Reserved (set to 0) - - - - 18 Reserved (set to 0) - - - - 17 Reserved (set to 0) - - - - 16 Reserved (set to 0) - - - - 4.5.99 ,62 4 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 4.0 4.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the data registers are filled will overflow from the last register into the first register, then the second, and so on, in a first-in, first-overwritten fashion. Dual Serial Interface Control This integrated circuit is a read/write slave device that 2 supports both the Inter IC Bus (I C-bus) and the System Management Bus (SMBus) two-wire serial interface protocols. The unique device address that is written to the device determines whether the part expects to receive 2 SMBus commands or I C commands. Since SMBus is 2 derived from the I C-bus, the protocol for both bus types is very similar. In general, the bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. Bus logic levels and timing parameters noted herein fol2 low I C-bus convention. Logic levels are based on a percentage of VDD. A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS). 4.1 4.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to allow the master to generate a STOP condition. Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line when the clock line is high is interpreted by the device as a START or STOP 2 condition. Both I C-bus and SMBus protocols define the following conditions on the bus. Refer to Figure 12: Bus Timing Data for more information. 4.2 Bus Operation and Commands All programmable registers can be accessed via the bidirectional two wire digital interface. The device accepts the Random Register Read/Write and the Sequential 2 Register Read/Write I C commands. The device also supports the Block Read/Write SMBus commands. 4.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 4.2.1 I2C-bus and SMBus Device Addressing After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W 2 bit. Note that every device on an I C-bus or SMBus must have a unique address to avoid bus conflicts. For an SMBus interface, the address of the device is: 4.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 4.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. A6 A5 A4 A3 A2 A1 A0 1 1 0 1 0 0 1 4.5.99 ,62 5 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 2 For an I C-bus interface, the device can support two de2 vice addresses to permit multiple devices on one I C-bus. The A2 address bit is ignored and can be set to either a one or a zero. 2 Therefore, for an I C-bus interface the device address is: 4.2.2 4.2.4 I2C-bus: Sequential Register Write Procedure Sequential write operations, as shown in Figure 8, allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the Random Register Write if several registers must be written. To initiate a write procedure, the R/W bit that is transmit2 ted after the seven-bit I C device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave’s address pointer. Following an acknowledge by the slave, the master is allowed to write data up to the last addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a Sequential Register Write. 4.2.3 I2C-bus: Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, as shown in Figure 7, the R/W bit that is transmitted after the 2 seven-bit I C address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave’s address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave’s address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 4.2.5 I2C-bus: Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure, as shown in Figure 9, is more efficient than the Random Register Read if several registers must be read from. To perform a read procedure, the R/W bit that is trans2 mitted after the seven-bit I C address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave’s address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave’s address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. A6 A5 A4 A3 A2 A1 A0 1 0 1 1 X 0 0 I2C-bus: Random Register Write Procedure Random write operations, as shown in Figure 6, allow the master to directly write to any register. To initiate a write procedure, the R/W 2 bit that is transmitted after the seven-bit I C device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave’s address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a Register Write, the data that has been transferred is ignored. 4.5.99 ,62 6 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Figure 6: Random Register Write Procedure (I2C-bus) S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A Register Address A P Data Acknowledge START Command DATA Acknowledge STOP Condition WRITE Command From bus host to device Acknowledge From device to bus host Figure 7: Random Register Read Procedure (I2C-bus) S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A S DATA A P Data Acknowledge Repeat START WRITE Command From bus host to device R A 7-bit Receive Device Address Register Address Acknowledge START Command DEVICE ADDRESS Acknowledge STOP Condition READ Command NO Acknowledge From device to bus host Figure 8: Sequential Register Write Procedure (I2C-bus) S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS DATA Register Address Acknowledge START Command A A DATA DATA Data Data Acknowledge A Acknowledge Data Acknowledge WRITE Command From bus host to device A P Acknowledge STOP Command From device to bus host Figure 9: Sequential Register Read Procedure (I2C-bus) S DEVICE ADDRESS 7-bit Receive Device Address W A REGISTER ADDRESS Register Address Acknowledge START Command WRITE Command From bus host to device A S DEVICE ADDRESS R A 7-bit Receive Device Address A DATA Data Acknowledge Repeat START Acknowledge DATA READ Command A P Data Acknowledge NO Acknowledge STOP Command From device to bus host 4.5.99 ,62 7 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 registers, starting by default at Register 0. To perform a Block Read procedure the R/W bit that is transmitted after the seven-bit SMBus address is a logic-low, as in the Block Write procedure. The write bit resets the register address pointer to zero. Following an acknowledge of the SMBus address and R/W bit by the slave device, a command code is written. It is defined that all eight bits of the command code must be zero (0). Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave’s address pointer is set. The slave SMBus address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then will expect a byte count value (which will be ignored). Following the byte count value, the device will take command of the bus and will transmit all the data beginning with Register 0. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. If the master does not want to receive all the data, the master can not acknowledge the last data byte and then can issue a STOP condition of the next clock. 4.2.6 SMBus: Block Write The Block Write command permits the master to write several bytes of data to sequential registers, starting by default at Register 0. The Block Write command, as noted in Figure 10, begins with the seven-bit SMBus device address followed by a logiclow R/W bit to begin a Write command. Following an acknowledge of the SMBus address and R/W bit by the slave device, a command code is written. It is defined that all eight bits of the command code must be zero (0). After the command code of zero and an acknowledge, the host then issues a byte count that describes the number of data bytes to be written. According to SMBus convention, the byte count should be a value between 0 and 32; however this slave device ignores the byte count value. Following an acknowledge of the byte count, data bytes may be written starting with Register 0 and incrementing sequentially. An acknowledge by the device between each byte of data must occur before the next data byte is sent. SMBus 4.2.7 SMBus: Block Read The Block Read command, shown in Figure 11, permits the master to read several bytes of data from sequential Figure 10: Block Write (SMBus) S DEVICE ADDRESS W A 7-bit Receive Device Address A BYTE COUNT = N Command Code A DATA BYTE 1 Byte Count WRITE Command From bus host to device DATA BYTE N Data Acknowledge START Command A A P Data Acknowledge Acknowledge Acknowledge Acknowledge STOP Command From device to bus host Figure 11: Block Read (SMBus) S DEVICE ADDRESS W A 7-bit Receive Device Address A S Command Code Acknowledge START Command WRITE Command From bus host to device DEVICE ADDRESS 7-bit Receive Device Address Repeat START Acknowledge R A BYTE COUNT = N Byte Count Acknowledge READ Command A DATA BYTE 1 Data Acknowledge Acknowledge A DATA BYTE N A P Data NO Acknowledge STOP Command From device to bus host 4.5.99 ,62 8 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 5.0 Electrical Specifications Table 7: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage, dc, Clock Buffers (VSS = ground) SYMBOL MIN. MAX. UNITS V VDD VSS-0.5 7 VDD_I2C VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 °C Ambient Temperature Range, Under Bias TA -55 125 °C Junction Temperature TJ 125 °C Supply Voltage, dc, Serial Communications Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 260 °C 2 kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 8: Operating Conditions PARAMETER Supply Voltage, Clock Buffers SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS V VDD 3.3V ± 5% 3.135 3.3 3.465 Supply Voltage, Serial Communications VDD_I2C 3.3V ± 5% 3.135 3.3 3.465 V Ambient Operating Temperature Range TA 0 70 °C Input Frequency fCLK 0 133 MHz Output Load Capacitance CL 30 pF 400 kb/s Serial Data Transfer Rate Standard mode 10 100 4.5.99 ,62 9 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 9: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall (FS6050) Supply Current, Dynamic, with Loaded Outputs IDD fCLK = 100MHz; VDD = 3.47V 180 360 mA Supply Current, Static IDDL Outputs low; VDD = 3.47V 0.75 3 mA Serial Communication Inputs/Output (SDA, SCL) High-Level Input Voltage VIH Outputs low 2.31 VDD+0.3 V Low-Level Input Voltage VIL Outputs low VSS-0.3 0.9 V Hysteresis Voltage * Vhys Outputs low 1.0 1 µA 15 µA V High-Level Input Current IIH -1 Low-Level Input Current (pull-up) IIL Outputs low; VIH = 0.4V, VDD = 3.47V. Note: SDA requires an external pull-up to drive the data bus. 5 11 Low-Level Output Sink Current (SDA) IOL VOL = 0.4V 10 25 mA Output Enable Input (OE) High-Level Input Voltage VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V High-Level Input Current IIH -1 1 µA Low-Level Input Current (pull-up) IIL 30 µA V VIH = 0.4V; VDD = 3.47V 10 22 V Clock Input (CLK_IN) High-Level Input Voltage VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V II -1 1 µA Input Leakage Current Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance IOH min VDD = 3.135V, VO = 2.0V IOH max VDD = 3.465V, VO = 3.135V IOL min VDD = 3.135V, VO = 1.0V IOL max VDD = 3.465V, VO = 0.4V -54 -65 -28 54 -46 69 33 53 zOH VO = 0.5VDD; output driving high 10 17.9 24 zOL VO = 0.5VDD; output driving low 10 16.3 24 -5 5 mA mA Ω µA Tristate Output Current IOZ Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -106 mA Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max. 107 mA 4.5.99 ,62 10 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 10: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. CONDITIONS/DESCRIPTION CLOCK (MHz) PARAMETER SYMBOL MIN. TYP. Clock Skew, Maximum; SDRAM_0 to any SDRAM pin * tskw Measured on the rising edge at 1.5V; CL = 20pF 66.67 182 100 228 tPLH(min) Measured on the rising edge at 1.5V; CL = 20pF 66.67 3.7 100 3.8 tPLH(max) Measured on the rising edge at 1.5V; CL = 30pF 66.67 3.7 100 4.0 Measured on the rising edge at 1.5V; CL = 20pF 66.67 3.9 100 3.8 Measured on the rising edge at 1.5V; CL = 30pF 66.67 4.2 100 4.0 66.67 1.0 MAX. UNITS Overall Propagation Delay, Average; CLK_IN to any SDRAM pin * tPHL(min) tPHL(max) ps ns Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer) tr(min) VO = 0.4V to 2.4V; CL = 20pF Rise Time * tr(max) tf(min) VO = 0.4V to 2.4V; CL = 30pF VO = 2.4V to 0.4V; CL = 20pF Fall Time * tf(max) VO = 2.4V to 0.4V; CL = 30pF tKH(min) VO = 2.4V; CL = 20pF Clock High Time * tKH(max) tKL(min) VO = 2.4V; CL = 30pF Tristate Enable Delay * Tristate Disable Delay * tPZH tPLZ tPHZ 1.2 100 1.0 66.67 1.0 100 0.7 66.67 1.1 100 0.8 66.67 6.5 100 3.8 66.67 6.5 100 3.8 6.5 100 4.6 66.67 6.3 100 4.5 From rising edge to rising edge at 1.5V; CL = 20pF 66.67 49 100 45 From rising edge to rising edge at 1.5V; CL = 30pF 66.67 50 VO = 0.4V; CL = 20pF VO = 0.4V; CL = 30pF Duty Cycle * tPZL 0.9 66.67 66.67 Clock Low Time * tKL(max) 100 Output tristated to output active; CL = 20pF Output active to output tristated; CL = 20pF 100 ns ns ns ns % 46 4.7 4.6 6.3 7.9 ns ns 4.5.99 ,62 11 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 11: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION SCL MIN. MAX. UNITS 10 400 kHz Clock frequency fSCL Bus free time between STOP and START tBUF 4.7 µs Set up time, START (repeated) tsu:STA 4.7 µs Hold time, START thd:STA 4.0 µs Set up time, data input tsu:DAT SDA 250 ns Hold time, data input thd:DAT SDA 300 ns Output data valid from clock Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP tAA Rise time, data and clock tr SDA, SCL Fall time, data and clock tf SDA, SCL High time, clock tH SCL tL SCL Low time, clock Set up time, STOP 3.5 µs 1000 ns 300 tsu:STO ns µs 4.0 4.7 µs 4.0 µs Figure 12: Bus Timing Data ~ ~ SCL ~ ~ thd:STA tsu:STA tsu:STO SDA ~ ~ ADDRESS OR DATA VALID START DATA CAN CHANGE STOP Figure 13: Data Transfer Sequence tH SCL tr ~ ~ tf tL tsu:STA thd:STA tAA tAA ~ ~ SDA IN tsu:DAT tsu:STO ~ ~ thd:DAT tBUF SDA OUT 4.5.99 ,62 12 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Figure 14: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer) Voltage (V) Low Drive Current (mA) MIN. TYP. MAX. 0 0 0 0 0.4 23 34 0.65 35 0.85 Voltage (V) High Drive Current (mA) 220 MIN. TYP. MAX. 0 -72 -116 -198 53 1 -72 -116 -198 140 52 83 1.4 -68 -110 -188 120 43 65 104 1.5 -67 -107 -184 1 49 74 118 1.65 -64 -103 -177 1.4 61 93 152 1.8 -60 -98 -170 1.5 64 98 159 2 -54 -90 -157 1.65 67 103 168 2.4 -39 -69 -126 200 180 160 100 1.8 70 108 177 2.6 -30 -56 -107 1.95 72 112 184 3.135 0 -15 -46 3.135 72 112 204 3.3 0 -23 112 204 3.465 3.6 0 $ 80 P 60 W 40 Q H 20 U U 0 X & -20 W X -40 S W X -60 2 0 0.5 1 1.5 2 2.5 3 3.5 4 -80 -100 -120 -140 -160 MIN. -180 TYP. -200 MAX. -220 30 Ω 50 Ω 2XWSXW9ROWDJH9 90 Ω Figure 15: DC Measurement Points Figure 17: Timing Measurement Points τKP 3.3V VOH 3.3 = 2.4V tr VIH 3.3 = 2.0V 1.5V tf 2.4V tKH 1.5V VIL 3.3 = 0.8V VOL 3.3 = 0.4V (device interface) tKL (system interface) 0.4V Duty Cycle VDD Figure 16: Clock Skew Measurement Point 50% 50% VSS 1.5V 3.3V 50% tPLZ 90% 1.5V VOL 10% tskw 3.3V tPZL VOH 50% tPHZ tPHZ 4.5.99 ,62 13 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 6.0 Package Information Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions DIMENSIONS INCHES 48 MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 0.110 2.41 2.79 A1 0.008 0.016 0.203 0.406 A2 0.088 0.092 2.24 2.34 B 0.008 0.0135 0.203 0.343 C 0.005 0.010 0.127 0.254 D 0.620 0.630 15.75 16.00 E 0.292 0.299 7.42 7.59 e 0.025 BSC E H XT 1 ALL RADII: 0.005" TO 0.01" B 7° typ. e 0.64 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.410 L 0.024 0.040 0.610 1.02 Θ 0° 8° 0° 8° A2 D A A1 BASE PLANE C θ L SEATING PLANE Table 13: 48-pin SSOP (7.5mm/0.300") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 93 °C/W Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s Lead Inductance, Self L11 Center lead 3.3 nH Lead Inductance, Mutual L12 Center lead to any adjacent lead 1.6 nH Lead Capacitance, Bulk C11 Center lead to VSS 0.6 pF Lead Capacitance, Mutual C12 Center lead to any adjacent lead 0.2 pF 4.5.99 ,62 14 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 14: 28-pin SOIC (7.5mm/0.300") Package Dimensions DIMENSIONS INCHES 28 MILLIMETERS MIN. MAX. MIN. MAX. A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 A2 0.08 0.100 2.05 2.55 B 0.013 0.013 0.33 0.51 C 0.009 0.009 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.05 BSC E H XT 1 ALL RADII: 0.005" TO 0.01" B e 7° typ. h x 45° 1.27 BSC H 0.393 0.419 10.00 10.65 h 0.010 0.030 0.25 0.75 L 0.016 0.05 0.40 1.27 Θ 0° 8° 0° 8° A2 D A1 BASE PLANE A C θ L SEATING PLANE Table 15: 28-pin SOIC (7.5mm/0.300") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 80 °C/W Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s Lead Inductance, Self L11 Center lead 2.5 nH Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.85 nH Lead Capacitance, Bulk C11 Center lead to VSS 0.42 pF Lead Capacitance, Mutual C12 Center lead to any adjacent lead 0.08 pF 4.5.99 ,62 15 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions DIMENSIONS INCHES 28 MILLIMETERS MIN. MAX. MIN. MAX. A 0.068 0.078 1.73 2.00 A1 0.002 0.008 0.05 0.21 A2 0.066 0.07 1.68 1.78 B 0.01 0.015 0.25 0.38 C 0.005 0.008 0.13 0.20 D 0.396 0.407 10.07 10.33 E 0.205 0.212 5.20 5.38 e 0.028 BSC E 1 B ALL RADII: 0.005" TO 0.01" e 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 0.037 0.55 0.95 Θ 0° 8° 0° 8° H XT A2 D BASE PLANE A 7° typ. C A1 θ L SEATING PLANE Table 17: 28-pin SSOP (5.3mm/0.209") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 97 °C/W Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s Lead Inductance, Self L11 Center lead 2.24 nH Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.95 nH Lead Capacitance, Bulk C11 Center lead to VSS 0.25 pF Lead Capacitance, Mutual C12 Center lead to any adjacent lead 0.07 pF 4.5.99 ,62 16 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 7.0 Ordering Information DEVICE NUMBER FS6050 FS6051 FS6053 FS6054 ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11257-801 48-pin (7.5mm/0.300”) SSOP 0°C to 70°C (Commercial) Tape and Reel 11257-811 48-pin (7.5mm/0.300”) SSOP 0°C to 70°C (Commercial) Tube 11257-802 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel 11257-812 28-pin (7.5mm/0.209”) SOIC 0°C to 70°C (Commercial) Tube 11257-806 28-pin (5.3mm/0.209”) SSOP 0°C to 70°C (Commercial) Tape and Reel 11257-816 28-pin (5.3mm/0.209”) SSOP 0°C to 70°C (Commercial) Tube 11257-803 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel 11257-813 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tube 11257-804 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel 11257-814 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tube 2 Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Companies conveys 2 2 a license under Philips I C Patent Rights to use these components in an I C system, provided that the system conforms 2 to the I C Standard Specification as defined by Philips. Copyright © 1998 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: [email protected] 4.5.99 ,62 17 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 8.0 Application Information 8.1 Reduction of EMI Figure 18: Board Layout CLK GND VOID The primary concern when designing the board layout for this device is the reduction of electromagnetic interference (EMI) generated by the 18 copies of the 100MHz SDRAM clock. It is assumed the reader is familiar with basic transmission line theory. 1 48 2 47 RS 4 45 RS 5 44 1000pF 8.1.1 Layout Guidelines To obtain the best performance, noise should be minimized on the power and ground supplies to the IC. Observe good high-speed board design practices, such as: Use multi-layer circuit boards with dedicated low impedance power and ground planes for the device (denoted as CLK VDD and CLK GND in Figure 18). The device power and ground planes should be completely isolated from the motherboard power and ground planes by a void in the power planes. Several low-pass filters using low impedance ferrite EHDGV DW 0+] DUH UHFRPPHQGHG WR GHFRuple the device power and ground planes from the motherboard power and ground planes (MB VDD and MB GND). The beads should span the gap between the power and ground planes. Seven beads for power and seven beads for ground are suggested (14 total) so that the clock rise times (1V/ns) can be maintained. Place 1000pF bypass capacitors as close as possible to the power pins of the IC. Use RF-quality lowinductance multi-layer ceramic chip capacitors. Six capacitors is optimal, one on each power/ground grouping as shown in Figure 18. Load similar clock outputs equally, and keep output loading as light as possible to help reduce clock skew and power dissipation. Use equal-length clock traces that are as short as possible. Rounded trace corners help reduce reflections and ringing in the clock signal. The clock traces must never cross the void area between power/ground planes. Each trace must have a complete plane (either VDD or GND) under the complete length of the trace. MB GND RS RS 1000pF RS 8 41 RS RS 9 40 RS 11 38 RS 13 36 RS RS 14 35 RS RS 17 32 RS 18 31 1000pF 1000pF 1000pF RS RS 1000pF RS 21 28 24 25 RS MB VDD CLK VDD Component Layer MB GND CLK GND MB GND MB VDD CLK VDD MB VDD Signal Layer 8.1.2 Output Driver Termination A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal reflections. Figure 19: Series Termination zO DRIVER RS LINE zL RECEIVE 4.5.99 ,62 18 )6)6)6)6 /RZ6NHZ&ORFN)DQRXW%XIIHU,&V XT April 1999 pacitance, and the number of connected devices with their associated input currents. Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors on both lines. A guideline is Series termination adds no dc loading to the driver, and requires less power than other resistive termination methods. Further, no extra impedance exists from the signal line to a reference voltage, such as ground. As shown in Figure 19, the sum of the driver’s output impedance (zO) and the series termination resistance (RS) must equal the line impedance (zL). That is, RP < RS = z L − zO . where tr is the maximum rise time (minus some margin) 2 and Cbus is the total bus capacitance. Assuming an I C 2 device on each DIMM, an I C controller, the clock buffer, and two other bus devices results in values in the 5kΩ to 7kΩ range. Use of a series resistor to provide protection against high voltage spikes on the bus will alter the values for RP. Note that when the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full signal amplitude. Vi = V tr , 2 × Cbus ( z O + RS ) V = ( z O + RS ) + z L 2 The full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. Note also that the voltage at the receive end must add up to a signal amplitude that meets the receiver switching thresholds. The slew rate of the signal is also reduced due to the additional RC delay of the load capacitance and the line impedance. Also note that the output driver impedance will vary slightly with the output logic state (high or low). Figure 20: Connections to the Serial Bus RP SDA RP SCL RS RS (optional) (optional) RS Data In Clock Out Dynamic Power Dissipation TRANSMITTER High-speed clock drivers require careful attention to power dissipation. Transient power (PT) consumption can be derived from Clock In Data Out RECEIVER 8.3.1 For More Information More detailed information on serial bus design can be 2 obtained from SMBus and I C Bus Design, available from the Intel Corporation at http://www.intel.com. 2 Information on the I C-bus can be found in the document 2 The I C-bus And How To Use It (Including Specifications), available from Philips Semiconductors at http://www-us2.semiconductors.philips.com. Additional information on the System Management Bus can be found in the System Management Bus Specification, available from the Smart Battery System Implementers’ Forum at http://www.sbs-forum.org. PT = VDD × C load × f CLK × N SW 2 where Cload is the load capacitance, VDD is the supply voltage, fCLK is the clock frequency, and Nsw is the number of switching outputs. The internal heat (junction temperature, TJ) generated by the power dissipation can be calculated from TJ = Θ JA × PT + TA where ΘJA is the package thermal resistance, TA is the ambient temperature, and PT is derived above. 8.3 (optional) Data In Data Out 8.2 RS (optional) Serial Communications Connection of devices to a standard-mode implementa2 tion of either the I C-bus or the SMBus is similar to that shown in Figure 20. Selection of the pull-up resistors (RP) and the optional series resistors (RS) on the SDA and SCL lines depends on the supply voltage, the bus ca4.5.99 ,62 19