ETC FS6261-01

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0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
1.0
•
2.0
®
Generates clocks required for Intel i820 based
desktop and workstation systems, including:
♦
Four enabled 2.5V 133/100MHz CPU Front Side
Bus (FSB) clocks
♦
Two 2.5V CPU/2 clocks for synchronous memory
♦
Seven enabled 3.3V PCI bus clocks and one
free-running PCI clock
♦
Four enabled 3.3V 66MHz AGP clocks
♦
Three 2.5V 16.67MHz APIC bus clocks
♦
Two 3.3V 14.318MHz REF clocks
♦
•
Features
The FS6261-01 is a CMOS clock generator IC designed
for high-speed motherboard applications. Two different
frequencies can be selected for the CPU clocks via two
SEL pins. Glitch-free stop clock control of the CPU, AGP
(66MHz) and PCI clocks is provided. A low current
power-down mode is available for mobile applications.
Separate clock buffers provide for a 2.5V voltage range
on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks.
Figure 2: Pin Configuration
One 3.3V 48MHz USB clock
CPU clock cycle – cycle jitter < 150ps p-p
Non-linear spread-spectrum modulation
(-0.5% at 31.5kHz)
•
Supports test mode and tristate output control
Figure 1: Block Diagram
XIN
XOUT
Crystal
Oscillator
VDD_R
56
VDD_A
2
55
APIC_2
REF_1
3
54
APIC_1
VDD_R
4
53
APIC_0
XIN
5
52
VSS_A
XOUT
6
51
VDD_C2
VSS_P
7
50
CPU/2_1
PCI_F
8
49
CPU/2_0
PCI_1
9
48
VSS_C2
VDD_P
10
47
VDD_C
PCI_2
11
46
CPU_3
PCI_3
12
45
CPU_2
VSS_P
13
44
VSS_C
PCI_4
14
43
VDD_C
PCI_5
15
42
CPU_1
VDD_P
16
41
CPU_0
PCI_6
17
PCI_7
40
VSS_C
18
39
VDD
VSS_P
19
38
VSS
VSS_66
20
37
PCI_STOP#
CK66_0
21
36
CPU_STOP#
VDD_C2
CK66_1
22
35
PWR_DWN#
CPU/2_0:1
VDD_66
23
34
SS_EN#
VSS_C2
VSS_66
24
33
SEL_1
VDD_A
CK66_2
25
32
SEL_0
APIC_0:2
CK66_3
26
31
VDD_48
VSS_A
VDD_66
27
30
CK48
VDD_C
SEL133/100#
28
29
VSS_48
REF_0:1
SEL_0:1
SS_EN#
SEL_133/100#
1
REF_0
FS6261-01
Separate CPU-enable, PCI-enable and power-down
inputs with glitch-free stop clock controls on all clocks
for clock control and power management
VSS_R
(2.5V outputs)
•
•
Description
VSS_R
PLL
÷2
delay
÷6 or
÷8
PWR_DWN#
CPU_0:3
56-pin SSOP
VSS_C
(2.5V outputs)
CPU_STOP#
VDD_66
delay
÷1½
or ÷2
Table 1: CPU/PCI Frequency Selection
CK66_0:3
VSS_66
SEL_133/100#
SEL_1
SEL_0
CPU (MHz)
PCI (MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tristate
(reserved)
100
100
XIN/2
(reserved)
133
133
tristate
(reserved)
33.33
33.33
XIN/6
(reserved)
33.33
33.33
VDD_P
delay
÷3 or
÷4
PCI_F
PCI_1:7
PCI_STOP#
VSS_P
VDD_48
PLL
÷3 or
÷4
CK48
VSS_48
FS6261-01
Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc.
reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
53, 54, 55
DO
APIC_0:2
30
DO
CK48
DESCRIPTION
Three low-skew (<250ps @ 1.25V) 2.5V 16.67MHz clock outputs for APIC bus timing. APIC
clocks are synchronous with CPU clocks but lag the CPU clocks by 1.5 to 4ns.
One 3.3V 48MHz clock output for Universal Serial Bus (USB) timing
CK66_0:3
Four 3.3V 66MHz AGP clock outputs. CK66 clocks are synchronous with CPU clocks but lag the
CPU clocks by 0 to 1.5ns.
DO
CPU_0:3
Four low-skew 2.5V 133/100MHz CPU clock outputs for host frequencies
DO
CPU/2_0:1
36
DIU
CPU_STOP#
CPU_0:3 and CK66_0:3 clock output enable. Asynchronous, active-low disable stops all CPU
and CK66 clocks in the low state.
9, 11, 12, 14,
15, 17, 18
DO
PCI_1:7
Seven 3.3V PCI clock outputs. PCI clocks are synchronous with CPU clocks but lag the CK66
clocks by 1.5 to 4ns.
8
DO
PCI_F
37
DIU
PCI_STOP#
PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI clocks in the low
state.
35
DIU
PWR_DWN#
Asynchronous active-low power-down signal shuts down oscillator, all PLLs, puts all clocks in
low state. Clock re-enable latency of ≤ 3ms.
2, 3
DO
REF_0:1
21, 22, 25, 26
DO
41, 42, 45, 46
49, 50
U
32, 33
DI
28
DI
SEL_133/100#
SEL_0:1
34
DIU
SS_EN#
39
P
VDD
Two low-skew 2.5V clock outputs at half the CPU clock frequencies (66/50MHz)
One free-running 3.3V PCI clock output
Two buffered outputs of the 14.318MHz reference clock
Two frequency select inputs (see Table 4)
Selects 133MHz or 100MHz CPU frequency (pull-up/pull-down must be provided externally)
Spread spectrum enable. Active-low enable turns on the spread spectrum feature; a logic-high
turns off the spread spectrum modulation.
3.3V ± 10%
31
P
VDD_48
Power supply for 3.3V CK48 clock output
23, 27
P
VDD_66
Power supply for 3.3V CK66_0:3 clock outputs
56
P
VDD_A
Power supply for 2.5V APIC_0:2 clock outputs
43, 47
P
VDD_C
Power supply for 2.5V CPU_0:3 clock outputs
51
P
VDD_C2
Power supply for 2.5V CPU/2_0:1 clock outputs
10, 16
P
VDD_P
Power supply for 3.3V PCI_1:7 and PCI_F clock outputs
4
P
VDD_R
Power supply for 3.3V REF_0:1 clock outputs
38
P
VSS
29
P
VSS_48
Ground for CK48 clock outputs
Ground
20, 24
P
VSS_66
Ground for CK66_0:3 clock outputs
52
P
VSS_A
Ground for APIC_0:2 clock outputs
40, 44
P
VSS_C
Ground for CPU_0:3 clock outputs
48
P
VSS_C2
Ground for CPU/2_0:1 clock outputs
7, 13, 19
P
VSS_P
Ground for PCI_1:7 and PCI_F clock outputs
1
P
VSS_R
5
AI
XIN
6
AO
XOUT
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Ground for REF_0:1 clock outputs
14.318MHz crystal oscillator input. XIN can be driven by an external frequency source.
14.318MHz crystal oscillator output
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Table 3: Actual Clock Frequencies
Note: Spread spectrum disabled
CLOCK
APIC_0:2
TARGET (MHz)
ACTUAL (MHz)
DEVIATION (ppm)
16.67 (with CPU = 133.3)
16.6634
-195.92
16.67 (with CPU = 100.0)
16.6661
-36.657
133.33
133.3072
-195.92
100.00
99.9963
-36.657
66.67
66.6536
-195.92
CPU_0:3
CPU/2_0:1
PCI_1:7, PCI_F
CK66_0:3
50.00
49.9982
-36.657
33.33 (with CPU = 133.3)
33.3268
-195.92
33.33 (with CPU = 100.0)
33.3321
-36.657
66.67 (with CPU = 133.3)
66.6536
-195.92
66.67 (with CPU = 100.0)
66.6642
-36.657
48
48.0080
+167
CK48 (1)
(1) 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB requirements.
3.0
Programming Information
Table 4: Function/Clock Enable Configuration
CONTROL INPUTS
CLOCK OUTPUTS (MHz)
CPU/2_
0:1
PCI_F
PCI_1:7
APIC_
0:2
CK48
CK66_
0:3
tristate
tristate
tristate
tristate
tristate
tristate
SEL_
133/100#
SEL_1
SEL_0
PWR_
DWN#
CPU_
STOP#
PCI_
STOP#
0
0
0
1
X
X
0
0
1
1
1
1
0
1
0
1
1
1
14.318
100
50
33.33
33.33
16.67
tristate
66.67
0
1
1
1
1
1
14.318
100
50
33.33
33.33
16.67
48
66.67
1
0
0
1
1
1
XIN
XIN÷2
XIN÷4
XIN÷8
XIN÷8
XIN÷16
XIN÷2
XIN÷4
1
0
1
1
1
1
1
1
0
1
1
1
14.318
133.33
66.67
33.33
33.33
16.67
tristate
66.67
1
1
1
1
1
1
14.318
133.33
66.67
33.33
33.33
16.67
48
66.67
X
X
X
REF_0:1 CPU_0:3
tristate
tristate
(reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved)
(reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved)
0
X
X
low
low
low
low
low
low
low
low
SEL_0:1 and
SEL_133/100# ≠ 0
1
0
0
14.318
low
running
33.33
low
16.67
48
low
1
0
1
14.318
low
running
33.33
33.33
16.67
48
low
or
1
1
0
14.318
running
running
33.33
low
16.67
48
66.67
SEL_0:1 ≠ 01
1
1
1
14.318
running
running
33.33
33.33
16.67
48
66.67
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3.1
Powering down occurs in less than two PCI clocks from
the falling edge of PWR_DWN# to when all clock outputs
are forced low. The REF and CK48 clocks are brought
low as soon as possible.
SEL_1, SEL_0
These two input pins can either tristate the output drivers,
select the Test Mode frequency, or choose the CPU frequencies. Both the SEL_1 and SEL_0 pins have pull-ups
that default the CPU output frequency to either 100MHz
or 133MHz, depending on the state of the SEL_133/100#
pin. These pins should be fixed at a logic state before
power-up occurs.
3.2
4.2
SEL_133/100#
4.2.1 CPU_STOP#
The CPU_STOP# pin is an active-low LVTTL input pin
that disables the CPU_0:3 and CK66_0:3 clocks for low
power operation. CPU_STOP# can be asserted asynchronously, and the stop clock control is glitch-free, in
that the CPU clock must complete a full cycle before the
clock is stopped low. One rising edge of the PCI_F clock
is allowed before the CPU and CK66 clocks are enabled
or disabled.
This pin is an active-low LVTTL input that switches between a 133MHz or a 100MHz system (CPU) clock. A
pull-up or pull-down must be provided externally and this
pin should be fixed at a logic state before power-up occurs.
4.0
Clock Latency
All clock outputs are stopped in the low state, and are
started so that the first high pulse is a full pulse width. All
clocks complete a full period on transitions between running (enabled) and stopped (disabled) to ensure glitchfree stop clock control.
All enabled clocks will continue to run while disabled
clocks are stopped. The clock enable signals are assumed to be asynchronous inputs relative to clock outputs. Enable signals are synchronized to their respective
clocks by this device. The CPU and PCI clocks will transition between running and stopped according to Table 5.
4.1
Clock Enable Latency
Clock enable latency is defined in the number of rising
edges of free-running PCI clocks between when the enable signal becomes active (a rising edge) to when the
first valid clock is driven from the device.
4.2.2 PCI_STOP#
The PCI_STOP# pin is an active-low LVTTL input pin that
disables the PCI_1:7 clocks for low power operation, except for the PCI_F clock. The PCI_F is a free-running
clock, and will continue to run even if all other PCI clocks
have stopped. PCI_STOP# can be asserted asynchronously, and the stop-clock control is glitch-free, in that the
PCI clock must complete a full cycle before the clock is
stopped low. Only one rising edge of the PCI_F clock is
allowed after the PCI_STOP# signal is enabled/disabled.
Power-Up Latency
Table 5: Latency Table
Power-up latency is defined as the time from the moment
when PWR_DWN# goes inactive (a rising edge) to when
the first valid clocks are driven from the device. Upon release of PWR_DWN#, external circuitry should allow a
minimum of 3ms for the PLLs to lock before enabling any
clocks.
SIGNAL
CPU_STOP#
4.1.1 PWR_DWN#
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that puts the device in a low power inactive
state without removing power from the device. All internal
clocks are turned off, and all clock outputs are held low.
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PCI_STOP#
PWR_DWN#
SIGNAL STATE
PCI CLOCK ENABLE
LATENCY
0
disabled
1
1
enabled
1
0
disabled
1
1
enabled
1
0
Power OFF
2 (max.)
1
Power ON
3ms
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Figure 2: CPU_STOP# Timing
CPU_
STOP#
PCI_F
CPU
(133MHz)
CPU
(100MHz)
Figure 3: PCI_STOP# Timing
PCI_
STOP#
PCI_F
PCI_1:7
Figure 4: PWR_DWN# Timing
PWR_
DWN#
PCI_F
PCI_1:7
CPU
(133MHz)
CPU
(100MHz)
VCO
Crystal
Oscillator
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
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5.0
5.2
Spread Spectrum Modulation
The frequency of modulation, noted as fm, describes how
fast the center frequency sweeps between fnom, and (1-δ)
fnom,. Typical modulation frequencies must be greater
than 30kHz (above the audio band) but small enough to
not upset system timing. Since a tracking PLL cannot
instantaneously update the output clock to match a
modulated input clock, any accumulation of the difference
in phase between the modulated input clock and a tracking PLL output clock is called tracking skew. The resulting phase error will decrease the timing margins in any
successive circuitry.
To limit peak EMI emissions, high-speed motherboard
designs now require the reduction of the peak harmonic
energy contained in the system bus frequencies. A reduction in the peak energy of a specific frequency can be
accomplished by spreading the energy over a limited
range of frequencies through a technique known as
spread spectrum clocking. In this technique, a generated
clock frequency is dithered in a tightly controlled sweep
near the clock frequency using a predetermined modulation profile and period.
Figure 5: Spectral Energy Distribution
spreadspectrum
clock
5.3
(1-δ)fnom
fnom
The amount of EMI reduction is directly related to three
parameters: the modulation percentage, the frequency of
the modulation, and the modulation profile.
5.1
Modulation Profile
The modulation profile determines the shape of the
spectral energy distribution by defining the time that the
clock spends at a specific frequency. The longer a clock
remains at a specific frequency, the larger the energy
concentration at that frequency. A sinusoidal modulation
spends a large portion of time between fnom, and (1-δ)
fnom, resulting in large energy peaks at the edges of the
spectral energy distribution. A linear modulation, such as
a triangle profile, improves the spectral distribution but
also exhibits energy peaking at the edges. A non-linear
modulation profile, known as the “Hershey Kiss” profile
offers the best distribution of spectral energy.
∆E
non-spread
clock
Modulation Frequency
Modulation Percentage
Figure 6: Modulation Profiles
The modulation percentage δ, is typically 0.5% of the
center frequency (denoted here as fnom). The modulation
percentage determines the range of frequencies the
spectral energy is distributed over. For a 100MHz clock
frequency, a ±0.5% modulation sweeps the clock frequency between 99.5MHz and 100.5MHz. If the sweep is
symmetrical around the center frequency, the technique
is known as center-spread modulation. However, a circuit
that is designed for a 100MHz reference may not have
enough timing margin to support a clock greater then
100MHz. The clock frequency can instead be modulated
between fnom, and (1-δ) fnom,; the technique is known as
down-spread modulation. For a δ of –0.5%, the clock will
sweep between 99.5MHz and 100MHz. A small degradation in circuit performance may be noticed, as the clock
frequency now averages 99.75MHz.
,62
fnom
fnom
time
(1-δ)fnom
1/fm
time
(1-δ)fnom
1/fm
The type of modulation profile used will also impact
tracking skew. The maximum frequency change occurs at
the profile limits where the modulation changes the slew
rate polarity. To track the sudden reversal in clock frequency, the downstream PLL must have a large loop
bandwidth.
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Compared to the profile limits the modulation slew rate is
relatively slow between the limits, allowing the downstream PLL a chance to reduce the tracking skew. The
ability of the downstream PLL to catch up is determined
by the loop transfer function phase angle.
Figure 7: PLL Tracking Skew
PLL Tracking Skew
100
80
Spread spectrum clocking can be shown to have a negligible effect on cycle-to-cycle jitter performance. Any increase in jitter is less than 1ps when δ<1% and
fm<50kHz. Careful design of downstream PLLs can ensure that tracking skew is minimized. To have less than
100ps of tracking skew, a downstream PLL should have
a loop bandwidth greater than 1MHz, and a phase angle
less than 0.1°.
60
Skew [ps]
40
20
0
20
40
60
80
100
Figure 7 shows the tracking skew of a downstream PLL
with a loop bandwidth of 1.5MHz and a phase angle of
0.26° following a non-linear profile-modulated 100MHz
input clock with a δ=-0.5% and an fm=31.2kHz.
Time [us]
5.4
Spread Spectrum Enable
The active-low LVTTL SS_EN# input pin enables spread
spectrum modulation of the CPU and PCI clocks. When
SS_EN# is a logic-high, the spread spectrum modulation
of these clocks is disabled. If SS_EN# is a logic-low,
spread spectrum modulation is enabled.
A pull-up on this pin disables spread spectrum modulation by default.
Figure 8: Actual Modulation Profile
100
Frequency (MHz)
99.9
99.8
99.7
99.6
99.5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
1/fm (µs)
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6.0
Electrical Specifications
Table 6: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (VSS = ground)
SYMBOL
MIN.
MAX.
UNITS
VDD
VSS-0.5
7
V
Input Voltage, dc
VI
VSS-0.5
VDD+0.5
V
Output Voltage, dc
VO
VSS-0.5
VDD+0.5
V
Input Clamp Current, dc (VI < 0 or VI > VDD)
IIK
-50
50
mA
Output Clamp Current, dc (VI < 0 or VI > VDD)
IOK
-50
50
mA
Storage Temperature Range (non-condensing)
TS
-65
150
°C
Ambient Temperature Range, Under Bias
TA
-55
Junction Temperature
TJ
Lead Temperature (soldering, 10s)
125
°C
125
°C
260
°C
2
kV
Input Static Discharge Voltage Protection (MIL-STD 883E, method 3015.7)
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 7: Operating Conditions
PARAMETER
Supply Voltage
Operating Temperature Range
SYMBOL
VDD
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
Core (VDD) @ 3.3V ± 5%
3.135
3.3
3.465
Clock Buffers (VDD_P, VDD_R,
VDD_66, VDD_48) @ 3.3V ± 5%
3.135
3.3
3.465
Clock Buffers (VDD_A, VDD_C,
VDD_C2) @ 2.5V ± 5%
2.375
2.5
2.625
TA
Crystal Resonator Frequency
fXTAL
Crystal Resonator Load Capacitance
CXL
0
XIN, XOUT pins
APIC_0:2
Load Capacitance
,62
CL
UNITS
V
70
°C
14.316
14.318
14.32
MHz
13.5
18
22.5
pF
10
20
CPU_0:3
10
20
CPU/2_0:3
10
20
PCI_F, PCI_1:7
10
30
CK48
10
20
CK66_0:3
10
30
REF_0:1
10
20
pF
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Table 8: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
Supply Current, Static
IDD
IDDs
fCPU = 133MHz; SEL_0:1 = 11
VDD_A = VDD_C = VDD_C2 = 3.465V
120
fCPU = 133MHz; SEL_0:1 = 11
VDD_A = VDD_C = VDD_C2 = 2.625V
88
fCPU = 100MHz; SEL_0:1 = 11
VDD_A = VDD_C = VDD_C2 = 3.465V
120
fCPU = 100MHz; SEL_0:1 = 11
VDD_A = VDD_C = VDD_C2 = 2.625V
86
PWR_DWN# low
VDD_A = VDD_C = VDD_C2 = 3.465V
12
PWR_DWN# low
VDD_A = VDD_C = VDD_C2 = 2.625V
8
mA
µA
Digital Inputs (CPU_STOP#, PCI_STOP#, PWR_DWN#, SEL_0:1, SS_EN#)
High-Level Input Voltage
VIH
2.0
VDD+0.3
Low-Level Input Voltage
VIL
VSS-0.3
0.8
V
High-Level Input Current
IIH
5
µA
Low-Level Input Current (pull-up)
IIL
VIL = 0.4V
-2
V
µA
-0.8
Digital Inputs (SEL_133/100#)
High-Level Input Voltage
VIH
2.0
VDD+0.3
V
Low-Level Input Voltage
VIL
VSS-0.3
0.8
V
II
-5
+5
µA
Input Leakage Current
Crystal Oscillator Feedback (XIN)
Threshold Bias Voltage
VTH
1.5
V
High-Level Input Current
IIH
VIH = 3.3V
32
µA
Low-Level Input Current
IIL
VIL = 0V
-32
µA
Crystal Loading Capacitance *
CL(xtal)
As seen by an external crystal connected to
XIN and XOUT
Input Loading Capacitance *
CL(XIN)
As seen by an external clock driver on XOUT;
XIN unconnected
13.5
18
22.5
pF
36
pF
Crystal Oscillator Drive (XOUT)
High Level Output Source Current
IOH
VI = 3.3V, VO = 0V
-8.0
mA
Low Level Output Sink Current
IOL
VI = 0V, VO = 3.3V
8.7
mA
,62
1.31.00
9
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Table 8: DC Electrical Specifications, continued
Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
CPU_0:3, CPU/2_0:1, APIC_0:2 Clock Outputs (2.5V Type 1 Clock Buffer)
High Level Output Source Current
IOH min
VDD_C, VDD_C2, VDD_A = 2.375V, VO = 1.0V
IOH max
VDD_C, VDD_C2, VDD_A = 2.625V,
VO = 2.375V
IOL min
VDD_C, VDD_C2, VDD_A = 2.375V,
VO = 1.2V
IOL max
VDD_C, VDD_C2, VDD_A = 2.625V,
VO = 0.3V
Low Level Output Sink Current
Output Impedance
-27
-27
mA
27
mA
30
zOL
Measured at 1.25V, output driving low
13.5
23
45
zOH
Measured at 1.25V, output driving high
13.5
25
45
-10
10
Ω
µA
Tristate Output Current
IOZ
Short Circuit Output Source Current
ISCH
VO = 0V; shorted for 30s, max.
-56
mA
Short Circuit Output Sink Current
ISCL
VO = 2.5V; shorted for 30s, max.
58
mA
REF_0:1, CK48 Clock Outputs (3.3V Type 3 Clock Buffer)
High-Level Output Source Current
Low-Level Output Sink Current
Output Impedance
IOH min
VDD_R, VDD_48 = 3.135V, VO = 1.0V
IOH max
VDD_R, VDD_48 = 3.465V, VO = 3.135V
IOL min
VDD_R, VDD_48 = 3.135V, VO = 1.95V
IOL max
VDD_R, VDD_48 = 3.465V, VO = 0.4V
-29
-23
29
27
zOL
Measured at 1.65V, output driving low
20
45
60
zOH
Measured at 1.65V, output driving high
20
46
60
-10
10
mA
mA
Ω
µA
Tristate Output Current
IOZ
Short Circuit Output Source Current
IOSH
VO = 0V; shorted for 30s, max.
-41
mA
Short Circuit Output Sink Current
IOSL
VO = 3.3V; shorted for 30s, max.
40
mA
PCI_1:7, PCI_F, CK66_0:1 Clock Outputs (3.3V Type 5 Clock Buffer)
High Level Output Source Current
Low Level Output Sink Current
Output Impedance
IOH min
VDD_P, VDD_66 = 3.135V, VO = 1.0V
IOH max
VDD_P, VDD_66 = 3.465V, VO = 3.135V
IOL min
VDD_P, VDD_66 = 3.135V, VO = 1.95V
IOL max
VDD_P, VDD_66 = 3.465V, VO = 0.4V
-33
-33
30
38
zOL
Measured at 1.65V, output driving low
12
29
55
zOH
Measured at 1.65V, output driving high
12
37
55
10
mA
Ω
µA
Tristate Output Current
IOZ
Short Circuit Output Source Current
IOSH
VO = 0V; shorted for 30s, max.
-51
mA
Short Circuit Output Sink Current
IOSL
VO = 3.3V; shorted for 30s, max.
62
mA
,62
-10
mA
1.31.00
10
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Table 9: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
133MHz
CONDITIONS/DESCRIPTION
MIN.
TYP.
100MHz
MAX.
MIN.
TYP.
UNITS
MAX.
Overall
Spread Spectrum Modulation
Frequency *
fm
SS_EN# low
31.5
31.5
kHz
Spread Spectrum Modulation Index*
δm
SS_EN# low
-0.5
-0.5
%
CPU @ 1.25V, CL=20pF to CK66 @
1.5V, CL=30pF (rising edges)
Clock Offset
tpd
0
0.3
1.5
0
0.4
1.5
CK66 @ 1.5V, CL=30pF to PCI @
1.5V, CL=30pF (rising edges)
1.5
2.9
4.0
1.5
3.1
4.0
CPU @ 1.25V, CL=20pF to APIC @
1.25V, CL=20pF (rising edges)
1.5
2.3
4.0
1.5
3.3
4.0
10
1.0
10
1.0
Tristate Enable Delay *
tDZL, tDZH
SEL_0:1 and SEL_133/100#=0
1.0
Tristate Disable Delay *
tDZL, tDZH
SEL_0:1 and SEL_133/100#=0
1.0
Clock Stabilization (on power-up) *
tSTB
via PWR_DWN#
10
3.0
ns
ns
10
ns
3.0
ms
55
%
APIC_0:2 Clock Output (2.5V Type 1 Clock Buffer)
Ratio of high pulse width to one
clock period, measured at 1.5V
Duty Cycle *
dt
Clock Skew *
tskw
APIC to APIC @ 1.25V, CL=20pF
-70
-70
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at 1.25V
relative to an ideal clock, CL=20pF, all
PLLs active
204
122
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
82
88
ps
Rise Time *
Fall Time *
45
50
55
45
50
tr min
Measured @ 0.4V – 2.0V; CL=10pF
1.2
1.2
tr max
Measured @ 0.4V – 2.0V; CL=20pF
1.5
1.5
tf min
Measured @ 2.0V – 0.4V; CL=10pF
1.8
1.5
tf max
Measured @ 2.0V – 0.4V; CL=20pF
2.1
1.8
ns
ns
CPU/2_0:1 Clock Outputs (2.5V Type 1 Clock Buffer)
Ratio of high pulse width to one
clock period, measured at 1.5V
Duty Cycle *
dt
Clock Skew *
tskw
CPU/2 to CPU/2 @ 1.25V, CL=20pF
+10
+10
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at
1.25V relative to an ideal clock,
CL=20pF, all PLLs active
136
122
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
108
112
ps
tr min
Measured @ 0.4V – 2.0V; CL=10pF
0.9
0.8
tr max
Measured @ 0.4V – 2.0V; CL=20pF
1.1
1.1
tf min
Measured @ 2.0V – 0.4V; CL=10pF
1.0
1.0
tf max
Measured @ 2.0V – 0.4V; CL=20pF
1.2
1.2
Rise Time *
Fall Time *
,62
45
52
55
45
52
55
%
ns
ns
1.31.00
11
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
133MHz
CONDITIONS/DESCRIPTION
100MHz
UNITS
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
45
49
55
45
49
55
CPU_0:3 Clock Outputs (2.5V Type 1 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
Clock Skew *
tskw
CPU to CPU @ 1.25V, CL=20pF
+60
+60
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at
1.25V relative to an ideal clock,
CL=20pF, all PLLs active
136
134
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
123
97
ps
Rise Time *
tr min
Measured @ 0.4V – 2.0V; CL=10pF
1.1
0.9
tr max
Measured @ 0.4V – 2.0V; CL=20pF
1.4
1.4
%
ns
tf min
Measured @ 2.0V – 0.4V; CL=10pF
1.0
0.9
tf max
Measured @ 2.0V – 0.4V; CL=20pF
1.1
1.2
Enable Delay *
tDLH
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
Disable Delay *
tDHL
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
Ratio of high pulse width to one
clock period, measured at 1.5V
45
55
45
55
%
Fall Time *
ns
REF_0:1 Clock Outputs (3.3V Type 3 Clock Buffer)
Duty Cycle *
dt
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at 1.5V
relative to an ideal clock, CL=20pF,
all PLLs active
Jitter, Period (peak-peak) *
tj(∆P)
Rise Time *
Fall Time *
50
50
27
23
ps
From rising edge to rising edge at
1.5V, CL=20pF, all PLLs active
177
111
ps
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.9
0.9
tr max
Measured @ 0.4V – 2.4V; CL=20pF
1.4
1.4
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.0
1.0
tf max
Measured @ 2.4V – 0.4V; CL=20pF
1.6
1.6
ns
ns
CK48 Clock Output (3.3V Type 3 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
51
55
45
51
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at 1.5V
relative to an ideal clock, CL=20pF,
all PLLs active
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.5V, CL=20pF, all PLLs active
143
202
Rise Time *
Fall Time *
,62
55
%
244
246
ps
ps
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.8
0.8
tr max
Measured @ 0.4V – 2.4V; CL=20pF
1.3
1.3
tf min
Measured @ 2.4V – 0.4V; CL=10pF
0.9
0.9
tf max
Measured @ 2.4V – 0.4V; CL=20pF
1.4
1.4
ns
ns
1.31.00
12
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
133MHz
CONDITIONS/DESCRIPTION
100MHz
UNITS
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
45
47
55
45
50
55
PCI_1:7, PCI_F Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
dt
Clock Skew *
tskw
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Ratio of high pulse width to one
clock period, measured at 1.5V
%
+660
+660
PCI to PCI @ 1.5V, CL=30pF
+60
+60
tj(LT)
On rising edges 500µs apart at 1.5V
relative to an ideal clock, CL=30pF,
all PLLs active
220
131
ps
tj(∆P)
From rising edge to rising edge at
1.5V, CL=30pF, all PLLs active
76
95
ps
tr min
Measured @ 0.4V – 2.4V; CL=10pF
1.2
1.3
tr max
Measured @ 0.4V – 2.4V; CL=30pF
1.8
1.8
PCI_F to PCI @ 1.5V, CL=30pF
ps
ns
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.3
1.2
tf max
Measured @ 2.4V – 0.4V; CL=30pF
1.6
1.5
Enable Delay *
tDLH
via PCI_STOP#
1.0
8.0
1.0
8.0
ns
Disable Delay *
tDHL
via PCI_STOP#
1.0
8.0
1.0
8.0
ns
55
45
55
%
Fall Time *
ns
CK66_0:3 Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
Clock Skew *
tskw
CK66 to CK66 @ 1.5V, CL=30pF
120
120
ps
Jitter, Long Term (σy(τ)) *
tj(LT)
On rising edges 500µs apart at 1.5V
relative to an ideal clock, CL=30pF,
all PLLs on
137
123
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.5V, CL=30pF, all PLLs active
75
79
ps
Rise Time *
45
52
51
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.9
0.9
tr max
Measured @ 0.4V – 2.4V; CL=30pF
1.5
1.5
ns
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.0
1.0
tf max
Measured @ 2.4V – 0.4V; CL=30pF
1.4
1.4
Enable Delay *
tDLH
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
Disable Delay *
tDHL
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
Fall Time *
ns
Figure 9: Clock Skew Diagrams
CPU
1.25V
2.5V
CPU
tskw
CK66
1.5V
tskw
3.3V
2.5V to 3.3V Clock Offset
,62
CK66
2.5V
1.25V
APIC
1.25V
1.5V
3.3V
tskw
2.5V
2.5V to 2.5V Clock Skew
PCI
1.5V
3.3V
3.3V to 3.3V Clock Skew
1.31.00
13
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Figure 10: DC Measurement Points
3.3V
2.5V
VOH 3.3 = 2.4V
VIH 3.3 = 2.0V
VOH 2.5 = 2.0V
1.5V
VIH 2.5 = 1.7V
1.25V
VIL 3.3 = 0.8V
VOL 3.3 = 0.4V
(device
interface)
VOL
(system
interface)
2.5 =
VIL 2.5 = 0.7V
0.4V
(device
interface)
A. 3.3V Clock Interface
(system
interface)
B. 2.5V Clock Interface
Figure 11: Timing Diagrams
τKP
tr
τKP
tf
tr
tf
2.4V
tKH
tKH
1.5V
tKL
2.0V
1.25V
tKL
0.4V
Duty Cycle
Duty Cycle
A. 3.3V Clock Interface
B. 2.5V Clock Interface
0.4V
Table 10: CPU_0:3, CPU/2_0:1, APIC_0:2 Clock Outputs
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.6
1.8
2.2
2.375
2.5
2.625
,62
High Drive Current (mA)
MIN.
TYP.
MAX.
0
3
6
9
12
15
17
19
21
23
24
25
27
27
28
29
29
29
29
0
7
13
19
24
30
35
39
43
47
50
53
56
58
60
62
63
63
63
63
0
11
21
30
40
48
56
63
70
77
83
88
93
97
100
106
110
111
111
111
111
Voltage
(V)
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.9
2
2.1
2.2
2.3
2.375
2.5
2.625
Low Drive Current (mA)
MIN.
TYP.
MAX.
-28
-28
-28
-28
-27
-26
-24
-21
-17
-15
-12
-9
-6
-3
0
-61
-61
-61
-61
-60
-58
-53
-48
-40
-36
-31
-25
-20
-14
-9
0
-107
-107
-107
-107
-105
-101
-94
-85
-73
-67
-59
-51
-43
-34
-27
-14
0
120
100
80
60
Output Current (mA)
Voltage
(V)
40
20
0
-20
0
0.5
1
1.5
2
2.5
-40
-60
-80
-100
30Ω
-120
Output Voltage (V)
50Ω
90Ω
Data in this table represents nominal characterization data only
1.31.00
14
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
Table 11: REF_0:1, CK48 Clock Outputs
0
0.4
0.65
0.85
1
1.4
1.5
1.65
1.8
1.95
3.135
3.6
High Drive Current (mA)
MIN.
TYP.
MAX.
Voltage
(V)
0
9
14
17
20
25
26
27
28
29
29
0
13
21
26
29
37
39
41
43
45
45
45
0
27
41
52
59
76
79
84
88
92
102
102
0
1
1.4
1.5
1.65
1.8
2
2.4
2.6
3.135
3.3
3.465
Low Drive Current (mA)
MIN.
TYP.
MAX.
-29
-29
-27
-27
-25
-24
-22
-16
-12
0
-46
-46
-44
-43
-41
-39
-36
-28
-22
-6
0
-99
-99
-94
-92
-89
-85
-79
-63
-53
-23
-12
0
120
100
80
60
Output Current (mA)
Voltage
(V)
40
20
0
-20
0
0.5
1
1.5
2
2.5
3
3.5
-40
-60
-80
-100
30Ω
-120
50Ω
Output Voltage (V)
90Ω
Data in this table represents nominal characterization data only
Table 12: PCI_1:7, PCI_F, CK66_0:3 Clock Outputs
0
0.4
0.65
0.85
1
1.4
1.5
1.65
1.8
1.95
3.135
3.6
High Drive Current (mA)
MIN.
TYP.
MAX.
Voltage
(V)
0
9.4
14
17.7
20
26.5
28
29
30
30
31
32
0
18
30
38
43
53
55
56
57
58
59
59
0
38
64
84
100
139
148
163
175
178
187
188
0
1
1.4
1.5
1.65
1.8
2
2.4
2.6
3.135
3.3
3.465
Low Drive Current (mA)
MIN.
TYP.
MAX.
-34
-33
-31
-30
-28
-25.5
-22
-14.5
-11
0
-59
-58
-55
-54
-52
-50
-46
-35
-28
-6
0
-195
-194
-189
-184
-172
-159
-140
-100
-83
-33
-19
0
200
150
100
Output Current (mA)
Voltage
(V)
50
0
0
0.5
1
1.5
2
2.5
3
3.5
-50
-100
-150
30Ω
-200
Output Voltage (V)
50Ω
90Ω
Data in this table represents nominal characterization data only
,62
1.31.00
15
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
7.0
Package Information
Table 13: 56-pin SSOP (0.300") Package Dimensions
DIMENSIONS
INCHES
56
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.095
0.110
2.41
2.79
A1
0.008
0.016
0.203
0.406
A2
0.088
0.092
2.24
2.34
B
0.008
0.0135
0.203
0.343
C
0.005
0.010
0.127
0.254
D
0.720
0.730
18.29
18.54
E
0.292
0.299
7.42
7.59
e
0.025 BSC
E
XT
1
B
ALL RADII:
0.005" TO 0.01"
e
0.64 BSC
H
0.400
0.410
10.16
10.41
L
0.024
0.040
0.610
1.02
Θ
0°
8°
0°
8°
H
A2
D
A1
BASE PLANE
A
7° typ.
C
θ
L
SEATING PLANE
Table 14: 56-pin SSOP (0.300") Package Characteristics
PARAMETER
Thermal Impedance, Junction to Free-Air
Lead Inductance, Self
SYMBOL
ΘJA
L11
L12
Lead Inductance, Mutual
L13
Lead Capacitance, Bulk
C11
C12
Lead Capacitance, Mutual
C13
,62
CONDITIONS/DESCRIPTION
Air flow = 0 m/s
TYP.
UNITS
81
°C/W
Longest trace + wire
6.41
Shortest trace + wire
2.49
Longest trace + wire to first adjacent trace
3.65
Shortest trace + wire to first adjacent trace
1.35
Longest trace + wire to next adjacent trace
2.50
Shortest trace + wire to next adjacent trace
0.90
Longest trace + wire to VSS
0.94
Shortest trace + wire to VSS
0.49
Longest trace + wire to first adjacent trace
0.48
Shortest trace + wire to first adjacent trace
0.20
Longest trace + wire to next adjacent trace
0.04
Shortest trace + wire to next adjacent trace
0.01
nH
nH
pF
pF
1.31.00
16
)6
XT
0RWKHUERDUG&ORFN*HQHUDWRU,&
January 2000
8.0
Ordering Information
Table 15: Device Ordering Codes
DEVICE NUMBER
ORDERING CODE
PACKAGE TYPE
OPERATING
TEMPERATURE RANGE
SHIPPING
CONFIGURATION
11565-801
48-pin (7.5mm/0.300”) SSOP
(Shrink Small Outline Package)
0°C to 70°C (Commercial)
Tape and Reel
11565-811
48-pin (7.5mm/0.300”) SSOP
(Shrink Small Outline Package)
0°C to 70°C (Commercial)
Tubes
FS6261-01
9.0
Revision Information
DATE
PAGE
DESCRIPTION
1/31/00
11-13
Updated characterization data
Copyright © 1999, 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: [email protected]
,62
1.31.00
17