DATABULLETIN MX812 VSR CODEC WITH DRAM CONTROL PRELIMINARY INFORMATION Features and Applications • Half-Duplex Voice Storage and Retrieval • Serial Bus µProcessor Control • Selectable Sample Rates and “Memory Size” • On-Chip DRAM Controller • Up To 2 Minutes of High-Quality Recorded Audio MX812DW 28-pin SOIC • Answering Functions and VoiceNotepad MX812J 28-pin CDIP • Low-Power 5-Volt CMOS CLOCK CLOCK GENERATOR WE CAS AUDIO OUT RAS1 DEMOD A10/R2 VBIAS A9 CVSD CODEC DRAM AUDIO IN MOD CONTROL A8 EXTERNAL A7 DRAM A6 EBIAS A5 VDD POWER METER 1 or 2 x A4 1Mbit A3 DRAM VSS A2 Chips STATUS REGISTER A1 CHIP SELECT SERIAL CLOCK COMMAND DATA REPLY DATA SERIAL C-BUS INTERFACE and LOGIC STORE/PLAY/WAIT COMMAND BUFFER or A0 1x D 4Mbit DRAM Chip DGND IRQ MODE REGISTER Figure 1 - MX812 Voice Store and Retrieve Codec © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 2 MX812 PRELIMINARY INFORMATION DESCRIPTION The MX812 is a half-duplex VSR Codec, which when connected to an audio processing microcircuit (such as the MX816, 826 or 836), provides the storage and recovery of speechband audio in attached Dynamic RAM. The addition of this device will enhance the communications system by providing cellular radios with Answering Functions, “Message-Notepad” and general announcement cababilities. The MX812 will enable: • Storage of a speech message for transmission (replay) at a later time. • Storage of a received speech message when the operator is not attending. • The storage and subsequent replay of speech. All VSR operating functions are controlled by a simple serial µProcessor interface which may operate from the radio’s own µProcessor/Controller. Pin Input audio from the “Store” output of the audio processor is digitized by delta modulation and stored via the DRAM controller, in attached memory. Audio for replay is recovered from the assigned memory locations and after demodulation made available for supply to the “Play” input of the audio processor. For use with other audio systems, the input/ output audio can be connected to relevant points in circuit. The MX812 has no on-chip input or output audio filtering; this capability must therefore be provided by the host system. Sampling rates and memory capacity are selectable to 32kb/s or 63kb/s and 1 x 4Mbit or 2 x 1Mbit respectively, which when used in conjunction allow control of audio-quality and storage-time. This low-power CMOS device is available 28-pin plastic SOIC and 28-pin Cerdip packages. Function 1 CAS: This output should be connected to the “Column Address Strobe” input pin(s) of all DRAM devices installed. 2 WE: This output should be connected to the “Write Enable” input pin(s) of all DRAM devices installed. 3 D: Digital (speech) data into and out of the VSR Codec. This pin should be connected to the “Data In” and “Data Out” pins (“D” and “Q”) of DRAM devices. 4 Xtal: The nominal 4.0MHz clock input to the VSR Codec. The signal applied to this device may be derived from the attached Audio Processor on-chip Xtal Oscillator circuits (see Figures 2 and 3). Note that the VSR Codec will be able to function and maintain correct DRAM refresh, with Xtal input frequencies down to 2.0MHz. Compand and Local Decoder time constants will change accordingly and minimum “C-BUS” timings (Figures 6 and 7) would have to be increased pro-rata. 5 Interrupt Request (IRQ): This Interrupt Request output from the MX812 is ‘wire-OR able’ allowing the Interrupt Outputs of other peripherals to be commoned and connected to the Interrupt input of the µProcessor (see the C-BUS Interface and System Applications document). This input has a lowimpedance pulldown to VSS when active, and a high-impedance when inactive. 6 Serial Clock: The C-BUS serial clock input. This clock produced by the µController, is used for transfer timing of commands and data to and from the VSR Codec. See Timing Diagrams. 7 Command Data: The C-BUS serial (command) data input from the µController. Data is loaded to this device in 8-bit bytes MSB (B7) first and LSB (B0) last, synchronized to the Serial Clock. 8 Chip Select (CS): The C-BUS data transfer control function. This input is provided by the µController. Transfer sequences are initiated, completed or aborted by this signal. See Timing Diagrams. 9 Reply Data: The C-BUS serial data output to the µController. The transmission of reply bytes is synchronized to the Serial Clock under the control of the Chip Select input. This is a 3-state output which is held at a high-impedance when not sending data to the µController. 10 VBIAS: The output of the internal analog circuitry bias line, held internally at VDD/2. This pin should be decoupled to VSS by capacitor C2 (see Figure 2). © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL Pin 3 MX812 PRELIMINARY INFORMATION Function 11 Audio Out: The analog output to the Audio Processor “Play” input when the VSR Codec is configured as a Decoder. When configured as an active Decoder but with no Play Page commands (62H) active, the VSR Codec will play-out an idle pattern of “101010........10s”. When not configured as a Decoder, or Powersaved (Mode Register), this output will be held at VBIAS via an internal 500kΩ resistor. The output at this pin is unfiltered; an external speechband filter – such as that included on the MX816/826/836 Audio Processors – will be required. Since this output is centered around VDD/2 a coupling capacitor is required. 12 EBIAS: The Encoder d.c. internal balancing circuitry line. This pin should be decoupled to VSS by capacitor C4 (see Figure 2). Note that in the ‘Encode’ mode (Mode Register DE and PS both “0”) the Codec drives this pin to approximately VDD/2 through a very high impedance; it can take more than one second for the EBIAS voltage to stabilize when power is first applied to this device. A faster start-up can be achieved by setting Bit DE or PS to “1” for 250mS (approx) during power-up. This will cause the EBIAS pin to be connected to VBIAS through a resistance of approximately 100kΩ. 13 Audio In: The analog input to the VSR Codec in the Encode mode. When not configured as an Encoder, or Powersaved (Mode Register), this input will be held at VBIAS via an internal 500kΩ resistor. This pin should be coupled via a capacitor, see Figure 2. As this input does not contain an internal audio filter, the audio to this pin should be limited to a 3400Hz “speechband” by an external audio filter – such as included in the MX816/826/836 Audio Processors. 14 VSS: The “analog” ground connection. See DGND description. 15 A0: 16 A1: 17 A2: 18 A3: 19 A4: 20 A5: 21 A6: 22 A7: 23 A8: 24 A9: 25 A10/R2: A dual function output pin selected by the memory size (MS) bit (Mode Register), as detailed in the table below: DRAM address line outputs from the MX812. These pins should be connected to the corresponding address inputs of the associated DRAM. MS bit “0” “1” DRAMs 1Mbits' 4Mbit Connected To DRAM No 2 RAS DRAM A10 This Output RAS2 A10 Signal 26 RAS: An output from the VSR Codec which should be connected to the “Row Address Strobe” pin of the 4Mbit DRAM or the first 1Mbit DRAM, see Figure 4, Example DRAM connections. 27 DGND: The digital signal ground connection to the VSR Codec. Both DGND and VSS pins should be connected to the negative side of the d.c. power supply. However, a printed circuit board should be laid out so that DGND is connected as closely as possible to the DRAM section ground pins. 28 VDD: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the VSR Codec are dependent upon this supply. This pin should be decoupled to VSS via capacitor C5, located close to the MX812 pins. © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 4 MX812 PRELIMINARY INFORMATION Application Information VDD D WE C5 CAS CAS WE D XTAL IRQ SERIAL CLOCK COMMAND DATA CS REPLY DATA VBIAS C1 AUDIO OUT EBIAS AUDIO IN C3 1 28 2 27 3 26 4 25 5 24 6 23 7 8 9 10 11 12 MX812J VDD DGND RAS A10/R2 22 21 20 19 18 17 13 16 14 15 D GND RAS A10/R2 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 D R A M VSS C2 C4 Component C1 C2 C3 C4 Value Dependent upon the input impedance of the driven stage 1.0µF 0.1µF 1.0µF non-electrolytic Tolerance: Capacitors = -50/+100% Figure 2 - Recommended External Components + 5.0V V CC VDD XTAL XTAL XTAL/CLOCK STORE Cellular Audio PLAY Processor AUDIO IN AUDIO OUT MX812 eg. MX8n6 E BIAS VSS VBIAS VBIAS VSS Figure 3 - Interfacing to an Audio Processor © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 5 MX812 PRELIMINARY INFORMATION Application Information ...... + 5.0V VDD WE + 5.0V W VCC VDD VCC WE VCC W W CAS CAS CAS CAS CAS RAS1 RAS RAS1 RAS RAS A10/R2 A10 A10/R2 MX812 DGND A9 A9 A9 A9 A9 A8 A8 A8 A8 A8 A7 A7 A7 A7 A6 A6 A6 A6 A5 A5 A5 A5 A4 A4 A4 A4 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 Q A0 A0 Q A0 Q D D D D 4Mbit. DRAM MX812 DGND VSS 1Mbit. DRAM. No.1 A7 A6 A5 A4 D VSS 1Mbit. DRAM. No.2 VSS Figure 4 - Example DRAM Connections Choice of DRAM Devices DRAM devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 Dynamic Random Access memories, with ‘CAS before RAS’ refresh, and a Row Address access time of 200 nano-seconds or less. BANK SELECT INPUTS A B WE CAS RAS1 A10/R2 A9 A8 A7 MX812 A6 A5 A4 'HC00 'HC04 W CAS RAS A10 A9 A8 A7 A6 A5 A4 W CAS RAS A10 A9 A8 A7 A6 A5 A4 4Mbit DRAM No. 1 A3 A2 A1 A0 A3 A2 A1 A0 Q A3 A2 A1 A0 Q D D D 4Mbit DRAM No. 2 Figure 5 - Use of External Elements to Drive Two 4-MBit DRAM Chips Driving Two 4-MBit DRAM Sections By adding external logic circuitry, the MX812 can be configured to drive two 4-MBit DRAM sections. This will have the effect of doubling the available storage time. i.e. 4 minutes at 32kbps. With reference to the circuitry shown in Figure 5: With the Mode Register MS Bit set to “0” the MX812 treats the DRAM sections as two 1-Mbit devices. The external logic makes each 4-MBit DRAM appear as four 1-MBit banks selected by the Bank Select lines ‘A’ and ‘B.’ Bank Select Inputs A B 0 1 0 1 DRAM No 1 Pages 0 – 1023 DRAM No 2 Pages 1024 – 2047 0 0 1 1 © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 6 MX812 PRELIMINARY INFORMATION The Controlling System: C-BUS Hardware Interface C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a µController and MX-COM's New Generation integrated circuits. C-BUS is designed for a low IC pin-count, flexibility in handling variable amounts of data, and simplicity of system design and µController software. It may be used with any µController, and can, if desired, take advantage of the hardware serial I/O functions built into many types of µController. Because of this flexibility and because the BUS data-rate is determined solely by the µController, the system designer can choose a µController appropriate to the overall system processing requirements. Control of the functions and levels within the MX812 VSR Codec is by a group of Address/Commands and appended data instructions from the system µController to set/adjust the functions and elements of the MX812. The use of these instructions is detailed in the following paragraphs and tables. Command Assignment Address/Command (A/C) Byte Hex. Binary MSB General Reset Write to Mode Register Read Status Register Store/Play Page Wait 01 60 61 62 63 0 0 0 0 0 + Data Byte/s LSB 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 + + + 1 byte Instruction to Mode Register 1 byte Reply from Status Register 2 bytes Command Table 1 – C-BUS Address/Commands “Write to Mode Register” Setting – A/C 60H, followed by 1 byte of Command Data. MSB 7 1 0 Interrupt Output – IE Controls the MX812 IRQ output driver. Sampling Rates – SR The CVSD Codec sampling rates. Accurate rates depend upon the applied Xtal/clock frequency (see Table 5). Memory Size – MS The MX812 can operate with 1 x 1Mbit, 2 x 1Mbit or 1 x 4Mbit of DRAM (see Figure 4). Powersave – PS Powersaves the CVSD Codec only. Logic functions and DRAM refresh are maintained. Decode/Encode – DE The Codec and DRAM operational mode.“ “Play” or “Store” Mode Bits 2 0 Transmitted to 812 First Interrupt Output Enable Disable 6 1 0 Sampling Rate 63kb/s 32kb/s 5 1 0 Memory (DRAM) Size Single 4Mbit 1 or 2 x 1Mbit 4 1 0 Powersave CVSD Codec Powersaved CVSD Codec Powered 3 1 0 Decode/Encode Decode – Play Mode Encode – Store Mode 1 0 0 0 Not Used Set to ‘zeros’ Table 2 - Control Register Interrupts The MX812's Interrupt Output is driven by the Status Bit 7 (IF) when the Mode Register Bit7 (IE) is set to a “1.” The IF bit and the Interrupt Output (If enabled) are set when the Store/Play/Wait command Buffer is emptied (MT bit) by transferring from the buffer to the DRAM control circuits. and/or The IF bit and the Interrupt Output (if enabled) are set when a Store, Play or Wait command has finished and the Command Buffer is empty. The notes below illustrate the IRQ pin conditions: IF Bit IE Bit IRQ “0” cleared “0” disable High Z “0” cleared “1” enable High Z “1” Interrupt “0” disable High Z “1” Interrupt “1” enable VSS (logic “0”) “General Reset” – A/C 01H Upon Power-Up the “bits” in the MX812 registers will be random (either “0” or “1”). A General Reset Command (01H) will be required to “reset” all microcircuits on the C-BUS, and has the following effect upon the MX812. Clear all Mode Register bits to “0” Status Register Bit 7 (IF) to “0” Bits 5 and 6 (MT and I) to “1” Halt any current Store, Play or Wait execution Clear the Store/Play/Wait Command Buffer © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 7 MX812 PRELIMINARY INFORMATION The Controlling System ...... “Read Status Register” Reading 4 – A/C 61H, followed by 1 byte of Reply Data. MSB 7 1 0 Received from 812 First Interrupt Condition (Flag) Bit 6 or 5 set to a “1” Cleared condition 6 1 0 Command Buffer Buffer Empty Cleared condition 5 1 0 Device Condition Idle Storing, Playing or Waiting 3 2 1 Interrupt Condition (Flag) – IF Set to a logic “1” whenever Bit 6 or Bit 5 goes from “0” to “1” (unless the transition is caused by a General Reset command 01 H). This indication allows monitoring by ‘poll’ while Interrupts are disabled. Cleared to a logic “0” by a General Reset command or immediately following a read of the Status Register. Command Buffer Status – MT Set to a logic “1” when the Command Buffer is empty or by a General Reset command. Cleared to a logic “0” by loading a new Store, Play, Wait commands. Device Condition – I Set to a logic “1” when NO Store, Play or Wait command is being executed or by a General Reset command. Set to a logic “0” while a Store, Play or Wait command is being executed. Encode Input Power Level – POWER Available in the Encode mode, a 5-bit representation of the analog signal input level, updated at the end of every Store or Wait command. Status Bits Input Power Level 0 Table 3 Status Register Store/Play/Wait Command Buffer A buffer used to accept and hold the latest Store, Play or Wait command received over the C-BUS while the MX812 is executing the previous command. The Status Register, bit 6, indicates the condition of this buffer. When a command is received it is first loaded into this buffer. If the MX812 is already executing a previously loaded Store, Play or Wait command the new command will be stored temporarily in the Command Buffer, from where it will be taken on completion of the previous command. This permits the MX812 to perform a continuous sequence of Store, Play or Wait commands, without gaps and without requiring an unduly fast response from the mController. Note that this Command Buffer can only hold one Store, Play or Wait instruction, each new command received into this buffer will overwrite any previously loaded contents. To Store or Play a sequence of pages the relevant commands should be loaded with sequential page numbers while observing the Status Register – Bit 6. “Store/Play Page” – A/C 62H, followed by 2 bytes of Command Data. operation. For the purposes of storage and replay, the attatched The particular page selected is identified by the 12 lowest DRAM is divided into ‘data-pages’ of 1024 bits (1kbit). bits of the 2 x Store/Play bytes as shown below. One Store/Play command (loaded MSB first) will instruct If a Store command is loaded and executed whilst the the MX812 to store or play (depending upon the setting of the Codec is “Powersaved” in the Encode mode, the selected Mode Register, Bit-3) to or from 1 x 1024 “page” of DRAM. DRAM page will be filled with an idle pattern (“101010.....”). The Store/Play/Wait command buffer will allow continuity of Bit Number Bit MSB – Loaded to MX812 First 15 14 13 12 11 10 Value x x x x Page “0” “0” “0” “0” 2 11 2 10 9 2 8 2 8 7 2 7 6 5 4 6 5 4 2 2 2 2 3 2 2 2 1 2 0 Bit Value ––––––––––––––––––––––– DRAM Page Number ––––––––––––––––––––––– Page DRAM Size 4Mbit 1 + 1Mbit 1Mbit “Wait” 9 Loaded Last – LSB 3 2 1 0 Valid Page Nos 0 – 4095 0 – 2047 0 – 1023 – A/C 63H, –– Wait for 1024 bit periods Causes the MX812 to wait for 1024 bit periods (approximately 16 or 32ms). If the Codec is set to the Encode mode, a new “Power” Bit Nos 0 – 11 0 – 10 0 – 9 reading that is relevant to the input audio level, will be loaded into the Status Register at the end of the Wait period. If the Codec is set to the Decode mode it will ‘Play’ a perfect idle pattern (“101010..........”) during the Wait period. © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 8 MX812 PRELIMINARY INFORMATION Control Timing Information Figure 6 shows the timing parameters for two-way communication between the µController and Cellular peripherals on the “C-BUS.” Figure 7 shows the timing relationships between the Serial Clock and Data. t CSOFF CHIP SELECT t CSE t NXT t CSH t NXT SERIAL CLOCK t CK COMMAND DATA 7 6 5 4 3 2 1 MSB 0 7 6 5 4 3 2 1 7 0 6 5 4 3 2 1 0 LSB FIRST DATA BYTE ADDRESS/COMMAND BYTE LAST DATA BYTE t HIZ REPLY DATA 7 6 5 4 3 2 1 7 0 LSB MSB FIRST REPLY DATA BYTE Logic level is not important 6 5 4 3 2 1 0 LAST REPLY DATA BYTE Figure 6 - Control Timing Information t CK t CL 70% VDD t CH SERIAL CLOCK (from C) 30% VDD t CDH t CDS COMMAND DATA (from C) t RDH t RDS REPLY DATA (to C) Figure 7 - Control Timing Relationships I bit (idle) Device Condition MT bit Command Buffer Status IF bit (Flag) Interrupt (IRQ) Output New 'Store, Play or Wait' Command from C-BUS C1 C2 Read Status Register C3 ** ** ** The value read from the Status Register at these times will include a valid 'Power' reading if the Codec is set to the Encode mode. Command Executing C1 C2 ** C3 Figure 8 - Typical Command Sequences © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 9 MX812 PRELIMINARY INFORMATION Control Timing Information ...... Timing Specification – Figures 6 and 7 Characteristics See Note Min. Typ. Max. Unit – µs t CSE “CS-Enable to Clock-High” 2.0 – t CSH Last “Clock-High to CS-High” 4.0 – – µs tHIZ “CS-High to Reply Output Tri-state” – – 2.0 µs tCSOFF “CS-High” Time between transactions 2.0 – – µs t CK “Clock-Cycle” Time 2.0 – – µs tNXT “Inter-Byte” Time 4.0 – – µs t CH “Serial Clock-High” Period 500 – – ns tCL “Serial Clock-Low” Period 500 – – ns t CDS “Command Data Set-Up” Time 250 – – ns t CDH “Command Data Hold” Time 0 – – ns t RDS “Reply Data Set-Up” Time 250 – – ns t RDH “Repy Data Hold” Time 50.0 – – ns Address Line Decoding MA0 to MA21 are the outputs of the internal 22-bit DRAM address counter, which are time multiplexed as ‘Row’ and ‘Column’ addresses onto the DRAM address lines A0 to A10 etc., as shown below. Memory Size (MS) Bit = “1” – 4Mbit DRAM Pin A0 A1 A2 A3 A4 A5 A6 Row Address MA0 MA2 MA4 MA6 MA8 MA10 MA12 Column Address MA1 MA3 MA5 MA7 MA9 MA11 MA13 A7 A8 A9 A10/R2 MA14 MA16 MA18 MA20 MA15 MA17 MA19 MA21 Memory Size (MS) Bit = “0” – 1Mbit DRAM(s) Pin Row Address Column Address A0 A1 A2 A3 A4 A5 A6 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA20 MA21 RAS1 0 x active 1 x A10/R2 A7 A8 A9 MA14 MA16 MA15 MA17 MA18 MA19 DRAM Selected “first” active “second” x = don't care Table 4 Address Line Decoding Sample Rate (SR) Bit SR = SR = “1” “0” Division Ratio 4.0 64 kbps 128 kbps 62.5 kbps 31.25 kbps Local Decoder Clock Xtal/clock Frequency (MHz) 4.032 125 kHz 63 kbps 31.5 kbps Internal Clock Rate 126 kHz 4.096 64 kbps 32 kbps 128 kHz Table 5 Sampling Clock Rates Available © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 10 MX812 PRELIMINARY INFORMATION Performance SINAD (dB) 35 Sample Rate = 63kb/s 30 25 20 Sample Rate = 32kb/s 15 10 5 0 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0dB. (308mVrms) 3. 6 Input Level (dB) Figure 9 - Typical “SINAD vs Input Level” Plot Performance Figure 9 Shows a typical graph of SINAD vs Input Level produced for both 32kbps and 63kbps sample rates at an input frequency of 1.0kHz. Figure 10 shows a typical graph of the “Power” reading for increasing input signal levels. The “Power” figure (0 to 31) is the binary figure obtained from the 5-bit representation in the Status Register - Bits 0, 1, 2, 3 and 4 while the Codec is selected to the Encode mode. This reading is updated at the end of every Store or Wait command; Excessive input signal levels will record “111112” (3110). 1000 Input Level (mVrms) Log Scale 100 10 Sample Rate 32kbps 'POWER' Reading Sample Rate Lin Scale 63kbps 1 0 10 20 30 Figure 10 - Typical “Power Reading vs Input Level” Plot © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 11 MX812 PRELIMINARY INFORMATION Specifications Absolute Maximum Ratings Operating Limits Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not suggested. All devices were measured under the following conditions unless otherwise noted. Supply Voltage Input Voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25°C Derating Operating Temperature Storage Temperature VDD = 5.0V -0.3 to 7.0 V -0.3 to (VDD+0.3V) ±30mA ±20mA 800mW Max. 10mW/°C -40°C to +85°C -55°C to +125°C Characteristics See Note TAMB = 25°C Xtal/Clock f0 = 4.00MHz Audio Level 0dB ref = 308mVrms @ 1kHz Reply Data Line loaded with 50pF/200kΩ to VSS Min. Typ. Max. Unit 4.5 5.0 5.5 V Static Values Supply Voltage Supply Current Enabled 1 – 3.0 – mA Powersaved 1 – 1.0 – mA Analog Input Impedance – 100 – kΩ Analog Output Impedance (Decode) – 1.0 – kΩ – 500 – kΩ Analog Output Impedance (Encode or Powersave) DRAM Interface Input Logic “1” 2 3.5 – – V Input Logic “0” 2 – – 1.5 V Output Logic “1” (at Io = -120µA) 3 2.7 – – V Output Logic “0” (at Io = 120µA) 3 – – 0.4 V Input Leakage Current (at V IN = 0 to VDD) 4 -1.0 – 1.0 µA Input Capacitance 2 – 10.0 – pF Input Logic “1” 5 3.5 – – V Input Logic “0” 5 – – 1.5 V (logic “1” or “0”) 5 -1.0 – 1.0 µA Output Logic “1” (-120µA) 6 4.6 – – V Output Logic “0” (360µA) 7 – – 0.4 V I (logic “1” or “0”) 6 -4.0 – 4.0 µA 5 – – 7.5 pF 8 – – 4.0 µA Digital Interface IIN Output Logic Levels Out Tri-state Input Capacitance IOX (VOut = 5V) © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL Characteristics 12 MX812 PRELIMINARY INFORMATION See Note Min. 12 4.0 9 -24.0 9, 10 300 9 – Analog Output Signal Levels 13 Output Noise (idle) Typ. Max. Unit 4.1 MHz 4.0 dB 3400 Hz – 2.0 kΩ -7.0 – -5.0 dB 11 – -55.0 – dBp 11 – -50.0 – dBp 11 – 23.0 – dB Dynamic Values “Xtal” Pin Input Frequency Range Store Mode Analog Input Signal Levels Analog Input Signal Frequency Range Recommended Signal Source Impedance – Play Mode Overall ‘Store to Play’ Performance Output Noise (Input Short Circuit) SINAD (SR = 32kb/s) (Input = 1.0kHz @ -6.0dB) Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Not including DRAM current. D input from DRAM Outputs to DRAM. All digital inputs. Serial Clock, Command Data and Chip Select inputs. Reply Data output. Reply Data and Interrupt (IRQ) outputs. Leakage current into the “Off” Interrupt (IRQ) output. For optimum performance. Input filtering must be performed at the source. Measured in conjunction with the FX836 R2000 system Audio Processor. For full C-BUS compatibility. Playback of a stored “-6.0dB 1.0kHz Test Signal.” © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. VSR CODEC with DRAM CONTROL 13 MX812 PRELIMINARY INFORMATION Package Outline Figure 11 shows the MX812J Ceramic Dual In-Line, or Cerdip, Package. The MX812DW is shown in Figure 12. Pin 1 is marked with an indent spot on each chip. Pins number counterclockwise when viewed from the top side. Handling Precautions ä ä The MX812 is a CMOS LSI circuit which includes input protection. However, precautions should be taken to prevent static discharges which may cause damage. A ä ä K ä ä ä ä J ä B ä ä L Package Tolerances Pin 1 ä Dimension in,(mm) A B C D E F G H J K L ä ä C ä ä ä D H ä ä ä E ä ä ä G F Min. Max. 1.44 (36.58) 0.51 (13.06) 0.18 (4.49) 0.12 (3.0) 0.10 (2.54) 0.018 (0.45) 0.055 (1.39) 0.02 (.50) 0.61 (15.50) 0.670 (17.0) 0.009 (0.25) 1.46 (37.05) 0.53 (13.36) 0.220 (5.57) 0.15 (3.81) typical typical typical 0.05 (1.30) 0.62 (15.70) typical typical Figure 11 - MX812J 28-pin Cerdip A C H B D F G E Package Tolerances Pin 1 L M K N J P R Dimension in,(mm) A B C D E F G H J K L M N P R Min. Max. 0.698 (17.72) 0.291 (7.39) 0.092 (2.33) 0.004 (0.102) 0.014 (0.36) 0.050 (1.27) 0.026 (0.66) 0.096 (2.43) 5 0.020 (0.51) 0.025 (0.63) 0.041 (1.04) 0.009 (0.23) 5 0.39 (9.91) 0.706 (17.97) 0.299 (7.59) typical 0.012 (0.304) 0.018 (0.46) typical typical 0.104 (2.64) typical 0.040 (1.02) typical typical 0.011 (0.28) typical 0.414 (10.51) Figure 12 - MX812DW SOIC-28 Package © 1997 MX•COM Inc. www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054 Doc. # 20480076.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.