LIN D O C #: 1840 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER T H E I N F I N I T E P O W E R I O F P N N O VA T I O N R O D U C T I O N D DESCRIPTION The UC184xA family of control ICs provides all the necessary features to implement off-line fixed-frequency, current-mode switching power supplies with a minimum of external components. The current mode architecture demonstrates improved load regulation, pulse-by-pulse current limiting and inherent protection of the power supply output switch. The IC includes: A bandgap reference trimmed to ±1% accuracy, an error amplifier, a current sense comparator with internal clamp to 1V, a high current totem pole output stage for fast switching of power OF UC384 X A VS . SG384 X D ISCHARGE C URRENT A P P L I C AT I O N S SG384x SG384x Min. Limit Max. Limit ■ ECONOMICAL OFF-LINE FLYBACK OR FORWARD CONVERTERS. ■ DC-DC BUCK OR BOOST CONVERTERS. ■ LOW COST DC MOTOR CONTROL. TA=25°C A V A I L A B L E Part # 7.8 −3σ H E E T ■ LOW START-UP CURRENT. (0.5mA max.) ■ TRIMMED OSCILLATOR DISCHARGE CURRENT. (See Product Highlight) p OPTIMIZED FOR OFF-LINE AND DC-TO-DC CONVERTERS. p AUTOMATIC FEED FORWARD COMPENSATION. p PULSE-BY-PULSE CURRENT LIMITING. p ENHANCED LOAD RESPONSE CHARACTERISTICS. p UNDER-VOLTAGE LOCKOUT WITH HYSTERESIS. p DOUBLE PULSE SUPPRESSION. p HIGH-CURRENT TOTEM POLE OUTPUT. p INTERNALLY TRIMMED BANDGAP REFERENCE. p 500KHz OPERATION. p LOW RO ERROR AMPLIFIER. MOSFET's, and an externally programmable oscillator to set frequency and maximum duty cycle. The undervoltage lock-out is designed to operate with 250µA typ. start-up current, allowing an efficient bootstrap supply voltage design. Available options for this family of products, such as start-up voltage hysteresis and duty cycle, are summarized below in the Available Options section. The UC184xA family of control ICs is also available in 14-pin SOIC package which makes the Power Output Stage Collector and Ground pins available. UC384xA 7.5 S K E Y F E AT U R E S PRODUCT HIGHLIGHT COMPARISON A T A 8.3 Mean 8.8 +3σ 9.3 Discharge Current Distribution - mA O P T I O N S Start-Up Hysteresis Max. Duty Voltage Cycle UCx842A 16V 6V <100% UCx843A 8.4V 0.8V <100% UCx844A 16V 6V <50% UCx845A 8.4V 0.8V <50% PA C K A G E O R D E R I N F O R M AT I O N TA (°C) M Plastic DIP 8-pin SOIC DM Plastic 8-pin SOIC D Plastic 14-pin DIP Y Ceramic 8-pin 0 to 70 UC384xAM UC384xADM UC384xAD — -40 to 85 -55 to 125 UC284xAM — UC284xADM — UC284xAD — UC284xAY UC184xAY Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. UC3842ADMT) F O R F U R T H E R I N F O R M AT I O N C A L L ( 7 1 4 ) 8 9 8 - 8 1 2 1 Copyright © 1995 Rev. 1.2 12/95 11861 WESTERN A VENUE , G ARDEN G ROVE , CA. 92841 1 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P R O D U C T I O N A B S O L U T E M A X I M U M R AT I N G S D A T A S H E E T PACKAGE PIN OUTS (Note 1) Supply Voltage (Low Impedance Source) (VCC) ......................................................... 30V Supply Voltage (ICC < 30mA) .......................................................................... Self Limiting Output Current ............................................................................................................. ±1A Output Energy (Capacitive Load) ................................................................................. 5µJ Analog Inputs (VFB & ISENSE) ........................................................................ -0.3V to +6.3V Error Amp Output Sink Current ............................................................................... 10mA Power Dissipation at TA = 25°C (M Package) .............................................................. 1W Storage Temperature Range .................................................................... -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) ............................................................. 300°C Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Pin numbers refer to DIL packages only. COMP VFB ISENSE RT/CT 1 8 2 7 3 6 4 5 VREF VCC OUTPUT GND M & Y PACKAGE (Top View) COMP VFB ISENSE RT/CT 1 8 2 7 3 6 4 5 VREF VCC OUTPUT GND DM PACKAGE (Top View) T H E R MAL DATA M PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 95°C/W DM PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 165°C/W D PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 120°C/W Y PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 130°C/W COMP N.C. VFB N.C. ISENSE N.C. RT/CT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VREF N.C. VCC VC OUTPUT GND PWR GND D PACKAGE (Top View) Junction Temperature Calculation: TJ = TA + (PD x θJA). The θ JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow 2 Copyright © 1995 Rev. 1.2 12/95 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P R O D U C T I O N D A T A S H E E T ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over the operating ambient temperatures for UC384xA with 0°C ≤ TA ≤ 70°C, UC284xA with -40°C ≤ TA ≤ 85°C, UC184xA with -55°C ≤ TA ≤ 125°C; VCC=15V; RT=10K; C T=3.3nF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) Parameter Symbol Test Conditions UC184xA/284xA UC384xA Units Min. Typ. Max. Min. Typ. Max. Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability (Note 2 & 7) Total Output Variation Output Noise Voltage (Note 2) Long Term Stability (Note 2) Output Short Circuit Current VREF VN TJ = 25°C, IL = 1mA 12 ≤ VIN ≤ 25V 1 ≤ IO ≤ 20mA Over Line, Load, and Temperature 10Hz ≤ f ≤ 10kHz, TJ = 25°C TA = 125°C, t = 1000hrs ISC 4.95 5.00 5.05 4.90 5.00 5.10 6 20 6 20 6 25 6 25 0.2 0.4 0.2 0.4 4.9 5.1 4.82 5.18 50 50 5 25 5 25 -30 -100 -180 -30 -100 -180 V mV mV mV/°C V µV mV mA Oscillator Section Initial Accuracy (Note 6) Voltage Stability Temperature Stability (Note 2) Amplitude (Note 2) Discharge Current TJ = 25°C 12 ≤ VCC ≤ 25V TMIN ≤ TA ≤ TMAX 47 52 0.2 5 1.7 8.3 57 1 47 8.8 8.8 7.8 7.6 52 0.2 5 1.7 8.3 57 1 TJ = 25°C, VPIN 4 = 2V VPIN 4 = 2V, TMIN ≤ TA ≤ TMAX 7.8 7.5 VPIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 -0.3 -1 -0.3 -2 65 90 65 90 0.7 1 0.7 1 60 70 60 70 2 6 2 6 -0.5 -0.8 -0.5 -0.8 5 6 5 6 0.7 1.1 0.7 1.1 8.8 8.8 kHz % % V mA mA Error Amp Section Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth (Note 2) Power Supply Rejection Ratio (Note 3) Output Sink Current Output Source Current Output Voltage High Level Output Voltage Low Level IB AVOL UGBW PSRR IOL I OH VOH VOL 2 ≤ V O ≤ 4V Tj = 25°C 12 ≤ VCC ≤ 25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V VPIN 2 = 2.3V, RL = 15K to ground VPIN 2 = 2.7V, RL = 15K to VREF V µA dB MHz dB mA mA V V Current Sense Section Gain (Note 3 & 4) Maximum Input Signal (Note 3) Power Supply Rejection Ratio (Note 3) Input Bias Current Delay to Output (Note 2) AVOL PSRR IB Tpd 3.15 2.85 1.1 0.9 VPIN 3 = 0 to 2V 3 1 70 -2 150 ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA TJ = 25°C, CL = 1nF TJ = 25°C, CL = 1nF VCC = 5V, ISINK = 10mA 0.1 1.5 13.5 13.5 50 50 0.7 0.4 2.2 VPIN 1 = 5V 12 ≤ VCC ≤ 25V 2.85 0.9 -10 300 3 1 70 -2 150 3.15 1.1 0.1 1.5 13.5 13.5 50 50 0.7 0.4 2.2 -10 300 V/V V dB µA ns Output Section Output Low Level Output High Level Rise Time (Note 2) Fall Time (Note 2) UVLO Saturation VOL VOH TR TF VSAT 13 12 13 12 150 150 1.2 150 150 1.2 V V V V ns ns V ( E l e c tr i c a l Cha r a ct er i st i cs cont i nu e next pa g e.) Copyright © 1995 Rev. 1.2 12/95 3 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P R O D U C T I O N D A T A S H E E T ELECTRICAL CHARACTERISTICS Symbol Parameter (Con't.) UC184xA/284xA UC384xA Units Min. Typ. Max. Min. Typ. Max. Test Conditions Under-Voltage Lockout Section Start Threshold Min. Operation Voltage After Turn-On x842A/4A x843A/5A x842A/4A x843A/5A 15 7.8 9 7.0 16 8.4 10 7.6 17 9.0 11 8.2 14.5 7.8 8.5 7.0 16 8.4 10 7.6 17.5 9.0 11.5 8.2 V V V V x842A/3A x844A/5A 94 47 96 48 100 50 0 94 47 96 48 100 50 0 % % % 0.5 17 30 0.3 11 35 0.5 17 30 0.3 11 35 mA mA V PWM Section Maximum Duty Cycle Minimum Duty Cycle Total Standby Section Start-Up Current Operating Supply Current Zener Voltage I CC VZ ICC = 25mA Notes: 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VVFB = 0. 4. Gain defined as: AVOL = ∆ V COMP ; 0 ≤ V ISENSE ≤ 0.8V. ∆ VISENSE 5. Adjust VCC above the start threshold before setting at 15V. 6. Output frequency equals oscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator frequency for the UC1844A and UC1845A. 7. "Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: VREF (max.) - VREF (min.) Temp Stability = T J (max.) - TJ (min.) V REF (max.) & V REF (min.) are the maximum & minimum reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature." BLOCK DIAGRAM VCC * GROUND 34V UVLO ** UVLO 16V (1842A/4A) 8.4V (1843A/5A) Hysteresis 6V (1842A/4A) 0.8V (1843A/5A) VREF 5.0V 50mA 5V Ref S/R Internal Bias 2.5V * VC VREF Good Logic RT/CT Oscillator *** Error Amp VFB COMP CURRENT SENSE T OUTPUT S 2R R R 1V Current Sense Comparator PWM Latch ** POWER GROUND * - V CC and VC are internally connected for 8 pin packages. ** - POWER GROUND and GROUND are internally connected for 8 pin packages. *** - Toggle flip flop used only in x844A and x845A series. 4 Copyright © 1995 Rev. 1.2 12/95 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P R O D U C T I O N D A T A S H E E T CHARACTERISTIC CURVES FIGURE 1. — OSCILLATOR FREQUENCY vs. TIMING RESISTOR Oscillator Frequency - (Hz) VREF 8 CT = 1nF 1M RT RT/CT 4 CT = 2.2nF CT 100k GROUND 5 CT = 4.7nF 10k For RT > 5k, f » 0 300 1.0k 3.0k 10.0k 30.0k 1.72 RT CT Note: Output drive frequency is half the oscillator frequency for the UCx844A/5A devices. 100k RT - (ohms) FIGURE 2. — MAXIMUM DUTY CYCLE vs. TIMING RESISTOR Maximum Duty Cycle - (%) 100.0 80.0 60.0 40.0 20.0 0 300 1.0k 3.0k 10.0k 30.0k 100k RT - (ohms) Copyright © 1995 Rev. 1.2 12/95 5 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P R O D U C T I O N D S A T A H E E T T Y P I C A L A P P L I C AT I O N C I R C U I T S FIGURE 4. — MOSFET PARASITIC OSCILLATIONS FIGURE 3. — CURRENT SENSE SPIKE SUPPRESSION VCC VCC DC BUS 7 7 R1 Q1 UCx84xA DC BUS UCx84xA 6 5 6 IPK RS CHANGE 3 C IPK(MAX) = RS Q1 1.0V RS 5 The RC low pass filter will eliminate the leading edge current spike caused by parasitics of Power MOSFET. A resistor (R1) in series with the MOSFET gate will reduce overshoot & ringing caused by the MOSFET input capacitance and any inductance in series with the gate drive. (Note: It is very important to have a low inductance ground path to insure correct operation of the I.C. This can be done by making the ground paths as short and as wide as possible.) FIGURE 5. — EXTERNAL DUTY CYCLE CLAMP AND MULTI-UNIT SYNCHRONIZATION 8 8 RA 4 7 RB 6 UCx84xA 555 TIMER 3 4 2 5 1 5 0.01 6 f= 1.44 (R A + 2RB)C f= RB RA + 2R B To other UCx84xA devices Precision duty cycle limiting as well as synchronizing several parts is possible with the above circuitry. Copyright © 1995 Rev. 1.2 12/95 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P D R O D U C T I O N A T A S H E E T T Y P I C A L A P P L I C AT I O N C I R C U I T S (continued) FIGURE 6. — SLOPE COMPENSATION VCC UCx84xA DC BUS 7(12) VO 5V 8(14) UVLO S R 5V REF RT INTERNAL BIAS 2.5V 2N222A VREF GOOD LOGIC RSLOPE 7(11) 4(7) OSCILLATOR From VO Q1 CT 2(3) Rd CF 1V ERROR AMP RF 6(10) C.S. COMP 2R Ri R 5(8) PWM LATCH R 3(5) 1(1) 5(9) C RS Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique. FIGURE 7. — OPEN LOOP LABORATORY FIXTURE VREF RT 2N2222 4.7K 100K 1K ERROR AMP ADJUST 4.7K 1 COMP VREF 8 2 VFB VCC 7 5K ISENSE ADJUST 3 ISENSE OUTPUT 6 4 RTCT GROUND 5 CT VCC A UCx84xA 0.1µF 0.1µF 1K OUTPUT GROUND High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Copyright © 1995 Rev. 1.2 12/95 7 PRODUCT DATABOOK 1996/1997 UC184xA/284xA/384xA CURRENT MODE PWM CONTROLLER P D R O D U C T I O N A T A S H E E T T Y P I C A L A P P L I C AT I O N C I R C U I T S (continued) FIGURE 8. — OFF-LINE FLYBACK REGULATOR 4.7kW 1N4004 TI 1W 220µF 250V 1N4004 3600pF 400V 4.7kW 2W 140kW 1/2W AC INPUT 1N4004 MBR735 4700µF 10V 5V 2-5A 1N4935 1N4004 1N4935 16V 150kW 3.6kW VFB 1 COMP 8 VREF 4 RT/CT VCC 10µF 20V 0.01µF 27kW OUT 6 100pF CUR 3 SEN 10kW 0.01µF .0022µF 820pF 1N4935 2 7 GND 5 2.5kW IRF830 UC3844A 20kW 1kW 470pF 0.85kW ISOLATION BOUNDARY SPECIFICATIONS Input line voltage: Input frequency: Switching frequency: Output power: Output voltage: Output current: Line regulation: Load regulation: Efficiency @ 25 Watts, VIN = 90VAC: VIN = 130VAC: Output short-circuit current: 8 90VAC to 130VAC 50 or 60Hz 40KHz ±10% 25W maximum 5V +5% 2 to 5A 0.01%/V 8%/A* * This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side control winding is sensed by the UC3844A error amplifier. Load regulation is therefore dependent on the coupling between secondary and control windings, and on transformer leakage inductance. 70% 65% 2.5Amp average Copyright © 1995 Rev. 1.2 12/95