STMICROELECTRONICS UC3844T

UC3842T UC3843T
UC3844T UC3845T
®
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
.
.
..
.
.
..
.
TRIMMED OSCILLATOR FOR PRECISE FREQUENCY CONTROL
OSCILLATOR FREQUENCY GUARANTEED
AT 250kHz
CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD COMPENSATION
LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH HYSTERESIS
LOW START-UP AND OPERATING CURRENT
Minidip
SO8
comparator which also provides current limit control,
and a totem pole output stage designed to source
or sink high peak current. The output stage, suitable
for driving N-Channel MOSFETs, is low in the offstate.
Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC3842T and UC3844T have
UVLO thresholds of 16V (on) and 10V (off), ideally
suited to off-line applications The corresponding
thresholds for the UC3843T and UC3845T are 8.5 V
and 7.9 V. The UC3842T and UC3843T can operate
to duty cycles approaching 100%. A range of zero to
< 50 % is obtained by the UC3844T and UC3845T by
the addition of an internal toggle flip flop which blanks
the output off every other clock cycle.
DESCRIPTION
The UC384XT family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
BLOCK DIAGRAM (toggle flip flop used only in UC3844T and UC3845T)
Vi
7
UVLO
34V
GROUND
S/R
5
8
5V
REF
INTERNAL
BIAS
2.50V
VREF GOOD
LOGIC
RT/CT
VFB
COMP
CURRENT
SENSE
4
2
1
3
6
OSC
+
-
ERROR AMP.
VREF
5V 50mA
OUTPUT
T
2R
R
S
1V
R
PWM
LATCH
CURRENT
SENSE
COMPARATOR
D95IN331
September 2001
1/15
UC3842T - UC3843T - UC3844T - UC3845T
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vi
Supply Voltage (low impedance source)
Vi
IO
Supply Voltage (Ii < 30mA)
EO
Output Energy (capacitive load)
Value
Unit
30
V
Self Limiting
±1
5
Output Current
Analog Inputs (pins 2, 3)
Error Amplifier Output Sink Current
Ptot
Power Dissipation at Tamb ≤ 25 °C (Minidip)
Ptot
Power Dissipation at Tamb ≤ 25 °C (SO8)
Tstg
Storage Temperature Range
TL
Lead Temperature (soldering 10s)
A
– 0.3 to 5.5
µJ
V
10
1.25
mA
W
800
mW
– 65 to 150
°C
300
°C
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
PIN CONNECTION (top view)
Minidip/SO8
COMP
1
8
VREF
VFB
2
7
Vi
ISENSE
3
6
OUTPUT
RT/CT
4
5
GROUND
D95IN332
PIN FUNCTIONS
No
Function
1
COMP
Description
2
VFB
This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3
ISENSE
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4
RT/CT
The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.
5
GROUND
This pin is the combined control circuitry and power ground.
6
OUTPUT
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
7
VCC
This pin is the positive supply of the control IC.
8
Vref
This is the reference output. It provides charging current for capacitor C T through resistor RT.
This pin is the Error Amplifier output and is made available for loop compensation.
ORDERING NUMBERS
2/15
SO8
Minidip
UC3842TD
UC3843TD
UC3844TD
UC3845TD
UC3842TN
UC3843TN
UC3844TN
UC3845TN
U3842T - UC3843T - UC3844T - UC3845T
THERMAL DATA
Symbol
Rth j-amb
Description
Thermal Resistance Junction-ambient.
Minidip
SO8
Unit
100
150
°C/W
max.
ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for
0 < Tamb < 105°C; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol
Parameter
Test Conditions
Min.
Value
Typ.
Max.
Unit
REFERENCE SECTION
∆VREF
Line Regulation
12V ≤ Vi ≤ 25V
2
20
mV
∆VREF
Load Regulation
1 ≤ Io ≤ 20mA
3
25
mV
∆VREF/∆T Temperature Stability
(Note 2)
Total Output Variation
Line, Load, Temperature
eN
Output Noise Voltage
10Hz ≤ f ≤ 10KHz Tj = 25°C
(note 2)
Long Term Stability
Tamb = 125°C, 1000Hrs (note 2)
ISC
Output Short Circuit
0.2
4.85
mV/°C
5.15
V
µV
50
5
25
mV
-30
-100
-180
mA
49
48
225
52
–
250
55
56
275
KHz
KHz
KHz
OSCILLATOR SECTION
Frequency
Tj = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2k, CT = 1nF)
∆fOSC/∆V
Frequency Change with Volt.
VCC = 12V to 25V
–
0.2
1
%
∆fOSC/∆T
Frequency Change with Temp.
TA = Tlow to Thigh
–
1
–
%
VOSC
Oscillator Voltage Swing
(peak to peak)
–
1.6
–
V
Idischg
Discharge Current (VOSC =2V)
TA = Tlow to Thigh
7.3
–
8.8
mA
2.42
2.50
2.58
V
-0.1
-2
µA
fOSC
ERROR AMP SECTION
V2
Input Voltage
VPIN1 = 2.5V
Ib
Input Bias Current
VFB = 5V
AVOL
2V ≤ Vo ≤ 4V
65
Unity Gain Bandwidth
TJ = 25°C
Power Supply Rejec. Ratio
Io
Io
BW
PSRR
90
dB
0.7
1
MHz
12V ≤ Vi ≤ 25V
60
70
dB
Output Sink Current
VPIN2 = 2.7V VPIN1 = 1.1V
2
12
mA
Output Source Current
VPIN2 = 2.3V VPIN1 = 5V
-0.5
-1
mA
VOUT High
VPIN2 = 2.3V;
RL = 15KΩ to Ground
5
6.2
V
VOUT Low
VPIN2 = 2.7V;
RL = 15KΩ to Pin 8
0.8
1.1
V
3
3.15
V/V
1
1.1
CURRENT SENSE SECTION
GV
V3
SVR
Ib
Gain
(note 3 & 4)
2.85
Maximum Input Signal
VPIN1 = 5V (note 3)
0.9
Supply Voltage Rejection
12 ≤ Vi ≤ 25V (note 3)
Input Bias Current
Delay to Output
70
V
dB
-2
-10
µA
100
300
ns
3/15
UC3842T - UC3843T - UC3844T - UC3845T
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Value
Typ.
Max.
ISINK = 20mA
0.1
0.4
V
ISINK = 200mA
1.6
2.2
V
Test Conditions
Min.
Unit
OUTPUT SECTION
VOL
VOH
VOLS
Output Low Level
Output High Level
ISOURCE = 20mA
13
13.5
V
ISOURCE = 200mA
12
13.5
V
UVLO Saturation
VCC = 6V; ISINK = 1mA
0.1
1.1
V
tr
Rise Time
Tj = 25°C CL = 1nF (2)
50
150
ns
tf
Fall Time
Tj = 25°C CL = 1nF (2)
50
150
ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
Min Operating Voltage
After Turn-on
UC3842T/4T
15
16
17
V
UC3843T/5T
7.8
8.4
9.0
V
UC3842T/4T
9
10
11
V
UC3843T/5T
7.0
7.6
8.2
V
UC3842T/3T
94
96
100
%
UC3844T/5T
47
48
50
%
0
%
PWM SECTION
Maximum Duty Cycle
Minimum Duty Cycle
TOTAL STANDBY CURRENT
Ist
Ii
Viz
Start-up Current
Vi = 6.5V for UC3843T/45T
0.3
0.5
mA
Vi = 14V for UC3842T/44T
0.3
0.5
mA
12
17
mA
Operating Supply Current
VPIN2 = VPIN3 = 0V
Zener Voltage
Ii = 25mA
30
36
V
Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as
close to Tamb as possible.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2 = 0.
4. Gain defined as :
∆ VPIN1
A=
; 0 ≤ VPIN3 ≤ 0.8 V
∆ VPIN3
5. Adjust Vi above the start threshold before setting at 15 V.
4/15
U3842T - UC3843T - UC3844T - UC3845T
Figure 1: Open Loop Test Circuit.
VREF
RT
4.7KΩ
2N2222
100KΩ
COMP
VFB
ERROR AMP.
ADJUST
1KΩ
ISENSE
ISENSE
ADJUST
4.7KΩ
A
VREF
5KΩ
RT/CT
0.1µF
8
1
7
2
3
Vi
Vi
1W
1KΩ
0.1µF
D.U.T.
6
4
5
OUTPUT
OUTPUT
GROUND
CT
GROUND
D95IN343
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5 KΩ potentiometer are used to sample the oscillator
waveform and apply an adjustable ramp to pin 3.
Figure 2: Timing Resistor vs. Oscillator Frequency
Figure 3: Output Dead-Time vs. Oscillator Frequency
RT
(KΩ)
%
D95IN333
D95IN334
C
50
T=
20
0p
F
T=
10
0p
C
T=
50
20
CT=5nF
50
C
F
C
CT=2nF
30
0p
F
CT=5nF
20
T=
1n
F
CT=1nF
10
5
CT=10nF
CT=100pF
3
2
2
Vi=15V
TA=25˚C
1
0.8
10K
CT=200pF
5
CT=2nF
CT=10nF
CT=500pF
10
Vi=15V
TA=25˚C
20K
30K
50K
100K
200K 300K
500K
fOSC(KHz)
1
10K
20K
30K
50K
100K
200K 300K
500K fOSC(KHz)
5/15
UC3842T - UC3843T - UC3844T - UC3845T
Figure 4: Oscillator Discharge Current vs. Temperature.
Idischg
(mA)
Figure 5: Maximum Output Duty Cycle vs. Timing Resistor.
D95IN336
D95IN335
Dmax
(%)
Vi=15V
VOSC=2V
90
8.5
Idischg=7.5mA
80
Idischg=8.8mA
70
8.0
60
Vi=15V
CT=3.3nF
TA=25˚C
7.5
50
40
7.0
-55
-25
0
25
50
75
100 TA(˚C)
Figure 6: Error Amp Open-Loop Gain and
Phase vs. Frequency.
D95IN337
(dB)
Vi=15V
VO=2V to 4V
RL=100K
TA=25˚C
80
Gain
60
0.8
1
2
3
5
RT(KΩ)
Figure 7: Current Sense Input Threshold vs. Error Amp Output Voltage.
φ
Vth
(V)
30
1.0
D95IN338
Vi=15V
TA=25˚C
60
0.8
90
0.6
20
120
0.4
0
150
0.2
180
f(Hz)
0.0
TA=125˚C
40
Phase
-20
10
100
1K
10K
100K
1M
Figure 8: Reference Voltage Change vs.
Source Current.
D95IN339
60
Vi=15V
50
TA=-40˚C
0
2
4
6
Figure 9: Reference Short Circuit Current vs.
Temperature.
D95IN340
ISC
(mA)
Vi=15V
RL≤0.1Ω
100
TA=-40˚C
40
VO(V)
90
TA=125˚C
30
TA=25˚C
80
20
70
10
60
0
50
0
6/15
20
40
60
80
100 Iref(mA)
-55
-25
0
25
50
75
100 TA(˚C)
U3842T - UC3843T - UC3844T - UC3845T
Figure 10: Output Saturation Voltagevs. Load
Current.
Ii
(mA)
D95IN341
Vi
-1
-2
Source Saturation
(Load to Ground)
TA=25˚C
TA=-40˚C
D95IN342
20
Vi=15V
80µs Pulsed Load 120Hz Rate
15
UCX843/45
3
10
TA=-40˚C
2
TA=25˚C
5
1
Sink Saturation
(Load to Vi)
0
0
200
400
RT=10K
CT=3.3nF
VFB=0V
ISense=0V
TA=25˚C
UCX842/44
Vsat
(V)
Figure 11: Supply Current vs. Supply Voltage.
GND
0
600
IO(mA)
Figure 12: Output Waveform.
0
10
20
30
Vi(V)
Figure 13: Output Cross Conduction
Vi =30V
CL = 15pF
TA = 25°C
Vi =15V
CL = 1.0nF
TA = 25°C
90%
VO
20V/DIV
ICC
10%
100mA/DIV
50ns/DIV
100ns/DIV
Figure 14: Oscillator and Output Waveforms.
Vi
CT
7
8
5V REG
OUTPUT
PWM
6
RT
LARGE RT/SMALL CT
OUTPUT
CLOCK
4
OSCILLATOR
CT
ID
OUTPUT
CT
5
SMALL RT/LARGE CT
GND
D95IN344
7/15
UC3842T - UC3843T - UC3844T - UC3845T
Figure 15 : Error Amp Configuration.
2.5V
1mA
+
VFB
2
COMP
1
Zi
-
Zf
D95IN345
Figure 16 : Under Voltage Lockout.
Vi
7
ON/OFF COMMAND
TO REST OF IC
UC3842T
UC3844T
UC3843T
UC3845T
VON
16V
8.4V
VOFF
10V
7.6V
ICC
<17mA
<0.5mA
VOFF VON
D99IN1058
VCC
During UVLO, the Output is low
Figure 17 : Current Sense Circuit .
ERROR
AMPL.
IS
COMP
R
RS
C
1
3
CURRENT
SENSE
5
GND
D95IN347
Peak current (is) is determined by the formula
1.0 V
IS max ≈
RS
A small RC filter may be required to suppress switch transients.
8/15
2R
R
1V
CURRENT
SENSE
COMPARATOR
U3842T - UC3843T - UC3844T - UC3845T
Figure 18 : Slope Compensation Techniques.
VREG
VREG
8
RT/CT
IS
RSLOPE
UC3842T
ISENSE
R1
3
4
UC3842T
CT
RSLOPE
5
RS
RT/CT
IS
4
CT
R1
8
RT
RT
ISENSE
3
5
RS
GND
GND
D99IN1059
Figure 19 : Isolated MOSFET Drive and Current Transformer Sensing.
VCC
Vin
7
ISOLATION
BOUNDARY
+
5.0Vref
-
VGS Waveforms
Q1
6
+
+
0
-
S
R
Q
50% DC
Ipk =
-
+
0
-
V(pin 1) -1.4
3RS
25% DC
NS
( )
NP
+
COMP/LATCH
R
3
C
RS
NS
NP
D95IN349
9/15
UC3842T - UC3843T - UC3844T - UC3845T
Figure 20 : Latched Shutdown.
4
OSC
8
R
BIAS
R
+
1mA
2R
+
-
2
EA
R
1
5
2N
3905
2N
3903
D95IN350
SCR must be selected for a holding current of less than 0.5mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
Figure 21: Error Amplifier Compensation
From VO
+
2.5V
1mA
Ri
-
2
Rd
2R
+
Cf
EA
R
Rf
1
5
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
From VO
+
2.5V
1mA
RP
Ri
2
CP
Rd
2R
+
Cf
Rf
-
EA
R
1
5
D95IN351
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
10/15
U3842T - UC3843T - UC3844T - UC3845T
Figure 22: External Clock Synchronization.
VREF
8
R
BIAS
RT
R
4
EXTERNAL
SYNC INPUT
OSC
+
CT
0.01µF
2R
+
47Ω
-
2
EA
R
1
5
D95IN352
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
8
VREF
RA
R
RB
5K
8
6
+
5
5K
S
-
4
+
Q
+
R
3
R
-
2
BIAS
4
7
2
5K
C
NE555
1
OSC
2R
+
-
EA
R
1
5
f=
1.44
(RA + 2RB)C
Dmax =
RB
TO ADDITIONAL
UC384XT
D99IN1060
RA + 2RB
11/15
UC3842T - UC3843T - UC3844T - UC3845T
Figure 24: Soft-Start Circuit
8
5Vref
R
+
BIAS
-
R
4
OSC
+
S
1mA
2R
+
2
-
1MΩ
Q
+
EA
R
R
-
1V
1
C
5
D95IN354
Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCC
Vin
7
8
+
5Vref
R
-
+
BIAS
7
-
R
4
VClamp
1mA
2
R2
R
5
Q
R
+
EA
Q1
S
2R
+
-
6
OSC
+
1V
1
Comp/Latch
5
C
R1
RS
BC109
VCLAMP = ·
12/15
R1
R1 + R 2
where 0 <VCLAMP <1V
Ipk(max) =
VCLAMP
RS
D95IN355
U3842T - UC3843T - UC3844T - UC3845T
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.010
1.65
0.065
a3
0.65
0.85
0.026
0.033
b
0.35
0.48
0.014
0.019
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.020
c1
45° (typ.)
D (1)
4.8
5.0
0.189
0.197
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
3.81
0.150
F (1)
3.8
4.0
0.15
0.157
L
0.4
1.27
0.016
0.050
M
S
OUTLINE AND
MECHANICAL DATA
0.6
0.024
SO8
8 ° (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
13/15
UC3842T - UC3843T - UC3844T - UC3845T
mm
DIM.
MIN.
A
TYP.
inch
MAX.
MIN.
3.32
TYP.
MAX.
0.131
a1
0.51
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
0.020
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
Z
14/15
3.18
OUTLINE AND
MECHANICAL DATA
3.81
1.52
0.125
0.150
0.060
Minidip
U3842T - UC3843T - UC3844T - UC3845T
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
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© 2001 STMicroelectronics – Printed in Italy – All Rights Reserved
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