Preliminary Information
T73LVP22
Dual 3.3V LVTTL/LVCMOS-to-Differential
LVPECL Translator
Applications
•
Multiple LVPECL clock sources
General Description
The TLSI T73LVP22 is a general-purpose dual LVTTL (LVCMOS)-to-differential LVPECL translator
operating from a single +3.3V supply. The device has two independent channels that accept an LVTTL or
LVCMOS input and provide differential LVPECL outputs referenced to the positive supply rail. The small 8pin SOIC package makes it ideal for applications which require the translation of multiple clocks or data
signals, and where cost, performance and size are of critical importance. The T73LVP22 is 100K PECL
compatible and is a pin-for-pin replacement for the MC100EPT22D.
Features
•
350pS typical propagation delay
•
Operating Frequency > 1 GHz
•
Differential LVPECL outputs
•
Flow-through pinout
•
Q, Q1 outputs default low with input
(D) open
•
ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
•
-40 oC to +85 oC operating temperature
range
•
Available in standard 8-pin SOIC
package
Figure 1. Functional Block Diagrams & Pin Assignments (Top View)
8-pin SOIC
Q
1
LVPECL
Qn
2
Q1
3
LVPECL
Q1n
4
{
LVTTL/
LVCMOS
{
LVTTL/
LVCMOS
8
VDD
7
D
6
D1
5
GND
See page 4 for package outline drawing
and
ordering information.
T73LVP22PI
Page 1
Rev A February 23, 2004
TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 • (631) 755-7005 • Fax 631-755-7626 • www.tlsi.com
T73LVP22
Preliminary Information
Table 1. Pin Description
Name
Description
Type
Pin #
Q, Q1
LVPECL data outputs
O
1, 3
Qn, Q1n
LVPECL complementary data outputs
O
2, 4
VDD
Connect to +3.3V
P
8
D, D1
LVCMOS/LVTTL data inputs
I
7, 6
GND
Connect to ground
P
5
Legend:
I = Input
O = Output
P = Power supply connection
Table 2. Absolute Maximum Ratings (each channel)
Symbol
Parameter
Conditions
VDD
Supply voltage
Referenced to GND
VIN
Input voltage
Referenced to GND
IOUT
Output current
Continuous
TSTG
Storage temperature
Min
Typ
-0.5
-65
Max
Units
+5.0
V
VDD
V
50
mA
o
+150
C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Table 3. Operating Conditions (each channel)
Symbol
VDD
Parameter
Conditions
Power Supply Voltage
Min
Typ
Max
+3.0
+3.3
+3.6
TA
Ambient Temperature
-40
VIH
Input HIGH Voltage
+2.0
VIL
Input LOW Voltage
T73LVP22PI
Units
+85
C
V
+0.8
Page 2
V
o
V
Rev A February 23, 2004
TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 • (631) 755-7005 • Fax 631-755-7626 • www.tlsi.com
T73LVP22
Preliminary Information
Table 4. DC Characteristics (each channel)
TA = -40oC to +85oC, VDD = +3.0V to +3.6V unless otherwise stated below.
Parameter
Conditions
Max
Units
IIH
Symbol
Input HIGH Current
VIN =+2.7V
100
µA
IIL
Input LOW Current
VIN = +0.5V
1
µA
VIK
Input Clamp Diode Voltage
IIN = -18mA
-1.2
V
VOH
Output HIGH Voltage
(1, 2)
o
-40 C
Min
VDD = +3.3V
2220
2320
2420
mV
+25 C
2220
2320
2420
mV
+85oC
2220
2320
2420
mV
1420
1520
1620
mV
+25 C
1420
1520
1620
mV
+85oC
1420
1520
1620
mV
o
VOL
Output LOW Voltage
(1, 2)
o
-40 C
VDD = +3.3V
o
IDD
Notes:
Power Supply Current
Typ
Total both channels, no load
46
mA
1. The T73LVP22 is designed to meet these specifications after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board.
2. Q, Q1 and Qn, Q1n outputs are loaded with 50 ohms to VDD-2 volts.
Table 5. AC Characteristics (each channel)
TA = -40oC to +85oC, VDD = +3.0V to +3.6V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
To Output Differential
350
500
ps
To Output Differential
350
500
ps
130
200
ps
Propagation Delay
(1)
tPHL
Propagation Delay
(1)
tr/tf
Output Rise/Fall time
20%-80%, Q/Qn
fMAX
Maximum Input Frequency
LVTTL or LVCMOS
input
>1
GHz
fMAX
Maximum Input Frequency (2)
750mV peak-to-peak
sine wave centered
around 1.5V
>1
GHz
tPLH
Notes:
80
1. Q, Q1 and Qn, Q1n outputs are loaded with 50 ohms to VDD-2 volts.
2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source.
T73LVP22PI
Page 3
Rev A February 23, 2004
TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 • (631) 755-7005 • Fax 631-755-7626 • www.tlsi.com
T73LVP22
Preliminary Information
Figure 2. Package Outline (8-pin SOIC)
Table 6. Ordering Information
Part Number
T73LVP22-S08
T73LVP22-S08-TNR
T73LVP22PI
Marking
T73LVP22
T73LVP22
Shipping/Packaging
Tubes
Tape & Reel
Page 4
No. of
Pins
8
8
Package
SOIC
SOIC
Temperature
-40°C to +85°C
-40°C to +85°C
Rev A February 23, 2004
TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 • (631) 755-7005 • Fax 631-755-7626 • www.tlsi.com