ETC EMC12

1180 McDermott Dr
t
West Chester, PA 19380-4022
Communication
Automation
Corporation
Tel: (610) 692-9526 tToll-free: (800) 367-6735 t Fax: (610) 436-8258 t http://www.cacdsp.com t Email: [email protected]
EMC12
Audio Interface
for the
EmPack System
Mezzanine Board
Technical Reference
Version 1.4
email: [email protected]
EMC12 Hardware Reference Manual
 2001- 2006 Communication Automation Corporation
West Chester, PA (USA)
License Agreement
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illegal to duplicate the design and implementation of the Hardware and/or to make copies of the Software except as
provided in this license agreement. It is illegal to give copies of CAC Software to another person, or to duplicate the
Software by any other means, including electronic transmission, except as provided in this license agreement. CAC
Software and Hardware contains trade secrets and, to protect them, you may not decompose, reverse engineer,
disassemble, or otherwise reduce the applicable object code or binary portions of the Software or Hardware to human
perceivable form.
Our software is a product of Communication Automation Corporation (CAC) and is licensed for unrestricted use WITH
CAC HARDWARE PRODUCTS ONLY. CAC software may be reproduced and used by the customer only if this legend
is included o n all distribution media and this legend is included as a part of the software comments, whether the CAC
software is used in whole or in part.
Users may copy or modify CAC software without royalty, but are not authorized to license, sub-license, or distribute this
copied or modified CAC software to any other person or organization except as part of a hardware product or software
developed by the user that incorporates CAC hardware products. You are permitted, however, to freely distribute your
own derived software that communicates to the CAC boards through these software drivers and libraries, free of any
royalty to CAC.
Warranty
Communication Automation Corporation reserves the right to make changes to these products, including any software
and/or hardware described herein, without notice. No warranty of merchantability or fitness for a particular purpose is
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arising out of, the use of this Software. CAC does not recommend the use of any of its products, Software or
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Use of a term in this manual should not be regarded as affecting the validity of any trademark or service mark.
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Table of Contents
1.
EMC12 AUDIO INTERFACE FOR THE EMPACK SYSTEM................................1-1
1.1
EmPack EMC12 Overview...........................................................................................................................................1-1
1.1.1
EMC12 Introduction..............................................................................................................................................1-1
1.1.2
EMC12 Top Level Description.............................................................................................................................1-2
1.2
EMC12 Hardware Specification .................................................................................................................................1-4
1.2.1
EmPack Mezzanine Interface................................................................................................................................1-4
1.2.2
Parallel I/O...............................................................................................................................................................1-5
1.2.3
Reset and Configuration.....................................................................................................................................1-11
1.3
EMC12 TDM................................................................................................................................................................1-12
1.3.1
TDM Connections...............................................................................................................................................1-12
1.3.2
Continuation Slots ...............................................................................................................................................1-15
1.3.3
TDM Validity and Conditional Transfers.........................................................................................................1-16
1.3.4
Programmable TDM Validity..............................................................................................................................1-16
1.3.5
TDM FIFO.............................................................................................................................................................1-17
1.3.6
TDM Last Control Word ....................................................................................................................................1-18
1.3.7
TDM Reset............................................................................................................................................................1-18
1.3.8
API Functions for TDM Control.......................................................................................................................1-19
1.4
EMC12 DSP.................................................................................................................................................................1-26
1.4.1
DSP Reset..............................................................................................................................................................1-26
1.4.2
DSP Interrupts ......................................................................................................................................................1-26
1.4.3
DSP Clock..............................................................................................................................................................1-26
1.4.4
DSP Memory.........................................................................................................................................................1-28
1.4.5
Sync Input.............................................................................................................................................................1-28
1.5
EMC12 CODECS ........................................................................................................................................................1-29
1.5.1
Analog I/O............................................................................................................................................................1-29
1.5.2
Data Conversion Mode and Sampling Rate.....................................................................................................1-33
1.5.3
I/O Jumper Settings .............................................................................................................................................1-36
1.5.4
EmPack Audio Signals ........................................................................................................................................1-38
1.6
Display LEDs................................................................................................................................................................1-43
1.7
Temperature Sensor...................................................................................................................................................1-43
1.8
Mechanical Characteristics......................................................................................................................................1-43
1.9
Power Consumption....................................................................................................................................................1-43
1.10
Software ........................................................................................................................................................................1-44
1.11
Reference Documents ................................................................................................................................................1-44
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TABLES
Table 1-1: EmPack Mezzanine Connector Pinout....................................................................................................................1-4
Table 1-2: PIO Resource Map ....................................................................................................................................................1-6
Table 1-3: Register Map For DSP Resources...........................................................................................................................1-6
Table 1-4: Register Map For TDM Resource...........................................................................................................................1-6
Table 1-5: Register Map For SYSTEM Resource....................................................................................................................1-7
Table 1-6: Board Control Register 0 (BCR0).............................................................................................................................1-7
Table 1-7: Board Control Register 1 (BCR1).............................................................................................................................1-7
Table 1-8: PIO Interrupt Status Register (PISR) ......................................................................................................................1-8
Table 1-9: PIO Interrupt Mask Register (PIMR)......................................................................................................................1-8
Table 1-10: DSP Interrupt Control Register (DICR) ................................................................................................................1-8
Table 1-11: CODEC Control Status Register (CCSR)..............................................................................................................1-8
Table 1-12: LTDM[0-11] Signal Allocation ............................................................................................................................1-12
Table 1-13: TDM Source Control Word Definition (Words 0-2) ........................................................................................1-13
Table 1-14: TDM Destination Control Words Definition (Words 3-6)..............................................................................1-13
Table 1-15: TDM Destination Control Word Definition (Word 7) .....................................................................................1-13
Table 1-16: Bus Source Encoding............................................................................................................................................1-14
Table 1-17: CODEC Destination Encoding.............................................................................................................................1-14
Table 1-18: DSP Destination Encoding...................................................................................................................................1-15
Table 1-19: AV9110 Serial Data Format...................................................................................................................................1-27
Table 1-20: Common AV9110 Data Stream.............................................................................................................................1-27
Table 1-21: DSP Memory Configurations...............................................................................................................................1-28
Table 1-22: CODEC / TDM Transfer Mapping......................................................................................................................1-34
Table 1-23: x2 Jumper Block......................................................................................................................................................1-36
Table 1-24: 2x2 Jumper Block....................................................................................................................................................1-36
Table 1-25: CODEC Jumper Block Examples ..........................................................................................................................1-37
Table 1-26: AMP and T&B OUT Signals ...............................................................................................................................1-40
Table 1-27: AMP and T&B IN Signals ....................................................................................................................................1-41
FIGURES
Figure 1-1: EMC12 Mezzanine Board with DSP.......................................................................................................................1-1
Figure 1-2: EMC12 Block Diagram.............................................................................................................................................1-3
Figure 1-3: TDM Timing............................................................................................................................................................1-16
Figure 1-4: CODEC Channel Gain Stages ...............................................................................................................................1-30
Figure 1-5: CODEC Channel Jumper PCB Section.................................................................................................................1-36
Figure 1-6: Thomas & Betts connector...................................................................................................................................1-38
Figure 1-7: AMP connector......................................................................................................................................................1-39
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1.
EMC12 Audio Interface for the EmPack System
1.1
EmPack EMC12 Overview
1.1.1
EMC12 Introduction
This document specifies the characteristics of the EMC12, an EmPack mezzanine board with six
CS4231A CODECs with a total of 12 audio channels, an optional Agere DSP32C processor, its memory,
and the software libraries and drivers to support this board. Some of the detailed specifications in this
manual reflect logic available in version 1.2 of the EMC12 FPGA configuration. This FPGA configuration
is included in version 3.4.7 of the EmPack FPGA flash file (fpga347.bin).
Figure 1-1: EMC12 Mezzanine Board with DSP
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1.1.2
EMC12 Top Level Description
The EMC12 is a mezzanine board for the EmPack system. It contains the following major functional
blocks:
An EmPack mezzanine bus interface
Six CS4231A CODECs with a total of 12 audio channels
An optional Agere DSP32C processor operating at 74 MHz
512k bytes or 2 Mbytes of zero wait-state (0ws) static RAM for the DSP
6 TDM buses connecting serial ports of the DSPs and other resources in the EmPack system
2 FIFOs storing TDM control information
2 LEDs under DSP program control
A global programmable frequency generator
An EEPROM containing board specific information
A temperature sensor
Software drivers for Solaris, Windows NT and Win2K are provided, together with a software interface
library to allow access to and control of the EMC12 from user-developed programs.
Diagnostics are provided which are sufficient to verify correct operation of all functional blocks on the
EMC12.
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Figure 1-2: EMC12 Block Diagram
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1.2
EMC12 Hardware Specification
The electrical hardware portions of the characteristics in Section 3 are elaborated in the following
subsections.
1.2.1
EmPack Mezzanine Interface
The EmPack mezzanine connector provides the basic communication path between the base board and
mezzanine boards. Signals used by the EMC12 are grouped by function and discussed in subsequent
sections.
Table 1-1: EmPack Mezzanine Connector Pinout
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
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Pin Name
+12V
+12V
N/C
TDI
TCK
GND
MODID0 (bottom)
MODID1 (top)
MODID3 (bottom)
~MODID0 (top)
GND
PIO_D0
PIO_D2
GND
PIO_D4
PIO_D6
GND
PIO_D8
PIO_D10
GND
PIO_D12
PIO_D14
GND
PIO_A0(HBS-)
PIO_A2
GND
PIO_A4
PIO_A6
GND
PIO_A8
PIO_A10
GND
I/O
I
I
I
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
Pin
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Pin Name
+12V
+12V
N/C
TDO
EECS
GND
MODID1 (bottom)
MODID2 (top)
MODID2 (bottom)
MODID1 (top)
VCC
PIO_D1
PIO_D3
GND
PIO_D5
PIO_D7
VCC
PIO_D9
PIO_D11
GND
PIO_D13
PIO_D15
VCC
PIO_A1
PIO_A3
GND
PIO_A5
PIO_A7
VCC
PIO_A9
PIO_A11
GND
Communication Automation Corporation
I/O
O
I
I
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
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EMC12 Hardware Reference Manual
Table 1-1 - EmPack Mezzanine Connector Pinout (continued)
Pin
Number
61
63
65
67
69
71
73
75
77
79
81
Pin Name
I/O
PIO_A12
PIO_A14
GND
PIO_A16
PIO_A18
GND
PIO_A20
PIO_LBSGND
PIO_IRQ0PIO_WAIT-
I
I
83
85
87
89
91
93
95
97
99
101
103
105
107
109
GND
LTDM0
LTDM2
GND
LTDM4
LTDM6
GND
LTDM8
LTDM10
GND
LFSYNCPROGRAMGND
VCC (bottom)
LASTMOD (top)
PIO_RDGND
PIO_WRGND
MEZZLCLK
111
113
115
117
119
1.2.2
I
I
I
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I
I
I
Pin
Number
62
64
66
68
70
72
74
76
78
80
82
Pin Name
I/O
I
I
84
86
88
90
92
94
96
98
100
102
104
106
108
110
PIO_A13
PIO_A15
VCC
PIO_A17
PIO_A19
GND
PIO_A21
PIO_CSVCC
PIO_IRQ1PIO_ACK(bottom)
PIO_ACK (top)
GND
LTDM1
LTDM3
VCC
LTDM5
LTDM7
GND
LTDM9
LTDM11
VCC
LMSYNC
RESETGND
REFCLK
112
114
116
118
120
GND
LCLK
GND
PRCLK
GND
I
I
I
I
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
Parallel I/O
The primary means of communication between the base board and the mezzanine is through the parallel
I/O interface. This group of signals consists of PIO_D[0-15], PIO_A[0-21], PIO_CS-, MODID[0-3],
PIO_WAIT-, PIO_RD-, PIO_WR-, PRCLK, PIO_IRQ0-.
1.2.2.1 MODID
Each mezzanine in an EmPack system has a unique Module ID (MODID) at any given time. The
MODID signals on the bottom connector of the first mezzanine (closest to the base board) are controlled
directly by the base board. The MODIDs of two adjacent mezzanines have the following relationship:
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If, for a particular mezzanine, MODIDn = Jn,
then, for the mezzanine above it, MODIDn+1 = Jn+1,
where Jn is a number in a sequence generated by the 4-bit Johnson counter. The sequence used is {0x7,
0x3, 0x1, 0x0, 0x8, 0xC, 0xE, 0xF}. Notice the sequence is circular. If, for example, the first mezzanine
sees a MODID of 0xE, then the second and third mezzanine will see 0xF, and 0x7 respectively. For
normal PIO, the base board always drives 0x7 on the MODID bits.
1.2.2.2 PIO Address Map
A mezzanine is selected in a PIO read/write operation if PIO_CS- is low, and the MODID matches the
address bits PIO_A[18-21]. Address bits PIO_A[14-17] select the resource on the mezzanine, and
PIO_A[1-5] select the register to be read or written. All PIO are 16-bit wide and PIO_A[0] is not
decoded.. Table 1-2 below shows the mezzanine PIO resource map.
See the CS4231A datasheet for register mapping of the CODEC and BROADCAST resources. Note:
Access to the BROADCAST resource is read only.
Table 1-2: PIO Resource Map
PIO_A[14-17]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa- 0xF
Resource
CODEC 0
CODEC 1
CODEC 2
CODEC 3
CODEC 4
CODEC 5
BROADCAST
FIFO (TDM)
SYSTEM
DSP
Reserved
Table 1-3: Register Map For DSP Resources
PIO_A[1-5]
0x00 - 0x0D
0x0E - 0x11
0x12
0x13 - 0x1D
0x1E
0x1F
Access
Read/Write
Read/Write
Read/Write
Register
See AT&T DSP32C Information Manual
Reserved
PDF-conditional PDR access (PDRW)
Reserved
PDF-conditional PDR2 access (PDR2W)
Reserved
Location
DSP
FPGA
FPGA
Table 1-4: Register Map For TDM Resource
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PIO_A[1-5]
0x00
0x01 - 0x1F
Access
Read/Write
Register
TDM Control Data Register (TCDR)
Reserved
Location
FIFO
Table 1-5: Register Map For SYSTEM Resource
PIO_A[1-5]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e - 0x1F
Access
Read/Write
Read/Write
Read
Read/Write
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Register
Board Control Register 0 (BCR0)
Board Control Register 1 (BCR1)
PIO Interrupt Status (PISR)
PIO Interrupt Mask (PIMR)
DSP Interrupt Control (DICR)
Last TDM Control Word (LTCW)
CODEC test points select (bits 0 – 2)
Test point diagnostic signal (bit 0)
CODEC 0 Control Status (CCS0)
CODEC 1 Control Status (CCS1)
CODEC 2 Control Status (CCS2)
CODEC 3 Control Status (CCS3)
CODEC 4 Control Status (CCS4)
CODEC 5 Control Status (CCS5)
Reserved
Device
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
Table 1-6: Board Control Register 0 (BCR0)
Bit(s)
0
1
Name
DSP_RESET
DSP_MMODE
Access
Read/Write
Read/Write
2
3
4
5 - 10
11 - 14
15
TDM_RESET
Reserved
ACTIVE_FIFO
CODEC_RESET
Reserved
DIGI_LOOP
Read/Write
Function
Control RESTN (active low) pin of each DSP
DSP memory mode:
0 = mode 6
1 = mode 7
TDM reset
Read Only
Read/Write
Currently active FIFO
Assert Power-Down to Codecs 0 - 5
Read/Write
Experimental Digital Loop-back mode
Table 1-7: Board Control Register 1 (BCR1)
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Bit(s)
0
Name
AV9110_EN
Access
Read/Write
1
DS1620_EN
Read/Write
2
FIFO_RESET
Write Only
Function
AV9110 Chip Select:
0 = chip deselected
1 = chip selected
0 = chip deselected
1 = chip selected
Reset inactive FIFO
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3
4
5
6
7 - 15
FIFO_RT
SWITCH_FIFO
CLR_FINT
CLR_TINT
Reserved
Write Only
Write Only
Write Only
Write Only
Retransmit inactive FIFO
Switch active FIFO
Clear FIFO Switch Interrupt
Clear PIO Timeout Interrupt
Table 1-8: PIO Interrupt Status Register (PISR)
Bit(s)
0
6
7
8 - 15
Name
DSP
FIFO
TIMEOUT
Reserved
Access
Read Only
Read Only
Read Only
Function
DSP PIF signal
FIFO switched
PIO Timeout
Table 1-9: PIO Interrupt Mask Register (PIMR)
Bit(s)
0
Name
DSP
Access
Read/Write
6
FIFO
Read/Write
7
TIMEOUT
Read/Write
8 - 15
Reserved
Function
0 = disable interrupt
1 = enable interrupt
0 = disable interrupt
1 = enable interrupt
0 = disable interrupt
1 = enable interrupt
Table 1-10: DSP Interrupt Control Register (DICR)
Bit(s)
0-2
Name
INT_CTRL
3 - 15
Reserved
Access
Write Only
Function
0 = Reserved
1 = set External INTREQ1
2 = set External INTREQ2
3 = clear INTREQ1 and INTREQ2, disable LMSYNC interrupt
4 = enable setting INTREQ1 by the rising edge of LMSYNC
5 = disable LMSYNC interrupt
6= enable setting INTREQ1 by both edges of LMSYNC
7 = Reserved
Table 1-11: CODEC Control Status Register (CCSR)
Bit(s)
0
1
2
3
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Name
ADC16
DAC16
SR16
SR32
Access
Read/Write
Read/Write
Read/Write
Read/Write
Function
ADC 16-bit conversion
DAC 16-bit conversion
16kHz sample rate
32kHz sample rate
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4
5
6
7 - 15
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SR48
LOCK
LOSTLOCK
Reserved
Read/Write
Read Only
Read Only
48kHz sample rate
CODEC sync locked
CODEC sync lost lock
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1.2.2.3 PIO Read/Write
The PIO_RD-, PIO_WR- and address decoding are used by the FPGA to generate appropriate read,
write and enable signals to the DSPs, the FIFOs and internal registers. As soon as the board is selected
(PIO_CS- low and MODID matches PIO_A[18-21]), PIO_WAIT- is asserted. When the PIO access
is decoded and no additional wait states are needed, the PIO_WAIT- signal is de-asserted, and the
appropriate read/write pulses are generated.
If the PDRW or PDR2W is addressed, then the PDF signal from the corresponding DSP is used to
generate extra wait states, if necessary. A high PDF in a write cycle or a low PDF in a read cycle will
insert extra wait states until the condition goes away. A maximum of 15 wait states are allowed before
the state machine terminates the read/write cycle by releasing the PIO_WAIT- signal, and set the
TIMEOUT bit in the PISR. If the corresponding bit in the PIMR is also set, the PIO_IRQ0- is asserted
(driven low).
1.2.2.4 PIO Interrupt
The mezzanine board can interrupt the base board via the PIO_IRQ0- signal. There are 3 interrupt
sources on the mezzanine each of which has a corresponding bit in the PIMR and PISR. Bits 0 of PISR
reflect the signal levels of the DSP PIF pins. Bit 6 of PISR is set when a FIFO switch has occurred. Bit
7 is set by a PIO timeout.
An interrupt source is enabled when the corresponding bit in the PIMR is set and disabled if the bit is
reset. The contents of PISR and PIMR are bit-wise AND’ed, and the result is OR’ed to generate the
PIO_IRQ0- signal. The PIO_IRQ0- is asserted until all the interrupt sources are either turned off or
disabled. Reading the PIR clears the corresponding DSP interrupt. To clear the FIFO Switch and PIO
Timeout interrupts, set the CLR_FINT and CLR_TINT bits in the BCR1 respectively.
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1.2.3
Reset and Configuration
The EEPROM (NM93C46M8) contains board specific information for the mezzanine. The TCK and
TDO signals are connected to the SK and DO pins of the EEPROM. MODID0 and MODID3 are
AND’ed together and connected to the DI pin. The base board can use the information stored in the
EEPROM to configure the EMC12 appropriately.
Note that the sequence of numbers used for MODID is {0x7, 0x3, 0x1, 0x0, 0x8, 0xC, 0xE, 0xF}. 0xF is
the only number whose MODID0 and MODID3 bits AND’ed together gives ‘1’. This means to shift a
‘1’ into the DI pin of the EEPROM, the base board needs to drive a value to MODID such that the
targeted mezzanine sees 0xF as the MODID. Any other value will present a ‘0’ at the DI pin. For
example, if the base board wants to interrogate the EEPROM of the second mezzanine, it needs to send a
sequence of ‘1’s and ‘0’s to the EEPROM. To send a ‘1’, it should drive 0xE to MODID, and to send a
‘0’, it can drive 0x7.
Activating the PROGRAM- signal clears the FPGA (XC4013E) internal configuration memory and the
FPGA is ready for reprogramming. The TDI, TDO, TCK signals are connected to the respective pins on
the FPGA. The MODID0 and MODID3 signals are NAND’ed and connected to the TMS pin of the
FPGA. These four pins are used to program the device with the JTAG Configure command. Note the
INIT- pin of the FPGA is pulled low to prevent the device from entering normal configuration through the
Mode pins.
Since the signals are shared between the FPGA and EEPROM, EECS is used to select the intended
device. When EECS is active, the EEPROM is enabled. The EECS signal is also OR’ed with TMS so
that when EECS is a ‘1’ the TMS input of the FPGA is also a ‘1’. This keeps the JTAG in the idle state
when the EEPROM is being accessed.
The RESET- signal is connected to the FPGA Global Set/Reset net, and the ZN pin of each DSP. When
RESET- is active (low), all DSP outputs are tri-stated and the FPGA internal registers are put in a known
state. The DSP_RESET bit in BCR0 becomes ‘0’ which halts all the DSPs on the mezzanine. In
addition, the FIFOs are reset and all TDM control information is cleared.
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1.3
EMC12 TDM
Serial data passing between resources in an EmPack system are routed through 6 time-divisionmultiplexed (TDM) buses They are called buses A, B, C, D, E and F. Each contains a data signal and a
valid signal. The Table below shows how LTDM lines are allocated among the 6 buses.
Table 1-12: LTDM[0-11] Signal Allocation
TDM BUS
A
B
C
D
E
F
TDM Data
LTDM0
LTDM1
LTDM4
LTDM5
LTDM8
LTDM9
TDM Valid
LTDM2
LTDM3
LTDM6
LTDM7
LTDM10
LTDM11
All 6 buses run synchronously at the same bit clock rate, with identical slot definition, frame duration and
frame sync pulse. The buses are connected to the serial port of each DSP. The TDM system operates
independently of the parallel I/O system.
Frames of data are passed through each serial TDM bus. The number of slots per frame is fixed at 128.
Each time slot has a fixed length of 8 bits. A buffered version of LCLK (SLCK) is used as the TDM bit
clock. The LFSYNC- signal is used to indicate frame boundary. It goes low on the falling edge of
LCLK for one LCLK period and the frame boundary falls within that pulse.
The TDM subsystem also has the concept of “Superframe” or “Multiframe” timing. The signal,
LMSYNC is a high active pulse that lasts for one TDM frame with transitions on a frame boundary. The
number of frames per Multiframe is controlled by the foundation board using the API function,
EmSetTdmMode . The LMSYNC signal is connected to the SY pin of the DSP. A DSP program can
test the state of the SY pin (using the sys flag to test if LMSYNC is high and the syc flag to test if
LMSYNC is low). A DSP program can synchronize its serial input and output to the TDM frames by
testing for a transition on the LMSYNC signal.
1.3.1
TDM Connections
The interconnection of TDM data to various resources in the system is dynamically controlled by the
contents of the TDM map. For each time slot, a set of control words in the map determines the source
and destination(s) of the data on each TDM bus. The control words are recycled in every TDM frame.
For the EMC12 mezzanine, eight control words are used to establish connection for each time slot.
Tables 1- 13, 1-14, and 1-15, below, show the format of the control words.
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The TDM Map control words are controllable using functions in the host API. These are described in
section 3.4.8 of this manual.
Table 1-13: TDM Source Control Word Definition (Words 0-2)
Word
0
1
2
Bits 4 - 7
Bus A Source
Bus C Source
Bus E Source
Bits 0 - 3
Bus B Source
Bus D Source
Bus F Source
Table 1-14: TDM Destination Control Words Definition (Words 3-6)
Word
3
4
5
6
Bits 8 - 6
CODEC0 Destination
CODEC3 Destination
CODEC6 Destination
CODEC9 Destination
Bits 5 - 3
CODEC1 Destination
CODEC4 Destination
CODEC7 Destination
CODEC10 Destination
Bits 0-2
CODEC2 Destination
CODEC5 Destination
CODEC8 Destination
CODEC11 Destination
Table 1-15: TDM Destination Control Word Definition (Word 7)
Word
7
Bits 0 - 3
DSP Destination
Tables 1-16, 1-17 and 1-18 below shown the meanings of the values for each type of control word.
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Table 1-16: Bus Source Encoding
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Meaning
CODEC0 drives TDM data
CODEC1 drives TDM data
CODEC2 drives TDM data
CODEC3 drives TDM data
CODEC4 drives TDM data
CODEC5 drives TDM data
CODEC6 drives TDM data
CODEC7 drives TDM data
CODEC8 drives TDM data
CODEC9 drives TDM data
CODEC10 drives TDM data
CODEC11 drives TDM data
DSP sends TDM valid control
DSP sends TDM data
Continuation slot
No Connection
Table 1-17: CODEC Destination Encoding
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
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Meaning
CODEC receives from Bus A
CODEC receives from Bus B
CODEC receives from Bus C
CODEC receives from Bus D
CODEC receives from Bus E
CODEC receives from Bus F
Continuation slot
No connection
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Table 1-18: DSP Destination Encoding
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6 - 0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1.3.2
Meaning
DSP receives unconditionally from Bus A
DSP receives unconditionally from Bus B
DSP receives unconditionally from Bus C
DSP receives unconditionally from Bus D
DSP receives unconditionally from Bus E
DSP receives unconditionally from Bus F
Reserved
DSP receives conditionally from Bus A
DSP receives conditionally from Bus B
DSP receives conditionally from Bus C
DSP receives conditionally from Bus D
DSP receives conditionally from Bus E
DSP receives conditionally from Bus F
Continuation slot (no ILD)
No connection
Continuation Slots
Normally a time-slot carries a single, 8-bit data item across each TDM bus. However, the TDM system
allows the use of consecutive time-slots on the TDM bus to carry larger data items. Four time-slots, for
example, can be combined to carry a 32-bit word. The technique of using multiple time-slots to carry a
larger data item is called “slot continuation”. When slot continuation is selected for a TDM bus, the
FPGA continues driving DSP serial data onto the TDM bus without generating an OLD pulse. Similarly,
the TDM bus data is driven to the DSP serial input without a ILD pulse. The same concept is used for
transferring 16-bit data items to or from the Codecs, using pairs of consecutive 8-bit time slots.
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1.3.3
TDM Validity and Conditional Transfers
Each TDM bus has a data signal and a valid signal. The valid signal is used to indicate whether a given
time-slot contains valid data. When a DSP is selected as the source of a TDM bus for a time-slot, the
OBE signal from the DSP is sampled before OLD pulse is generated. If OBE is low, indicating that the
DSP’s serial buffer has data to send, the OLD pulse is generated and the valid signal is driven high for
one bit clock. The valid signal is also driven high for one bit clock when a Codec is selected as the
source of a TDM bus. If OBE is high, indicating that the DSP’s serial output buffer is empty, the OLD
pulse is suppressed, and the valid signal is driven low for 1 bit clock.
When a DSP is selected to conditionally receive from a TDM bus, the valid line of the that bus is sampled
before the ILD pulse is generated. If the valid signal is low, the ILD pulse is suppressed and the data on
the bus is ignored.
SLCK
OBE
OLD
DO
OLD suppressed
D0
TDMDATA
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TDMVALID
ILD
ILD suppressed
D0
DI
D1
D2
D3
D4
D5
D6
D7
LMSYNC
INTREQ1
IBF
Figure 1-3: TDM Timing
1.3.4
Programmable TDM Validity
For the conditional TDM transfers described above, the hardware between the DSP and the TDM
subsystem determines whether a time slot’s data is valid based on the state of the DSP’s OBE signal.
Some applications may require the DSP to determine when the data it has to send is valid or not. For
example when dealing with isochronously generated data (such as E1 or T1 framers) the DSP will be
sending data at a constant rate and on a fixed and multiple number of time slots per TDM frame. In
order to maintain synchronization with the TDM frame, the DSP must be allowed to transmit serial data
for every time slot on which it is connected to the TDM bus. However there may be times when the
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DSP has no valid data to send on one or more time slots such as when a frame slip is detected on an
incoming E1 or T1 stream.
The EMC12 hardware provides a mechanism for the DSP to control the TDM valid signal that
accompanies each TDM data bus. This is accomplished by using pairs of consecutive TDM time slots.
For each pair of time slots to be connected in this way, the first time slot is given a Source control value
of 0xC (DSP Sends TDM Valid Control) and the second time slot is given a Source control value if 0xD
(DSP Sends TDM Data). These control word pairs must be encoded for the same TDM bus on
consecutive time slots.
When pairs of time slot control words are encoded this way, they behave as though the second time slot
was a continuation slot. The DSP receives one OLD signal for the pair, at the beginning of the first time
slot. The DSP is then expected to transmit 16 bits of serial data. The first 8 bits contain the TDM valid
information and the second 8 bits is the byte of data to be driven as TDM data on the selected TDM bus.
The 2nd bit of the valid information is sampled by the hardware and used to control the TDM valid signal
for the second time slot of the pair.
The examples below show how to build a 16-bit serial data word in the DSP program for a data byte that
is valid and one that is invalid. The bit ordering assumes that the DSP’s IOC register is set to transmit
the most significant bit of the serial output buffer first and that it will be transmitting serial data from the
memory referenced by serial_out_buffer using serial DMA output.
unsigned short serial_out_buffer[64];
char out_data[64]
int data_valid[64];
for (i = 0; i < 64; ++i)
{
serial_out_buffer[i] = out_data[i];
if (data_valid[i])
serial_out_buffer[i] |= 0x4000;
}
1.3.5
TDM FIFO
The TDM control words for an entire TDM frame are stored in one of two FIFOs on the board. The
FIFO being used for the current TDM frame is the active FIFO, the other is called the inactive FIFO.
The inactive FIFO can be read/written by the base board through the TCDR using PIO read/write
operations. Writing a ‘1’ to the FIFO_RT (FIFO Retransmit) bit in BCR1 resets the FIFO read pointer.
The word read from the TCDR after a FIFO Retransmit is the first word in the FIFO.
To load a new TDM control map, write a ‘1’ to the FIFO_RESET bit in BCR1. This resets the
read/write pointers of the FIFO. Then write each word (9-bit) of the map to the TCDR. A maximum of
1024 words can be written. The 1024th word is written to the LTCW register instead of the FIFO.
When the entire map is loaded, write a ‘1’ to the SWITCH_FIFO bit in BCR1. The inactive FIFO will
become active at the next frame boundary. The deactivated FIFO can be read and written by the base
board after the switch.
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This scheme of using two FIFOs and switching at frame boundary ensures that TDM control maps are
always valid and consistent.
1.3.6
TDM Last Control Word
Due to hardware limitations, the last TDM control word of the FIFO is not actually used for TDM
control. It is replaced on the fly with the contents of the “Last TDM Control Word” register of the
FPGA. Therefore, all software that affects the EmC12 TDM map must take this into account and make
sure that the “Last TDM Control Word” register is accessed instead of the last FIFO word.
1.3.7
TDM Reset
After power-on or board reset, the TDM_RESET bit in BCR0 is ‘0’. This bit can also be read/written by
the base board using the PIO interface.
When the TDM_RESET bit is ‘0’, the EMC12’s TDM system becomes idle. It does not drive any of the
LTDM lines or DSP SIO signals. Before writing a ‘1’ to the TDM_RESET bit, the base board should
setup the FIFOs with valid TDM control words. The TDM becomes active at the second frame
boundary after TDM_RESET become ‘1’.
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1.3.8
API Functions for TDM Control
The Empack host API includes several functions for controlling the TDM timing and connection map.
This section describes how these functions pertain to the EMC12 mezzanine. See the Empack API
Reference manual for more details about these functions.
1.3.8.1 TDM Timing and Operation Functions
The basic timing is fixed with a bit clock of 8.192 MHz, basic slot size of 8-bits and frame of 128 time
slots. The clock source and the number of frames per Multiframe is controlled by the Empack foundation
board and using the host API with the EmSetTdmMode function:
int
EmSetTdmMode (
EMPACK_HANDLE Empack,
int Mode,
int Multiframe,
int ModuleId
)
The Mode argument specifies the timing reference and clock configuration, specifying the source
of TDM clock, whether or not the Empack is supply the clock, sync and 8kHz reference clock to
the SCSA expansion bus. The Multiframe argument specifies the number of TDM frames per
Multiframe and the ModuleId argument specifies which mezzanine is supplying TDM clock if
the Mode argument specifies that the clock is supplied from a Mezzanine.
In case an application is required to adopt the current TDM configuration of an Empack the following
function is used to determine the current mode settings and initialize the software state to the current
hardware settings:
int
EmGetTdmMode (
EMPACK_HANDLE Empack,
int *Mode,
int *Multiframe,
int *ModuleId
)
This function will always initialize the API’s internal flags to match the current settings. If
desired, the values may be returned to the application by specifying pointers to store the values
for Mode, Multiframe and ModuleId. Specify NULL as the pointer for any of the data not
required.
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The TDM subsystem for a module is enabled or disabled with the following two functions:
int
EmStartTdm (
MODULE_HANDLE Module
)
int
EmStopTdm (
MODULE_HANDLE Module
)
The TDM subsystem is initially disabled when the Empack first powers up and will also be
disabled after a call to the EmInitModule or EmInitEmpack functions. The EmStartTdm
function will also updates the hardware TDM map if any changes have been made to the API’s
software copy since the last time the Map was updated.
An application can determine if the TDM subsystem is currently enabled and if the hardware map is
current using the following functions:
int
EmIsTdmStarted (
MODULE_HANDLE Module,
int *Status
)
int
EmIsTdmMapCur (
MODULE_HANDLE Module,
int *Status
)
Both of these functions store their result (0 for no or 1 for yes) in the integer pointed to by the
Status argument.
1.3.8.2 TDM Map Functions
The API maintains a software copy of the TDM map for each module. Incremental modifications to the
map are made only to the software copy. The active, hardware copy of the map is updated when
specified and becomes active at the next TDM frame boundary. The TDM Map for a module is cleared
using the following function:
int
EmClearTdmMap (
MODULE_HANDLE Module
)
This function clears both the software and hardware copy of the TDM map. The cleared map
becomes active on the next TDM frame boundary. The TDM map is also cleared by the
EmInitModule and EmInitEmpack functions if they are called with the EM_INIT_FORCED
option. On power-up the TDM map contents are undefined so it is necessary to call one of these
functions to clear the TDM map before creating the desired map.
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The following function is used to update the hardware copy of the map after making one or more
incremental changed to the map:
int
EmWriteTdmMap (
MODULE_HANDLE Module
)
This function writes the software copy of the TDM map to the hardware if the hardware copy is
not current. The new map will become active on the next TDM frame boundary. Note that the
EmStartTdm function will also update the hardware map if it is not current.
In case an application is required to adopt the current configuration of the TDM map, the following
function is used to initialize the software copy of the map to reflect the current hardware map form the
module.
int
EmReadTdmMap (
MODULE_HANDLE Module
)
Note that in such cases, the application should not call EmInitModule , EmInitEmpack or
EmClearTdmMap as doing so would destroy the current configuration of the hardware. After
calling EmReadTdmMap the application may modify and update the map normally.
The following functions are used to make incremental additions, adding TDM sources or destinations to
the software copy of theTDM map.
int
EmAddTdmSrc (
MODULE_HANDLE Module,
RESOURCE_HANDLE Resource,
int Slot,
int Bus,
int Option1,
int Option2
)
int
EmAddTdmDst (
MODULE_HANDLE Module,
RESOURCE_HANDLE Resource,
int Slot,
int Bus,
int Option1,
int Option2
)
EmAddTdmSrc is used to add a device that will drive data onto a specified TDM bus during a
specified TDM time slot. EmAddTdmDst is used to add a device to receive data from a
specified TDM bus during a specified TDM time slot. Both functions require arguments to
specify the Empack Module and Resource for the TDM device.
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The Slot argument specifies the TDM time slot with valid values in the range of 0 through 127.
The Bus argument specifies the TDM bus with valid values in the range of 0 through 5 or macros
TDM_BUSA, TDM_BUSB, TDM_BUSC, TDM_BUSD, TDM_BUSE or TDM_BUSF.
The Option1 argument specifies additional information for the type of connection to be made.
For the DSP resource valid values are:
TDM_DATA
TDM_CONTINUE
TDM_CONDITIONAL
TDM_DSP_VALID
Normal TDM data connection
Continuation slot for 16 or 32 bit data
Conditional receive slot (EmAddTdmDst only)
Valid information slot to precede a data slot (EmAddTdmSrc only)
Valid values for Codec resources are:
TDM_DATA
TDM_CONTINUE
Normal TDM data connection
Continuation slot for 16 bit audio samples
The Option2 argument does not pertain to the EMC12 mezzanine and should be 0.
The following functions are used to make incremental additions, deleting TDM sources or destinations to
the software copy of theTDM map.
int
EmDelTdmSrc (
MODULE_HANDLE Module,
RESOURCE_HANDLE Resource,
int Slot,
int Bus,
int Option1
)
int
EmDelTdmDst (
MODULE_HANDLE Module,
RESOURCE_HANDLE Resource,
int Slot,
int Option1
)
EmDelTdmSrc is used to delete (or disconnect) a device from driving data onto a specified
TDM bus during a specified TDM time slot. EmDelTdmDst is used to delete (or disconnect) a
device from receiving data from a specified TDM bus during a specified TDM time slot. Both
functions require arguments to specify the Empack Module and Resource for the TDM device.
The Slot argument specifies the TDM time slot with valid values in the range of 0 through 127.
The Bus argument specifies the TDM bus with valid values in the range of 0 through 5 or macros
TDM_BUSA, TDM_BUSB, TDM_BUSC, TDM_BUSD, TDM_BUSE or TDM_BUSF.
Note that there is no Bus argument for EmDelTdmDst, it disconnects the device from whatever
bus is was receiving data from.
The Option1 argument does not pertain to the EMC12 mezzanine and should be 0.
1.3.8.3 Examples Using TDM_DSP_VALID Mode
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The normal TDM map connections using the Option1 modes of TDM_DATA, TDM_CONTINUE and
TDM_CONDITIONAL are self explanatory. However the TDM_DSP_VALID and
TDM_C12DSP_OLD modes may require some further explanation.
Section 3.4.4 describes how the programmable TDM validity mode, TDM_DSP_VALID, works at the
hardware level. Below is an example of setting up a TDM map for this mode using the API functions.
In the example, a TDM map is built for an EMC12 DSP to transmit data and control the valid line on 4
TDM slots. The DSP will synchronize to the TDM frame and begin sending 4 16-bit words per frame.
Each 16-bit word has the TDM valid information in the upper 8-bits and the TDM data is in the lower 8bits.
MODULE_HANDLE
RESOURCE_HANDLE
int
emc12;
dsp;
tdm_bus = TDM_BUSA;
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmAddTdmSrc(emc12,
EmStartTdm(emc12);
dsp,
dsp,
dsp,
dsp,
dsp,
dsp,
dsp,
dsp,
4,
5,
8,
9,
12,
13,
16,
17,
tdm_bus,
tdm_bus,
tdm_bus,
tdm_bus,
tdm_bus,
tdm_bus,
tdm_bus,
tdm_bus,
TDM_DSP_VALID,
TDM_DATA, 0);
TDM_DSP_VALID,
TDM_DATA, 0);
TDM_DSP_VALID,
TDM_DATA, 0);
TDM_DSP_VALID,
TDM_DATA, 0);
0);
0);
0);
0);
With this TDM map loaded, the DSP will receive 4 OLD pulses per frame, at the beginning of time slots
4, 8, 12 and 16. The EMC12 hardware receive 16 bits from the DSP’s serial output port during time slot
pairs 4/5, 8/9, 12/13 and 16/17. The first 8 bits of each pair is the validity information, which is actually
encoded in the 2nd bit received. This information is held until the second slot of each pair when it is used
to drive the TDM valid line to coincide with the TDM data. No TDM data or valid is driven from the
DSP during the first slot of each pair and, although the second time slot of each pair is encoded as
TDM_DATA mode, the DSP only receives an OLD pulse for the time slots encoded as
TDM_DSP_VALID.
Example 2:
There may arise a need to temporarily replace one or more of the time slots transmitted from the DSP
with data from another source such as a Codec on the same EMC12 mezzanine or a DSP or Codec on
another mezzanine. However, with DSP transmitting on a fixed number of time slots, synchronized to the
TDM frame, the OLD pulses to the DSP should remain constant. When using TDM_DSP_VALID
mode it is possible to maintain the OLD pulses that occur at the beginning of the time slots designated for
the valid information, yet not have the valid information or the data portion of the DSP’s 16-bit serial
output driven onto the TDM bus.
In the example, below, the map using TDM_DSP_VALID mode from the previous example will be
modified. Sometime after that map has been in use the data from the DSP will be replaced on time slot 9
by data from a Codec and on time slot 13 by data from a device on another mezzanine. The following
function calls make the necessary changes to the map on the EMC12 mezzanine.
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Note that for replacing the DSP data with Codec data, as long as the same TDM bus is used it is not
necessary to delete the normal TDM slot for the DSP. Simply specifying the new source device is
sufficient to properly modify the TDM map. None of the changes actually take affect until
EmWriteTdmMap is called.
/* Replace DSP source on slot 9 with Codec */
EmAddTdmSrc(emc12, codec, 9, tdm_bus, TDM_DATA, 0);
/* Discontinue driving slot 13 with DSP data and valid*/
EmDelTdmSrc(emc12, dsp, 13, tdm_bus, 0);
EmWriteTdmMap(emc12);
The DSP will continue to receive the OLD pulses at the beginning of time slots 8 and 12, as directed by
the TDM_DSP_VALID mode on those time slots. The DSP will also continue transmitting 16-bits of
serial data during time slot pairs 8/9 and 12/13, but the data and valid lines are only driven from the DSP
during time slots 5 and 17. Data from the Codec is now being driven onto the TDM bus during time slot 9
and nothing on this mezzanine is driving data on the TDM bus during time slot 17.
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1.4
EMC12 DSP
The EMC12 is optionally populated with one Agere DSP32C, an 80 MHz, 20 MIPs, 40 MFlops digital
signal processor chip. It is packaged in a 164-pin bumpered quad flat pack (BQFP). The DSP32C may
be operated from 50MHz to 80 MHz.
The DSP is controlled by an FPGA (Xilinx 4013E) which provides address decoding for the parallel ports,
external interrupt control, TDM interface, and interface to the status LEDs.
1.4.1
DSP Reset
The RESTN pin of the DSP is controlled by the DSP_RESET bit in BCR0. Writing a ‘0’ to this bit halts
the DSP. This bit is ‘0’ after power-up and board reset.
A transition from ‘0’ to ‘1’ of this bit initiates the DSP reset sequence. Refer to the DSP32C
Information Manual for in-depth discussion of halt and reset operations of the DSP.
1.4.2
DSP Interrupts
The two external interrupt pins of the DSP32C, INTREQ1 and INTREQ2, are controlled by the DSP
Interrupt Control Register (DICR) in the FPGA. The various external interrupt operations and their
control values are shown in Table 10.
1.4.3
DSP Clock
The serially programmable frequency generator ICS AV9110-02CS14 operates from a reference clock
of 14.318 MHz (REFCLK) available on the mezzanine connector. The output clock (CLK/X) from the
AV9110 is then distributed to the local clock multipliers ICS AV9170-01CS8 which quadruple the
frequency. The programmability of the AV9110 lets the DSP clock frequency be selected in software.
The local clock multipliers allow the AV9110 output clock to be distributed over a long distance at
relatively low frequencies. TDI is connected to the DATA pin of the AV9110, and TCK is inverted and
connected to the SCLK pin. To program the AV9110, set the AV9110_EN bit of BCR1 to select the
AV9110, shift the serial data using TDI and TCK, and reset the AV9110_EN bit in BCR1 to deselect the
AV9110.
Table 1-19 shows the format of the serial data shifted into the AV9110.
Note that bit 0 is the first bit shifted into the device.
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Table 1-19: AV9110 Serial Data Format
Bit(s)
0-6
7 - 13
14
Field
N
M
V
15 - 16
X
17 - 18
R
19
CLK_EN
20
CLK/X_EN
21
22
Reserved
CLK_SEL
23
Reserved
Function
VCO Frequency Divider
Reference Frequency Divider
VCO Pre-scale Divider
0b = divide by 1
1b = divide by 8
CLK/X Output Divider
00b = divide by 1
01b = divide by 2
10b = divide by 4
11b = divide by 8
VCO Output Divider
00b = divide by 1
01b = divide by 2
10b = divide by 4
11b = divide by 8
CLK Output Enable
0b = tristate
CLK/X Output Enable
0b = tristate
Should be 1
Reference clock select on CLK
1b = reference frequency
Should be 1
Default
1111111b
0010010b
0b
10b
10b
1b
1b
1b
0b
1b
The output frequency of CLK/X is given by:
fCLK/X = (fREF • N • V ) / (M • R • X)
where fREF is the input reference clock.
For a reference clock of 14.318MHz, Table 20 shows the bit stream associated with several commonly
used DSP clock frequencies. Note that CLK/X is multiplied by 4 to generate the DSP clock.
Table 1-20: Common AV9110 Data Stream
DSP Clock Frequency (MHz)
50
74
80
Bit Stream (Bit 23 - Bit 0)
0xB305CD
0xB304DD
0xB288DF
Refer to ICS AV9110 data sheet for more information on programming the device.
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1.4.4
DSP Memory
The DSP can operate in either memory mode 6 or 7. The mode is controlled by the DSP_MMODE bit in
BCR0. A ‘0’ selects mode 6 and a ‘1’ selects mode 7. This bit is ‘0’ after power-up and board reset.
New memory mode will not take effect until a DSP reset sequence is performed by a ‘0’ to ‘1’ transition
of the DSP_RESET bit of BCR0.
The DSP has up to 2 Mbytes of 0-wait-state SRAM. Table 1-21 shows the address map for the DSP.
Table 1-21: DSP Memory Configurations
DSP Memory Address
0x000000
0x0007FF
0x000800
0x1FFFFF
0xFFE000
0xFFE7FF
0xFFF000
0xFFF7FF
0xFFF800
0xFFFFFF
1.4.5
Physical Memory Accessed
Mode 6
0x000000
Mode 7
Internal RAM0
0x1FFFFF
Internal RAM2
0x000800
0x1FFFFF
Internal RAM2
Internal RAM0
<none>
Internal RAM1
Internal RAM1
Sync Input
The Multi-Frame (LMSYNC) signal from the EmPack mezzanine connector is buffered and connected to
the SY pin of the DSP. The DSP program can read the level of the signal at any time.
The LMSYNC pulse lasts one full TDM frame and occurs every N frames, where N is 1, 2, 3, ..., 32.
Figure XX below shows the timing of the LMSYNC rising edge. The falling edge timing is identical but
occurs one TDM frame later.
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1.5
EMC12 CODECS
This section describes the basic operation of the Crystal CS4231A CODECs, as they are integrated on
the EMC12 mezzanine. Additional details on the operation of the CODECs may be found in the data
sheet for the CS4231A CODEC which is available on CAC’s FTP site
(ftp://ftp.cacdsp.com/pub/datasheets/crystal/cs4231a.pdf).
The EmPack application interface library includes several functions for controlling various settings for the
EMC12 CODECs. All of them operate on a RESOURCE HANDLE obtained by calling the
EmOpenResource function. The functions for setting parameters (EmSetCodec…) may be used to
control individual channels or all 12 channels simultaneously if the RESOURCE HANDLE references the
Broadcast resource, resource ‘m’ of an EMC12 mezzanine. The functions for reading current
parameters (EmGetCodec…) may only be used for individual channels. Brief descriptions of these
functions appear here. More details may be found in the EmPack Software Reference Manual.
1.5.1
Analog I/O
1.5.1.1 Gain Stages and Analog Characteristics
The figure below shows a functional diagram of the input and output gain stages for each of the 12 analog
channels (2 channels per CODEC).
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Figure 1-4: CODEC Channel Gain Stages
INPUT CHARACTERISTICS
1. The differential input amplifier introduces a -6dB attenuation, whether the input is configured as
differential or single -ended (see Section 1.5.3).
2. Maximum input is 23 Vp-p.
3. “External Atten” selects either 0 or –20 dB .
4. The clamp limits the voltage to protect the CODEC inputs. Care must be taken in setting the
external attenuator such that its output does not exceed ~4.8 Vp-p, at which point the signal be
clamped.
5. The CODEC Input Mux can select either MIC, MIC +20dB , LINE, or the output looped back.
6. The ADC gain can be set to 0 to 22.5 dB in 16 steps of 1.5 dB
7. The overall range of input gain/attenuation is –46 dB to +36.5 dB , where 0 dB results in a full
scale ADC conversion for 2.8 Vp-p at the differential input.
OUTPUT CHARACTERISTICS
1. The DAC attenuation can be set from 0 to -94.5 dB in 64 steps of 1.5 dB
2. The output has a +7 dB stage for compatibility with previous CAC products.
3. The final output gain stage introduces a +6dB gain, whether the output is configured as
differential or single -ended (see Section 1.5.3).
4. The overall range of output gain/attenuation is –81.5 dB to +13 dB , where 0 dB results in a full
scale voltage of 2.8 Vp-p at the differential output.
1.5.1.2 Gain Control API Functions
Output Muting:
int
EmSetCodecMute (
RESOURCE_HANDLE Resource,
BOOL Mute
)
int
EmGetCodecMute (
RESOURCE_HANDLE Resource,
BOOL *Mute
)
The EmSetCodecMute function controls the analog output muting. Muting is turned on (output
silent) if the Mute argument is TRUE (non-zero) and turned off if it is FALSE. The
EmGetCodecMute function returns the current mute setting in the memory pointed to by its
Mute argument.
Overall Input and Output Level Settings:
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int
EmSetCodecLevels (
RESOURCE_HANDLE Resource,
float Input
float Output
)
int
EmGetCodecLevels (
RESOURCE_HANDLE Resource,
float *Input
float *Output
)
The EmSetCodecLevels function provides a simple method to control the overall gain /
attenuation settings of the analog input and output. It adjusts all aspects of the input and output
gain stages to achieve the specified gain or attenuation, selecting which CODEC input to use and
taking into account the clipping level of the CODEC’s input clamp. The Input argument
specifies the overall input gain or attenuation in the range of –46.0 dBV to +36.5 dBV. The
Output argument specifies the overall output gain or attenuation in the range of –81.5 dBV to
+13 dBV. The values specified are relative to the nominal full scale level of 2.8 Vp-p. Note that
the actual settings will be rounded to the nearest 1.5 dB step.
The EmGetCodecLevels function returns the current input and output level settings, storing the
results in the memory pointed to by its Input and Output arguments.
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Converting Levels from VME6U6-C12 to EMC12:
The gain stages of the EMC12 Mezzanine were designed to provide a similar range of input and
output levels as the C12 Mezzanine for the VME6U6 boards. However, some differences
remain. Most notably, the EMC12 gain/attenuation settings are specified in decibels and the
VME6U6-C12 levels are specified as integer values used to set the digitally controlled voltage
dividers in its CODECs. There is also a different nominal full scale voltage reference; 2.8 Vp-p
for the EMC12 compared to 6.3 Vp-p for the VME6U6-C12.
These differences can be accommodated for with the following formulas to convert input and
output settings for the VME6U6-C12 to the decibel values for the EMC12. For both formulas,
value refers to the digital potentiometer values used for the VME6U6-C12 and dB refers to the
EMC12 values to be passed to the EmSetCodecLevels function.
Input level conversion:
dB = 20 * log (value / 128) – 7.0
Output level conversion:
dB = 20 * log (value / (256 – value)) + 7.0
Controlling Individual Gain / Attenuation Components:
The following functions in the EMAPI are available should you find it necessary to control the
various analog gain stages and signal paths separately. Please refer to the EmPack Software
Reference Manual for an explanation of the functions’ usage and arguments.
The functions below control the input signal path and gain stages; enabling the external –20 dB
attenuator, selecting the Mic or Line input to the CODEC, enabling the CODEC’s internal 20 dB
gain for the Mic input and the value of the CODEC’s register that sets its ADC gain.
int
EmSetCodecExtInputAtten (
RESOURCE_HANDLE Resource,
BOOL ExtInputAtten
)
int
EmGetCodecExtInputAtten (
RESOURCE_HANDLE Resource,
BOOL *ExtInputAtten
)
int
EmSetCodecInputSel (
RESOURCE_HANDLE Resource,
int InputSel
)
int
EmGetCodecInputSel (
RESOURCE_HANDLE Resource,
int *InputSel
)
int
EmSetCodecMi cGain (
RESOURCE_HANDLE Resource,
int
EmGetCodecMicGain (
RESOURCE_HANDLE Resource,
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BOOL MicGain
BOOL *MicGain
)
)
int
EmSetCodecAdcGain (
RESOURCE_HANDLE Resource,
int AdcGain
)
int
EmGetCodecAdcGain (
RESOURCE_HANDLE Resource,
int *AdcGain
)
The functions below control the value of the CODEC’s register that sets its DAC attenuation:
int
EmSetCODECDacAtten (
RESOURCE_HANDLE Resource,
int DacAtten
)
1.5.2
int
EmGetCODECDacAtten (
RESOURCE_HANDLE Resource,
int *DacAtten
)
Data Conversion Mode and Sampling Rate
The following two functions in the EmPack API control the analog-to-digital and digital-to-analog
conversion process. The two parameters are the data conversion format and the sampling rate.
The functions operate on registers inside the CS4231 CODECs as well as setting register bits in
the EMC12’s FPGA controlling the interface between the CODEC and the TDM subsystem.
These functions may be applied to an individual resource or the EMC12 broadcast resource.
Note, however, that these operations apply to both channels in the CODEC for an individual
resource. Therefore, setting the data conversion format or sampling rate for CODEC resource
‘a’ will set the same parameters for channel ‘b’. Setting these parameters for channel ‘c’ will
also set them for channel. ‘d’, etc.
int
EmSetCodecCvMode (
RESOURCE_HANDLE Resource,
int InputCvMode
int OutputCvMode
)
int
EmGetCodecCvMode (
RESOURCE_HANDLE Resource,
int *InputCvMode
int *OutputCvMode
)
The EmSetCodecCvMode function controls the digital data format (conversion mode) used by
the CODEC. The modes for input and output are specified as separate arguments,
InputCvMode and OutputCvMode, and may be different if desired. The valid values for the
conversion modes are defined as macros in the emapi.h. They are:
EM_CS4231_LIN8
EM_CS4231_LIN8_D
EM_CS4231_LIN16
EM_CS4231_LIN16_B
EM_CS4231_ULAW
EM_CS4231_ALAW
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Unsigned 8-bit Linear
Unsigned 8-bit Linear with Dither (for Input only)
Signed 16-bit Linear
Signed 16-bit Linear, Big Endian (byte reversed)
µ-Law Companded, 8-bit
A-Law Companded, 8-bit
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The EmGetCodecCvMode function reads the current conversion modes and stores the results
in the memory pointed to by its InputCvMode and OutputCvMode arguments.
When using the 16-bit conversion modes, it is necessary to configure the TDM map to use pairs
of consecutive TDM slots to carry each 16-bit sample. This is accomplished by configuring the
TDM MAP using first a normal TDM slot connection, followed by a CONTINUATION slot in
the succeeding time slot.
Note that the linear 8-bit conversion for the CS4231A CODEC deals with unsigned values. This
is not directly compatible with the DSP32C’s iconv and oconv instructions which deal with
signed 8-bit values.
int
EmSetCodecSampleRate (
RESOURCE_HANDLE Resource,
int SampleRate
)
int
EmGetCodecSampleRate (
RESOURCE_HANDLE Resource,
int *SampleRate
)
The EmSetCodecSampleRate function controls the sample rate of the CODEC. Valid values
for the SampleRate argument are defined as macros in the emapi.h. They are:
EM_CS4231_SR8
EM_CS4231_SR16
EM_CS4231_SR32
EM_CS4231_SR48
8 kHz Sample Rate
16 kHz Sample Rate
32 kHz Sample Rate
48 kHz Sample Rate
The TDM connections for the CODECs must be configured in accordance with the selected
sample rate. The EmPack TDM subsystem runs with a fixed frame rate of 8 kHz with 128 slots
per frame and 8-bits per slot. The simplest scenario is when the CODEC is set for 8 kHz
sampling rate; data must be transferred between the TDM subsystem and each CODEC channel
at a rate of one sample per TDM frame. However, at higher sampling rates multiple samples
must be transferred during each TDM frame and the transfers for each sample must occur
within certain fixed time slot ranges. The ranges of time slots for each sample depend on the
selected sample rate. Table 22, below, shows the valid TDM time slot ranges for each CODEC
data sample at the various sampling rates.
Table 1-22: CODEC / TDM Transfer Mapping
Sample
Rate
8 kHz
16 kHz
32 kHz
48 kHz
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Samples
per Frame
1
2
4
6
1
0 - 127
0 - 63
0 - 31
0 - 19
2
64 - 127
32 - 63
20 - 41
Time Slot Range for Sample:
3
4
5
64 - 95
96 - 127
42 - 63
64 - 83
84 - 105
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The EmGetCodecSampleRate function reads the current sample rate and stores the result in the memory
pointed to by its SampleRate argument.
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1.5.3
I/O Jumper Settings
For each of the 12 CODEC channels, there are two jumper blocks that configure the analog I/O circuitry.
Figure 5 shows a diagram representing one section of the EMC12 PCB. This section is repeated 12
times in a 2 x 6 array on the board near the front audio connector.
1
2
2
1
Figure 1-5: CODEC Channel Jumper PCB Section
One jumper block is 4x2 and is used as follows:
Table 1-23: 4 x 2 Jumper Block
Jumper Pair
1-2
2-4
5-6
3-5
5-7
6-8
Function
Microphone Power
DC Coupled Input
DC Differential Input
AC Coupled Single-Ended Input
DC Coupled Single-Ended Input
Single-Ended Input
The second jumper block is 2x2 and is used as follows:
Table 1-24: 2 x 2 Jumper Block
Jumper Pair
1-2
3-4
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Input Terminated with 604 Ohms
Single-Ended Output
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Table 1-25 shows a variety of common configurations for reference.
Table 1-25: CODEC Jumper Block Examples
DC Differential Input, Differential Output
1
2
DC Differential Input, Single-Ended Output
2
1
1
2
DC Differential Input, 600 Ohm Input
1
2
DC Single-Ended Input
2
1
1
2
1
Microphone Power
2
1
1
2
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2
1
AC Single-Ended Input
2
2
1
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1.5.4
EmPack Audio Signals
The input and output audio channels as routed through the EmPack system are differential, i.e. a pair of
wires (+ and -) carry each signal. The numbering of the twelve channels start with 0 and ends with 11.
Therefore, the input side of the first channel consists of the signals IN00+ and IN00-. Likewise, the
outputs are labeled OUT00+ and OUT00-. In addition to the 48 signal wires, there are 20 pins that are
either grounded or no-connections making a total of 68-pins. Two standard 68-pin SCSI connectors (one
from AMP and the other from Thomas&Betts) and standard 68-pin SCSI cable are used for interconnect
of the audio components of the EmPack system.
Figures 3-4 and 3-5 can be used to distinguish between the AMP and T&B styles of connectors and to
locate pin 1 for each type. Note that these figures represent the connectors soldered onto the circuit
board and not the cable connector.
Typically, Thomas&Betts (T&B) connectors are used between the EmPack codec cards mounted inside
the card cage and the rear-panel circuit board. Flat ribbon cable is used for the interconnection.
Figure 1-6: Thomas & Betts connector
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AMP connectors are used between the outside of the rear-panel and the audio patch panel. Standard
external SCSI cables with thumbscrews or latches are used to make these connections.
Figure 1-7: AMP connector
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Table 1-26: AMP and T&B OUT Signals
Signal
OUT00+
OUT00OUT01+
OUT01OUT02+
OUT02OUT03+
OUT03OUT04+
OUT04OUT05+
OUT05OUT06+
OUT06OUT07+
OUT07OUT08+
OUT08OUT09+
OUT09OUT10+
OUT10OUT11+
OUT11GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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AMP
35
1
37
3
41
7
43
9
46
12
48
14
54
20
57
23
59
25
61
27
63
29
66
32
5
6
11
21
30
34
16
17
18
19
-------
T&B
65
66
61
62
53
54
49
50
43
44
39
40
27
28
21
22
17
18
13
14
9
10
3
4
------7
8
25
26
29
30
31
32
33
34
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Table 1-27: AMP and T&B IN Signals
Signal
IN00+
IN 00IN 01+
IN 01IN 02+
IN 02IN 03+
IN 03IN 04+
IN 04IN 05+
IN 05IN 06+
IN 06IN 07+
IN 07IN 08+
IN 08IN 09+
IN 09IN 10+
IN 10IN 11+
IN 11GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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2
36
4
38
8
42
10
44
13
47
15
49
22
56
24
58
26
60
28
62
31
65
33
67
39
40
45
55
64
68
50
51
52
53
-------
T&B
64
63
60
59
52
51
48
47
42
41
38
37
24
23
20
19
16
15
12
11
6
5
2
1
------35
36
45
46
55
56
57
58
67
68
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1.6
Display LEDs
The EMC12 has a pair of status LEDs controlled by the DSP. The DSP can access these indic ators by
writing to any address between 0x800000 and 0xBFFFFF. The pair of LEDs display the value of the two
least significant bits written. The green LEDs corresponds to D1 and the yellow LED corresponds to
D0.
Note that, due to the physical memory wrapping around the 24-bit address space, writing to the LEDs will
also write data to the corresponding location in external RAM.
1.7
Temperature Sensor
The EMC12 has a DS1620 temperature sensor. The TCK and TDI signals are connected to the CLK
and DQ pins of the DS1620. To send/receive serial data to/from the device, set the DS1620_EN bit in
BCR1. Reset the bit to finish the data transmission. Refer to the Dallas DS1620 Data Sheet for
information on the serial data format.
1.8
Mechanical Characteristics
The EMC12 is implemented as a mezzanine in the EmPack system. It is secured to a heat spreader
which is, in turned, mounted on the EmPack card cage. The overall dimension of the board with the
spreader is 8.1” long, 5.5” wide, 0.3” high. The bottom mezzanine connector (P2) is a 60x2 position plug
and the top connector (J1) is a matching 60x2 position receptacle. The EMC12 board must be separated
from the EmPack baseboard and any other EMC12 mezzanine by either an EM6X32C mezzanine or an
EBX1 spacer.
A separate 4-pin standard disk drive power connector (P1) supplies +5V. The +12V is not used on this
board.
1.9
Power Consumption
The EMC12 requires +5V, and +12V. The power consumption requirement depends on the clock speed
and the activity on the board. Power consumption has been empirically found to be as follows for boards
populated with and without a DSP:
Product part Number
Supply
Current
Power
EBC2 (without DSP)
5 volts
12 volts
0.60 A
0.25 A
3.0 W
3.0 W
EBC1 (with DSP @ 74 MHz)
5 volts
12 volts
1.10 A
0.25 A
5.5 W
3.0 W
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1.10
Software
Software drivers for Solaris, Windows NT and Window 2K are provided, together with a host API to
allow access to and control of the EMC12 from user-developed programs. Diagnostics are provided
which are sufficient to verify correct operation of all functional blocks on the EMC12.
1.11
Reference Documents
1. Crystal Semiconductor CS4231A Data Sheet.
2. Xilinx XC4000 Series FPGA Data Sheet, September 1996.
3. AT&T DSP32C Digital Signal Processor Data Sheet, February 1995.
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