TECHNICAL DATA IN74LV640 Octal 3-State Inverting Bus Transceiver The 74LV640 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT640. The 74LV640 provides six inverting buffers with Schmitt-trigger action. • • • • Wide Operating Voltage: 1.2 to 3.6 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current ORDERING INFORMATION IN74LV640N Plastic IN74LV640D SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM DIR OE OE A2 03 18 B1 A3 04 17 B2 16 B3 640 15 B4 A6 07 14 B5 A7 08 13 B6 A8 09 12 B7 GND 10 11 B8 16 15 FUNCTION TABLE 14 A6 B6 08 19 A5 B5 07 A1 02 A4 B4 06 17 A3 B3 05 18 A2 B2 04 VCC A5 06 19 A1 B1 03 20 A4 05 01 02 DIR 01 B7 A8 12 09 B8 Inputs 13 A7 11 Inputs/Outputs OE DIR А В L L A=B input L H input B=A H X Z Z PIN 20=VCC PIN 10 = GND 1 IN74LV640 MAXIMUM RATINGS* Symbol VCC Parameter DC supply voltage (Referenced to GND) Value Unit -0.5 ÷ +5.0 V 1 DC input diode current ±20 mA 2 DC output diode current ±50 mA DC output source or sink current -bus driver outputs ±35 mA IGND DC GND current for types with - bus driver outputs ±70 mA ICC DC VCC current for types with - bus driver outputs ±70 mA PD Power dissipation per paskade, plastic DIP+ SOIC package+ 750 500 mW -65 ÷ +150 °C 260 °C IIK* IOK* Io* 3 Tstg TL Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 65° to 125°C SOIC Package: : - 8 mW/°C from 65° to 125°C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tLH, tHL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min Max Unit 1.2 3.6 V 0 VCC V -40 +125 °C 0 1000 700 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74LV640 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter VIH High-Level Input Voltage VIL Low -Level Input Voltage VOH High-Level Output Voltage Test Conditions VCC VO = VCC0.1 V 1.2 2.0 3.0 3.6 VI = VIH – or VIL IO = -50 µA VI = VIH – or VIL -40°C ÷ 85°C 25°C V 1.2 2.0 3.0 3.6 min 0.9 1.4 2.1 2.5 - max - 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 0.3 0.6 0.9 1.1 - 3.0 2.48 1.2 2.0 3.0 3.6 min 0.9 1.4 2.1 2.5 - max - -40°C ÷ 125°C min max 0.9 1.4 2.1 2.5 - 1.0 1.9 2.9 3.5 0.3 0.6 0.9 1.1 - 1.0 1.9 2.9 3.5 0.3 0.6 0.9 1.1 - - 2.34 - 2.20 - - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.09 - 0.1 0.1 0.1 0.09 3.0 - 0.33 - 0.40 - 0.50 Unit V V V IO = -8.0 mA VOL Low-Level Output Voltage VI = VIH – or VIL IO = 50 µA VI = VIH – or VIL V IO = 8.0 mA IIL Low-Level Input Leakage Current VI=0 V * - -0.1 - -1.0 - -1.0 µA IIH High-Level Input Leakage Current VI= VСС * - 0.1 - 1.0 - 1.0 µA IOZ Maximum Three-State Leakage Current VI= VIL or VIH VO=VCC or GND 1.2 * - ±0.5 - ±5.0 - ±10 µA ICC Quiescent Supply Current (per Package) VI=0 V or VСС * - 8.0 - 80.0 - 180.0 µA IO = 0 µA . 3 IN74LV640 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 6.0 ns, RL=1 kΩ) Guaranteed Limit Symbol Test Conditions Parameter VCC -40°C ÷ 85°C 25°C V -40°C ÷ 125°C min max 140 34 21 Unit 1.2 2.0 * min - max 100 23 14 min - max 125 28 18 1.2 2.0 * - 120 30 20 - 140 37 24 - 160 43 28 ns tPLH, tPHL Propagation Delay, A to B , B to A tPLZ, tPHZ Propagation Delay , Direction or Output Enable to A or B VIL=0 V VIH=VCC tLH = tHL =6.0 ns СL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns СL = 50 pF tPZL, tPZH Propagation Delay , Direction or Output Enable to A or B VIL=0 V VIH=VCC tLH = tHL =6.0 ns СL = 50 pF 1.2 2.0 * - 120 28 17 - 140 35 21 - 160 43 26 ns tTLH, tTHL Output Transition Time, Any Output VIL=0 V VIH=VCC tLH = tHL =6.0 ns СL = 50 pF 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 ns Input Capacitance (Pin 1 or Pin 19) 3.0 - 7.0 - - - - pF Input Capacitance (Pin 2-9 or Pin 11-18) 3.0 - 20.0 - - - - pF - 50 - - - - pF CI CI/O CPD VI=0 V or VСС ns * - VCC=3.3±0.3V tHL VCC tLH VCC 0.9 0.9 V1 0.1 0.1 tPHL VO GND RT DEVICE UNDER TEST CL RL tPLH 0.9 B (A) VI PULSE GENERATOR V1 0.9 V1 V1 0.1 0.1 tTHL tTLH Figure 1. Switching Waveforms VCC Termination resistance RT – should be equal to ZOUT of pulse generators Figure 2. Test Circuit 4 IN74LV640 N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 0.25 (0.010) M T L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 N 0.38 G K M H D NOTES: J Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° 1. Dimensions A and B do not include mold flash or protrusion. K 0.1 0.3 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side M 0.23 0.32 P 10 10.65 R 0.25 0.75 NOTES: for A; for B ‑ 0.25 mm (0.010) per side. 5