ISSI 61LV51216

ISSI
IS61LV51216
512K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 8, 10, and 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
®
MARCH 2005
DESCRIPTION
The ISSI IS61LV51216 is a high-speed, 8M-bit static RAM
organized as 525,288 words by 16 bits. It is fabricated using
ISSI's high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A data
byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV51216 is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
1
ISSI
IS61LV51216
®
TRUTH TABLE
I/O PIN
I/O0-I/O7
I/O8-I/O15
WE
CE
OE
LB
UB
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ICC
Read
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
I CC
Write
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
I CC
Mode
VDD Current
PIN CONFIGURATIONS
PIN DESCRIPTIONS
44-Pin TSOP (Type II)
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
A18
A14
A13
A12
A11
A10
A0-A18
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
IS61LV51216
®
PIN CONFIGURATIONS
48-Pin mini BGA (9mmx11mm)
1
2
3
4
5
PIN DESCRIPTIONS
6
A
LB
OE
A0
A1
A2
N/C
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VDD
E
VDD
I/O12
GND
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
NC
A0-A18
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VDD
Power
GND
Ground
1
2
3
4
5
6
7
8
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
–0.5 to VDD+0.5
V
VTERM
Terminal Voltage with Respect to GND
VDD
VDD Related to GND
–0.3 to +4.0
V
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
9
10
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
3
ISSI
IS61LV51216
®
OPERATING RANGE
Range
Ambient Temperature
VDD
0°C to +70°C
3.3V +10%, -5%
–40°C to +85°C
3.3V +10%, -5%
Commercial
Industrial
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VDD + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD
Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = Max.,
Com.
IOUT = 0 mA, f = fMAX Ind.
—
—
110
120
—
—
100
110
—
—
90
100
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
30
35
—
—
30
35
—
—
30
35
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
CE ≥ VDD – 0.2V,
Ind.
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
—
—
20
25
—
—
20
25
—
—
20
25
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
IS61LV51216
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
1
2
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
3
4
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
5
See Figures 1 and 2
6
AC TEST LOADS
7
319 Ω
ZO = 50Ω
1.5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1
8
3.3V
50Ω
OUTPUT
5 pF
Including
jig and
scope
9
353 Ω
10
11
Figure 2
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
5
ISSI
IS61LV51216
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-8
Min. Max.
Parameter
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2
tLZCE(2)
tBA
tHZB(2)
tLZB(2)
tPU
tPD
-10
Min. Max.
-12
Min. Max.
Unit
Read Cycle Time
8
—
10
—
12
—
ns
Address Access Time
—
8
—
10
—
12
ns
Output Hold Time
3
—
3
—
3
—
ns
CE Access Time
—
8
—
10
—
12
ns
OE Access Time
—
3.5
—
4
—
5
ns
OE to High-Z Output
—
3
—
4
0
5
ns
OE to Low-Z Output
0
—
0
—
0
—
ns
CE to High-Z Output
0
3
0
4
0
6
ns
CE to Low-Z Output
3
—
3
—
3
—
ns
LB, UB Access Time
—
3.5
—
4
—
5
ns
LB, UB to High-Z Output
0
3
0
3
0
4
ns
LB, UB to Low-Z Output
0
—
0
—
0
—
ns
Power Up Time
0
—
0
—
0
—
ns
Power Down Time
—
8
—
10
—
12
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
t AA
t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
IS61LV51216
®
READ CYCLE NO. 2(1,3)
1
tRC
ADDRESS
tAA
tOHA
2
tHZOE
3
OE
tDOE
CE
tLZOE
tACE
4
tHZCE
tLZCE
LB, UB
DOUT
VDD
HIGH-Z
tBA
tLZB
tHZB
tRC
5
DATA VALID
tPU
50%
Supply
Current
tPD
6
ICC
50%
ISB
UB_CEDR2.eps
7
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
7
ISSI
IS61LV51216
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
Unit
tWC
Write Cycle Time
8
—
10
—
12
—
ns
tSCE
CE to Write End
6.5
—
8
—
8
—
ns
tAW
Address Setup Time
to Write End
6.5
—
8
—
8
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
6.5
—
8
—
8
—
ns
tPWE1
WE Pulse Width
6.5
—
8
—
8
—
ns
tPWE2
WE Pulse Width (OE = LOW)
8.0
—
10
—
12
—
ns
tSD
Data Setup to Write End
5
—
6
—
6
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
ns
(2)
tHZWE
WE LOW to High-Z Output
—
3.5
—
5
—
6
ns
tLZWE(2)
WE HIGH to Low-Z Output
2
—
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write. Shaded area product in development
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
IS61LV51216
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
1
t WC
2
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
3
t AW
t PWE1
t PWE2
WE
4
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
5
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
6
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs
and at least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
9
ISSI
IS61LV51216
®
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
IS61LV51216
®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)
t WC
ADDRESS
(1,3)
1
t WC
ADDRESS 1
ADDRESS 2
2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
4
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
3
t HA
t HD
t SD
DATAIN
VALID
5
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
11
ISSI
IS61LV51216
®
ORDERING INFORMATION:
Commercial Range: 0°C to +70°C
Speed
(ns)
Order Part No.
Package
8
IS61LV51216-8T
IS61LV51216-8M
TSOP (Type II)
Mini BGA (9mm x 11mm)
10
IS61LV51216-10T
IS61LV51216-10M
TSOP (Type II)
Mini BGA (9mm x 11mm)
12
IS61LV51216-12T
TSOP (Type II)
Industrial Range: –40°C to +85°C
Speed
(ns)
12
Order Part No.
Package
8
IS61LV51216-8TI
IS61LV51216-8MI
TSOP (Type II)
Mini BGA (9mm x 11mm)
10
IS61LV51216-10TI
IS61LV51216-10TLI
IS61LV51216-10MI
TSOP (Type II)
TSOP (Type II), Lead-free
Mini BGA (9mm x 11mm)
12
IS61LV51216-12TI
TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
ISSI
PACKAGING INFORMATION
®
Mini Ball Grid Array
Package Code: M (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
D
5
4
3
2
1
A
e
B
B
C
C
D
D
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
A
SEATING PLANE
Notes:
1. Controlling dimensions are in millimeters.
A1
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
ISSI
PACKAGING INFORMATION
®
Mini Ball Grid Array
Package Code: M (48-pin)
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
.—
— 0.047
A1
0.25
—
0.40
0.010
— 0.016
A2
0.60
—
—
0.024
—
D
7.90 8.00 8.10
0.311 0.314 0.319
5.60BSC
0.220BSC
E
5.90 6.00 6.10
0.232 0.236 0.240
E1
4.00BSC
0.157BSC
e
0.80BSC
0.031BSC
D1
b
0.40
0.45
0.50
—
0.016 0.018 0.020
mBGA - 7.2mm x 8.7mm
mBGA - 9mm x 11mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
—
—
0.047
A
A1
0 .24
—
0.30
0.009
—
0.012
A1
A2
0.60
—
—
0.024
—
—
A2
D
8.60 8.70 8.80
D
10.90 11.00 11.10
0.429 0.433 0.437
5.25BSC
0.207BSC
D1
0.339 0.343 0.346
—
—
1.20
—
—
0.047
0.24
—
0.30
0.60
—
—
0.009
—
0.012
0.024
—
—
5.25BSC
0.207BSC
E
7.10 7.20 7.30
0.280 0.283 0.287
E
E1
3.75BSC
0.148BSC
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
e
0.75BSC
0.030BSC
0.012 0.014 0.016
b
b
2
0.30
0.35
0.40
D1
8.90
0.30
9.00
0.35
9.10
0.40
0.350 0.354 0.358
0.012 0.014 0.016
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
ISSI
®
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03