LG Semicon Co.,Ltd. REVISION HISTORY / Revision 1.0: July 1998 - Add PC100,7K(2-2-2) Specifications. - Update Icc Specifications. - Change Input Test Condition from 2.8/0.0V to 2.4/0.4V. - Added post SPD Information separately(7K/7J/10K) for Modules. - Add Minimum Capacitance Value for Component. Rev. 1.0 LG Semicon Co.,Ltd. Description The GM72V66841CT/CLT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841CT/CLT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 125 Mhz. Features * PC100,PC66 Compatible 7K(2-2-2), 7J(3-2-2), 10K(PC66) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 100/125 MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh/ Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit *JEDEC Standard 54Pin 400mil TSOP II Package GM72V66841CT/CLT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Pin Configuration VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Name CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ VCC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask VCC for DQ VSS for DQ Power for internal circuit Ground for internal circuit No Connection 1 LG Semicon GM72V66841CT/CLT Block Diagram A0 to A13 A0 to A8 A0 to A13 Column decoder Memory array Bank 3 4096 row x 512 column x 8 bit DQM Control logic & timing generator CAS Output buffer DQ0 to DQ7 2 4096 row x 512 column x 8 bit CKE Input buffer Bank 2 Sense amplifier & I/O bus 4096 row x 512 column x 8 bit Memory array RAS Bank 1 Row decoder CS Memory array Column decoder 4096 row x 512 column x 8 bit Refresh counter Row decoder Sense amplifier & I/O bus Bank 0 Column decoder Memory array Row decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Row decoder Row address counter WE Column address buffer CLK Column address counter LG Semicon GM72V66841CT/CLT Pin Description Pin Name DESCRIPTION CLK (input pin) CLK is the master Clock input to this pin. The other input signals are referred at CLK rising edge. CKE (input pin) This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for Power-down and Clock suspend modes. CS (input pin) When CS is Low, the command input cycle becomes valid. When CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins) Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 ~ A11 (input pins) Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address(AY0 to AY8; GM72V66841CT/CLT) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the Precharge mode. When A10 = High at the Precharge command cycle, all banks are Precharged. But when A10 = Low at the Precharge command cycle, only the bank that is selected by A12/A13 (BS) is Precharged. A12/A13 (input pin) DQM, DQMU/DQML (input pins) A12/A13 are bank select signal (BS). The memory array of the GM72V66841CT/CLT is divided into bank 0, bank 1, bank2 and bank 3. GM72V66841CT/CLT contain 4096-row x 512-column x 8-bits. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. DQM, DQMU/DQML controls input/output buffers. * Read operation: If DQM, DQMU/DQML is High, The output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. * Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. 3 LG Semicon GM72V66841CT/CLT Pin Description(Continued) Pin Name DESCRIPTION DQ0 ~ DQ7 (I/O pins) Data is input and output from these pins. These pins are the same as those of a conventional DRAM. VCC and VCCQ (Power supply pins) 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VSS and VSSQ (Power supply pins) Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) NC No Connection pins. Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. CKE n n-1 CS RAS CAS WE A12~ A13 A10 A0~ A11 X H X X X X X X H X L H H H X X X BST H X L H H L X X X READ H X L H L H V L V READ A H X L H L H V H V WRIT H X L H L L V L V Write with auto-Precharge WRIT A H X L H L L V H V Row address strobe and bank active ACTV H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X REF/SELF H V L L L H X X X MRS H X L L L L V V V Function Symbol Ignore command DESL H No Operation NOP Burst stop in full page Column address and read command Read with auto-Precharge Column address and write command Precharge select bank Precharge all banks Refresh Mode register set * Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input 4 LG Semicon Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignores command input at the Clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full page [BST] : This command stops a full-page burst operation (burst length = full-page(512;GM72V66841CT/CLT) and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for full-page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13). After the read operation, the output buffer becomes High-Z. Read with auto-Precharge [READ A]: This command automatically performs a Precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY8;GM72V66841CT/CLT) and the bank select address (A12/A13). GM72V66841CT/CLT Write with auto-Precharge [WRIT A]: This command automatically performs a Precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13(BS) and determines the row address (AX0 to AX11). If A12 is Low and if A13 is Low, bank 0 is activated. If A12 is High and A13 is Low, bank 1 is activated. If A12 is Low and A13 is High, bank 2 is activated. If A12 is High and A13 is High, bank 3 is activated. Precharge selected bank [PRE]: This command starts Precharge operation for the bank selected by A12/A13. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. Precharge all banks [PALL]: This command starts a Precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After Power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. 5 LG Semicon GM72V66841CT/CLT DQM Truth Table Function Symbol CKE n-1 n DQM Write enable/output enable ENB H X L Write inhibit/output disable MASK H X H * Notes : H: VIH, L: VIL, X: VIH or VIL. Write : lDID is needed. Read : lDOD is needed. The GM72V66841CT/CLT can mask input/output data by means of DQM. During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set to High, the output buffer becomes High-Z, disabling data output. 6 During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQM. For details, refer to the DQM control section of the GM72V66841CT/CLT operating instructions. LG Semicon GM72V66841CT/CLT CKE Truth Table Current State CKE Function n -1 n CS RAS CAS WE Address Active Clock suspend mode entry H L H X X X X Any Clock suspend L L X X X X X Clock Suspend Clock suspend mode exit L H X X X X X Idle Auto-refresh command (REF) H H L L L H X Idle Self-refresh entry (SELF) H L L L L H X Power down entry H L L H H H X Idle H L H X X X X L H L H H H X L H H X X X X L H L H H H X L H H X X X X Self refresh Power down Self refresh exit (SELFX) Power down Exit * Notes : H: VIH, L: VIL, X: VIH or VIL. Clock suspend mode entry: The synchronous DRAM enters Clock suspend mode from active mode by setting CKE to Low. The Clock suspend mode changes depending on the current status (1 Clock before) as shown below. ACTIVE Clock suspend: This suspend mode ignores inputs after the next Clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During Clock suspend mode, keep the CKE to Low. Clock suspend mode exit : The synchronous DRAM exits from Clock suspend mode by setting CKE to High during the Clock suspend state. IDLE: In this state, all banks are not selected, and completed Precharge operation. 7 LG Semicon GM72V66841CT/CLT Auto-refresh command[REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4,096 times are required to refresh the entire memory. Before executing the autorefresh command, all the banks must be in the IDLE state. In addition, since the Precharge for all banks is automatically performed after autorefresh, no Precharge command is required after auto-refresh. Self-refresh exit[SELFX]: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters Power down mode. In Power down mode, Power consumption is suppressed by cutting off the initial input circuit. Power down exit: When this command is executed at the Power down mode, the synchronous DRAM can exit from Power down mode. After exiting from Power down mode, the synchronous DRAM enters the IDLE state. Self-refresh entry[SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. 8 Current state CS RAS CAS WE Precharge H X X X X DESL Enter IDLE after tRP L H H H X NOP Enter IDLE after tRP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL NOP Address Command Operation LG Semicon GM72V66841CT/CLT Function Truth Table (Continued) Current state CS RAS CAS WE Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL NOP L L L H X REF, SELF Refresh L L L L MODE MRS Mode register set H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Idle Row active Address Command Operation ILLEGAL 9 LG Semicon GM72V66841CT/CLT Function Truth Table (Continued) Current state CS RAS CAS WE Read H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop to full page L H L H BA, CA, A10 READ/READ A Continue burst read to CAS latency and New read L H L L BA, CA, A10 WRIT/WRIT A L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Term burst read and Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and Precharge L H H H X NOP Continue burst to end and Precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Read with autoPrecharge 10 Address Command Operation Term burst read/start write LG Semicon GM72V66841CT/CLT Function Truth Table (Continued) Current state CS RAS CAS WE Write H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Term burst and New read L H L L BA, CA, A10 WRIT/WRIT A L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Term burst write and Precharge*2 L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and Precharge L H H H X NOP Continue burst to end and Precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Write with autoPrecharge Address Command Operation Term burst and New write 11 LG Semicon GM72V66841CT/CLT Function Truth Table (Continued) Current state Refresh (auto-refresh) CS RAS CAS WE Address Command Operation H X X X X DESL Enter IDLE after tRC L H H H X NOP Enter IDLE after tRC L H H L X BST Enter IDLE after tRC L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL * Notes : 1. H: VIH, L: VIL, X: VIH or VIL. The other combinations are inhibit. 2. An interval of tRWL is required between the final valid data input and the Precharge command. 3. If tRRD is not satisfied, this operation is illegal. 4. BA:Bank Address, RA:Row Address, CA:Column Address From [Precharge] To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of Precharge From [IDLE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. 12 From [ROW ACTIVE] To [PRE], [PALL]: These commands set the synchronous DRAM to Precharge mode. (However, an interval of tRAS is required.) LG Semicon From [READ] GM72V66841CT/CLT From [WRITE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters Precharge mode. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters Precharge mode. From [WRITE with AUTO-Precharge] From [READ with AUTO-Precharge] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [DESL], [NOP]: These commands continue write operations until the burst operation is completed, and the synchronous DRAM then enters Precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an autorefresh cycle (after tRC), the synchronous DRAM automatically enters the Idle state. 13 LG Semicon GM72V66841CT/CLT 64M SDRAM Function State Diagram E SR MRS MODE REGISTER SET ACTIVE IDLE Power DOWN ITE WR WRITE READ RE A WI D TH AP CKE=H WRITE WITH AP E RG HA EC PR WRITEA PRECHARGE CKE=L RE AD Read CKE=L READ WRITE READ SUSPEND CKE=H READ WITH AP ITE WR H AP T I W PR EC HA RG E TH AP TE WI RI BST (on full page) AP TH WI AD RE W CKE=L Power ON CKE =H ROW ACTIVE Write Power APPLIED *1 AUTOREFRESH REFRESH CK E= L BST (on full page) CKE=H IT EX SR CKE =L CK E= H WRITEA SUSPEND RY IDLE ACTIVE Clock SUSPEND WRITE SUSPEND NT SELFREFRESH CKE=L READA SUSPEND READA CKE=H PRECHARGE Precharge Automatic Transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, Precharge is performed automatically and enter the IDLE state. 14 LG Semicon GM72V66841CT/CLT Mode Register Configuration Burst read and SINGLE WRITE: The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: A13, A12, A11, A10, A9, A8: (OPCODE): Keep this bit Low at the mode register set cycle. The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): Burst read and BURST WRITE: A burst type is specified . When full-page burst is performed, only "sequential" can be selected. Burst write is performed for the specified burst length starting from the column address specified in the write cycle. A2, A1, A0: (BL): These pins specify the burst length. A13 A12 A11 A10 A9 A8 OPCODE A7 A6 0 A5 A4 LMODE A6 A5 A4 CAS Latency A3 A2 BT A1 A0 BL A3 Burst Type Burst Length A2 A1 A0 0 0 0 R 0 Sequential 0 0 1 R 1 0 1 0 0 1 1 X Interleave BT=0 BT=1 0 0 0 1 1 2 0 0 1 2 2 1 3 0 1 0 4 4 X R 0 1 1 8 8 1 0 0 R R 1 0 1 R R A13 A12 A11 A10 A9 A8 Write mode 1 1 0 R R 1 1 1 F.P. R 0 0 0 0 0 0 Burst read and BURST WRITE X X X X 0 1 R X X X X 1 0 Burst read and SINGLE WRITE X X X X 1 1 R F.P. = Full Page (512:GM72V66841CT/CLT) R is Reserved (inhibit) X: 0 or 1 15 LG Semicon GM72V66841CT/CLT Burst Sequence Burst Length 2 4 8 Starting Column Address A2 A1 A0 Sequential Interleave V V 0 0 - 1 0 - 1 V V 1 1 - 0 1 - 0 V 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 V 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 V 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 V 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 * Notes : V : Valid Address 16 Addressing(decimal) LG Semicon GM72V66841CT/CLT Operation of GM72V661641CT/CLT, GM72V66841CT/CLT, GM72V66441CT/CLT Series Read / Write Operation Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. GM72V66841CT/CLT can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full page(512;GM72V66841CT/CLT). The start address for a burst read is specified by the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (512;GM72V66841CT/CLT) data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register. CAS Latency CLK tRCD Command ACTV READ Address Row Column CL = 2 out 0 out 1 out 2 out 3 out 0 out 1 out 2 Dout CL = 3 out 3 CL : CAS Latency Burst Length = 4 17 LG Semicon GM72V66841CT/CLT Burst Length CLK tRCD Command Address Active Read Row Column out 0 BL = 1 out 0 out 1 BL = 2 out 0 out 1 out 2 out 3 Dout BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 0-1 out 0 out 1 BL = Full Page BL = Burst Length CAS Latency = 2 Write Operation Burst write or single write mode is selected by the OPCODE(A13, A12,A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE(A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8 and full page, like burst read operations. The write start address is specified by the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) at the write command set cycle. 18 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY8; GM72V66841CT/CLT) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.) LG Semicon GM72V66841CT/CLT Burst Write CLK tRCD Command ACTV WRIT Address Row Column in 0 BL = 1 in 0 in 1 in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 BL = 2 Din BL = 4 BL = 8 in 8 in 9 in 10 in 11 in 0-1 in 0 in 1 BL = Full Page CAS Latency = 2, 3 Single Write CLK tRCD Command ACTV WRIT Address Row Column Din in 0 19 LG Semicon GM72V66841CT/CLT Auto Precharge Read with auto-Precharge: In this operation, since Precharge is automatically performed after completing a read operation, a Precharge command need not be executed after each read operation. CAS Latency The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command. Precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output Burst Read with Auto-Precharge CLK CL=2 Command READ ACTV out 0 Dout out 1 out 2 out 3 lAPR CL=3 Command Dout READ ACTV out 0 out 1 out 2 out 3 lAPR Note : Internal auto-Precharge starts at the timing indicated by " " At CLK=50MHz (lAPR changes depending on the operating frequency.) 20 LG Semicon GM72V66841CT/CLT Write with auto-Precharge: In this operation, since Precharge is automatically performed after completing a burst write or single write operation, a Precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of the next command. Burst Write (Burst Length = 4) CLK Command WRIT DQ(input) in 0 ACTV in 1 in 2 in 3 lAPW Single Write CLK Command WRIT DQ(input) in ACTV lAPW 21 LG Semicon GM72V66841CT/CLT Full-page Burst Stop The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4, and 8. Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. CAS Latency BST to valid data BST to high impedance 2 1 2 3 2 3 CAS Latency=2, Burst Length = full page CLK BST Command out DQ(output) out out out out out lBSH = 2 cycle lBSR = 1 cycle CAS Latency = 3, Burst Length = full page CLK BST Command DQ(output) out out out out out out out lBSH = 3 cycle lBSR = 2 cycle 22 LG Semicon GM72V66841CT/CLT Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command, and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4, and 8. And an interval of tRWL is required between the last data-in and the next Precharge command. Burst Length = full page CLK BST Command DQ(output) in PRE/PALL in tRWL lBSW = 0 cycle 23 LG Semicon GM72V66841CT/CLT Command Intervals Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. READ to READ Command Interval (Same Row Address in Same Bank) CLK Command ACTV Address (A0-A11) Row READ READ Column A Column B BS(A12/A13) out A0 Dout Bank0 Active Column=A Column=B Read Read out B0 out B1 out B2 Column=A Column=B Dout Dout out B3 CAS Latency =3 Burst Length = 4 Bank0 2. Same bank, different ROW address: 3. Different bank: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a Precharge command and a bank-active command. When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. 24 LG Semicon GM72V66841CT/CLT READ to READ Command Interval (different bank) CLK Command ACTV ACTV READ READ Address (A0-A11) Row 0 Row 1 Column A Column B BS(A12/A13) Dout Bank0 Active Bank3 Bank0 Active Read Bank3 Read out A0 out B0 Bank0 Dout Bank3 Dout out B1 out B2 out B3 CAS Latency = 3 Burst Length = 4 25 LG Semicon GM72V66841CT/CLT Command Intervals Write command to Write command interval: In the case of burst writes, the second write command has priority. 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. WRITE to WRITE Command Interval (same ROW address in same bank) CLK Command ACTV WRIT WRIT Address (A0-A11) Row Column A Column B in A0 in B0 BS(A12/A13) Din Bank0 Active in B1 in B2 in B3 Burst Write Mode Burst Length = 4 Bank0 Column=A Column=B Write Write 2. Same bank, different ROW address: 3. Different bank: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two write commands with a Precharge command and a bank-active command. When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. In the case of burst write, the second write command has priority. 26 LG Semicon GM72V66841CT/CLT WRITE to WRITE Command Interval (different bank) CLK Command ACTV ACTV WRIT WRIT Address (A0-A11) Row 0 Row 1 Column A Column B BS(A12/A13) Din in A0 Bank0 Active Bank3 Bank0 Active Write in B0 in B1 in B2 in B3 Burst Write Mode Burst Length = 4 Bank3 Write Read command to Write command interval: 1. Same bank, same Row address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQM, DQMU/DQML must be set High-Z so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CLK Command DQM, DQMU /DQML READ WRIT CL=2 CL=3 Din Dout in B0 in B1 in B2 in B3 High-Z Burst Length = 4 Burst Write 27 LG Semicon GM72V66841CT/CLT READ to WRITE Command Interval (2) CLK Command READ DQM, DQMU /DQML CL=2 WRIT 2 Clock High-Z Dout CL=3 High-Z Din 2. Same bank, different ROW address: 3. Different bank: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a Precharge command or a bank-active command. When the bank changes, the write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bankactive state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. 28 LG Semicon GM72V66841CT/CLT Write Command to Read Command Interval: However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. 1. Same bank, same Row address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the write command can be performed after an interval of no less than 1 cycle. WRITE to READ Command Interval (1) CLK Command WRIT READ DQM, DQMU/DQML Din in A0 out B0 Dout out B1 out B2 out B3 CAS Latency Column=A Write Column=B Read Burst Write Mode CAS Latency=2 Burst Length = 4 Bank0 Column=B Dout WRITE to READ Command Interval (2) CLK Command WRIT READ DQM, DQMU/DQML Din in A0 in A1 out B0 Dout out B1 out B2 out B3 CAS Latency Column=A Write Column=B Read Column=B Dout Burst Write Mode CAS Latency=2 Burst Length = 4 Bank0 29 LG Semicon GM72V66841CT/CLT 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a Precharge command and a bank-active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed(as in the case of the same bank and the same address). Read command to Precharge interval (same bank): When the Precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the Precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to Precharge command execution. READ to Precharge Command Interval (same bank) : To output all data CAS Latency = 2, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 out A1 out A2 out A3 lEP = -1 Cycle CL=2 CAS Latency = 3, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 CL=3 30 out A1 out A2 lEP = -2 Cycle out A3 LG Semicon GM72V66841CT/CLT READ to Precharge Command Interval (same bank) : To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High - Z out A0 Dout lHZP=2 CAS Latency = 3, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High - Z Dout out A0 IHZP=3 31 LG Semicon GM72V66841CT/CLT Write Command to Precharge Command Interval (same bank): When the Precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. However, if the burst write operation is unfinished, the input data must be masked by means of DQM, DQMU/DQML for assurance of the cycle defined by tRWL. Burst Length = 4 ( To stop write operation) CLK Command WRIT PRE/PALL DQM, DQMU/DQML Din tRWL CLK Command WRIT PRE/PALL DQM, DQMU/DQML Din in A0 in A1 tRWL Burst Length = 4 (To write all data) CLK Command WRIT PRE/PALL DQM, DQMU/DQML Din in A0 in A1 in A2 in A3 tRWL 32 LG Semicon GM72V66841CT/CLT Bank Active Command Interval 2. In the case of different bank-active commands: The interval between the bankactive commands must be no less than tRRD. 1. Same bank: The interval between the two bank-active commands must be no less than tRC. Bank Active to Bank Active Command Interval for Same Bank CLK Command ACTV ACTV Address (A0-A11) ROW ROW BS(A12/A13) tRC Bank 0 Active Bank 0 Active Bank Active to Bank Active for different bank CLK Command ACTV ACTV Address (A0-A11) ROW:0 ROW:1 BS(A12/A13) tRRD Bank 0 Active Bank 3 Active 33 LG Semicon GM72V66841CT/CLT Mode Register Set to Bank-Active Command Interval : The interval between setting the mode register and executing a bank-active command must be no less than tRSA. CLK Command MRS ACTV Address (A0-A13) CODE BS & ROW tRSA Mode Register Set Bank Active DQM Control (GM72V661641CT/CLT) DQM Control The DQMU and DQML mask the upper and lower bytes of DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. (GM72V66841CT/CLT,GM72V66441CT) Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2. Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0. 34 The DQM mask DQ data. The timing of DQM is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2. Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0. LG Semicon GM72V66841CT/CLT Reading CLK DQM, DQMU/DQML DQ (input) out 0 High-Z out 1 out 3 lDOD = 2 Latency Writing CLK DQM, DQMU/DQML DQ (input) in 0 in 1 in 3 lDID = 0 Latency 35 LG Semicon GM72V66841CT/CLT Refresh Clock suspend (Active Power down) mode: Auto refresh: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters Clock suspend mode. During Clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates Clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". All the banks must be Precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4,096 cycles/64ms. (4,096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-Z after auto-refresh start. In addition, since a Precharge has been completed by an internal operation after the auto-refresh, an additional Precharge operation by the Precharge command is not required. Self refresh: After executing a self-refresh command, the selfrefresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a selfrefresh exit command. If you use distributed auto-refresh mode with 15.6us interval in normal read/write cycle, auto-refresh should be executed within 15.6 us immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6us interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power down mode: The synchronous DRAM enters Power down mode when CKE goes Low in the IDLE state. In Power down mode, Power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the Power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. 36 Power-up sequence: During Power-up sequence, the DQM and the CKE must be set to High. When 200§Á has past after Power on, all banks must be Precharged using the Precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. LG Semicon GM72V66841CT/CLT Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT -0.5 to Vcc+0.5 (<= 4.6 (max)) V 1 Supply voltage relative to VSS VCC -0.5 to +4.6 V 1 Short circuit output current IOUT 50 mA PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Power dissipation Notes : 1. Respect to VSS Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Symbol Min Max Unit Note VCC, VCCQ 3.0 3.6 V 1 VSS, VSSQ 0 0 V Input high voltage VIH 2.0 Vcc + 0.3 V 1, 2 Input low voltage VIL -0.3 0.8 V 1,3 Supply voltage Notes : 1. All voltage referred to VSS. 2. VIH (max) = 4.6V for pulse width <= 5ns 3. VIL (min) = -1.5V for pulse width <= 5ns 37 LG Semicon GM72V66841CT/CLT DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) - 7K - 7J -8 - 10K Max Max Max Max ICC1 80 80 80 70 mA ICC2P 2 2 2 2 mA 2 2 2 2 Parameter Symbol Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) Active standby current in power down ICC2PS 0.4 0.4 0.4 0.4 15 15 15 15 mA 10 10 10 10 5 5 5 5 6 6 6 6 ICC3P Active standby current in power down ICC3PS (input signal stable) Active standby current in non power down mA ICC2N ICC2NS Unit Test conditions Notes 5 5 5 5 5 5 5 5 4 4 4 30 30 30 30 ICC3N 25 25 25 25 Active standby current in non power down ICC3NS (input signal stable) 20 20 20 20 10 10 10 10 Burst operating current CKE=VIL, tCK= Infinity CKE,CS = VIH, tCK = 12ns mA CKE = VIH, tCK = Infinity mA CKE = VIL, tCK = 12 ns, DQ = High-Z mA 4 Burst length= 1 tRC = min CKE = VIL, tCK = 12 ns CKE = VIL, tCK = Infinity 1, 2, 3 5 6 6,8 4 4,8 4 1,2,5 1,2,5,8 2,6 2,6,8 mA CKE,CS = VIH, 1,2,4 tCK = 12 ns, 1,2,4,8 DQ = High-Z mA CKE = VIH, tCK = Infinity 2,9 2,8,9 ( CL= 2 ) ICC4 120 80 100 80 mA tCK = min ( CL= 3 ) ICC4 120 120 155 120 mA BL = 4 Refresh current ICC5 110 110 110 90 mA tRC = min 3 1 1 1 1 ICC6 mA VIH >=VCC - 0.2 VIL <=.2V 7 Self refresh current 0.4 38 0.4 0.4 0.4 1,2,3 7,8 LG Semicon GM72V66841CT/CLT Parameter Symbol Input leakage current - 7K, -7J, -8, -10K Unit Test conditions Notes Min Max ILI -1 1 uA 0<=Vin <=VCC Output leakage current ILO -1.5 1.5 uA 0<=Vout <=VCC DQ = disable Output high voltage VOH 2.4 - V IOH = -2 mA Output low voltage VOL - 0.4 V IOL =2 mA Notes : 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. L-Version. 9. Input signals are VIH or VIL fixed. Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V +/- 0.3 V) Parameter Symbol Min. Max. Unit Notes Input capacitance (CLK) CI1 2.5 4 pF 1, 3, 4 Input capacitance (Signals) CI2 2.5 5 pF 1, 3, 4 Output capacitance (DQ) CO 4.0 6.5 pF 1, 2, 3, 4 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM, DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. 4. Measured with 1.4 V bias and 200mV swing at the pin under measurement. 39 LG Semicon GM72V66841CT/CLT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) Parameter Symbol - 7K - 7J -8 - 10K Min Max Min Max Min Max Min Max tCK tCK tCKH tCKL tAC tAC tOH 10 - 15 - 12 - 15 - 10 - 10 - 8 - 10 - 3 - 3 - 3 - 3 3 - 3 - 3 - - 6 - 8 - - 6 - 6 3 - 3 tLZ 2 - tHZ - tDS tDH tAS tAH tCES CKE setup time for power down exit System clock cycle time (CL=2) Unit Notes ns 1 - ns 1 3 - ns 1 8 - 9 ns 1, 2 - 6 - 8 - 3 - 3 - ns 1, 2 2 - 2 - 2 - ns 1, 2, 3 6 - 6 - 6 - 7 ns 1, 4 2 - 2 - 2 - 2 - ns 1 1 - 1 - 1 - 1 - ns 1 2 - 2 - 2 - 2 - ns 1 1 - 1 - 1 - 1 - ns 1 2 - 2 - 2 - 2 - ns 1, 5 tCESP 2 - 2 - 2 - 2 - ns 1 CKE hold time tCEH 1 - 1 - 1 - 1 - ns 1 Command (CS, RAS, CAS, WE, DQM) setup time tCS 2 - 2 - 2 - 2 - ns 1 Command (CS, RAS, CAS, WE, DQM) hold time tCH 1 - 1 - 1 - 1 - ns 1 tRC 70 - 70 - 72 - 90 - ns 1 tRAS 50 120000 50 120000 48 120000 60 120000 ns 1 tRCD 20 - 20 - 24 - 30 - ns 1 tRP 20 - 20 - 24 - 30 - ns 1 (CL=3) CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period 40 LG Semicon GM72V66841CT/CLT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) (Continued) Parameter Symbol Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period - 7K - 7J -8 - 10K Unit Notes Min Max Min Max Min Max Min Max tRWL 10 - 10 - 10 - 15 - ns 1 tRRD 20 - 20 - 16 - 20 - ns 1 tT 1 5 1 5 1 5 1 5 ns tREF - 64 - 64 - 64 - 64 ms Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V. 2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination. 3. tLZ (min)defines the time at which the outputs achieves the low impedance state. 4. tHZ (max)defines the time at which the outputs achieves the high impedance state. 5. tCES define CKE setup time to CKE rising edge except Power down exit command. Test Condition - Input and output-timing reference levels: 1.4V - Input waveform and output load: See following figures I/O input 2.4V 80% 0.4V 20% OPEN CL tT tT 41 LG Semicon GM72V66841CT/CLT Relationship Between Frequency and Minimum Latency - 7K Parameter frequency(MHz) Symbol Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command CS to command disable Power down exit to command input 42 -8 - 10K Notes 100 100 66 125 83 100 66 10 10 15 8 12 10 15 lRCD 2 2 2 3 2 3 2 1 lRC 7 7 6 9 6 9 6 = [lRAS +lRP], 1 lRAS 5 5 4 6 4 6 4 1 lRP 2 2 2 3 2 3 2 1 lRWL 1 1 1 2 1 1 1 1 lRRD 2 2 2 2 2 2 2 1 lSREX 1 1 1 1 1 1 1 lAPW 3 3 3 5 3 4 3 = [lRWL +lRP], 1 lSEC 9 9 6 9 6 9 6 = [lRC] lHZP lHZP 2 - 2 - 2 - 2 3 3 3 3 3 3 3 lAPR 1 1 1 1 1 1 1 lEP lEP -1 - -1 - -1 - -1 -2 -2 -2 -2 -2 -2 -2 lCCD 1 1 1 1 1 1 1 lWCD 0 0 0 0 0 0 0 lDID lDOD lCLE lRSA lCDD 0 0 0 0 0 0 0 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 lPEC 1 1 1 1 1 1 1 tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) - 7J LG Semicon GM72V66841CT/CLT Relationship Between Frequency and Minimum Latency - 7K Parameter frequency(MHz) Symbol (CL=2) (CL=3) (CL=2) (CL=3) Burst stop to write data ignore -8 - 10K 100 100 66 125 83 100 66 10 10 15 8 12 10 15 1 - 1 - 1 - 1 2 2 2 2 2 2 2 2 - 2 - 2 - 2 3 3 3 3 3 3 3 0 0 0 0 0 0 0 tCK (ns) Burst stop to output valid data hold Burst stop to output high impedance - 7J lBSR lBSR lBSH lBSH lBSW Notes Notes : 1. lRCD to lRRD are recommended value. 43 LG Semicon Timing Waveforms GM72V66841CT/CLT Read Cycle tCK tCKH tCKL CLK tRC CKE VIH tRAS tCS tCH tRCD tRP tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH CS RAS CAS WE A12/A13 A10 tAS tAH . Address tCS tCH DQM , DQMU/DQML DQ(input) tAC tAC tAC tAC tHZ tOH tOH DQ(output) tLZ Bank0 Active Bank0 Read tOH tOH Bank0 Precharge CAS Latency = 2 Burst Length = 4 Bank0 Access = VIH or VIL 44 LG Semicon Write Cycle GM72V66841CT/CLT tCK tCKH tCKL CLK tRC CKE VIH tRAS tCS tCH tRCD tRP tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tCS tCH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH tAS tAH CS RAS CAS WE A12/A13 A10 tAS tAH . Address tCS tCH DQM , DQMU/DQML tDS tDH tDS tDH tDS tDH tDS tDH DQ(input) tRWL DQ(output) Bank0 Active Bank0 Write Bank0 Precharge CAS Latency = 2 Burst Length = 4 Bank0 Access = VIH or VIL 45 LG Semicon Mode Register Set Cycle 0 1 GM72V66841CT/CLT 2 3 4 5 6 7 8 9 10 11 12 13 14 b+3 b 15 16 17 18 CLK VIH CKE CS RAS CAS WE A12/A13 Address code R:b valid . C:b C:b DQM , DQMU/DQML DQ(output) b DQ(input) High - Z tRP Precharge if needed tRSA Mode Bank3 Register Active Set . b+1 . b+2 . b+3 . tRCD Bank3 Read Output Mask tRCD=3 CAS Latency=3 Burst Length=4 = VIH or VIL 46 LG Semicon Read Cycle/ Write Cycle 0 CLK CKE 1 GM72V66841CT/CLT 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 . b . b+1 18 19 20 VIH CS RAS CAS WE A12/A13 Address R:a C:a R:b . C:b C:b .. C:b DQM , DQMU/DQML DQ(output) a a+1 a+2 a+3 DQ(input) b b+1 b+2 b+3 .. .. .. .. b b+1 b+2 b+3 High-Z Bank0 Active Bank0 Read Bank3 Active Bank3 Bank0 Read Precharge Bank3 Read Bank3 Read Bank3 Precharge Read Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL VIH CKE CS RAS CAS WE A12/A13 Address R:a C:a R:b .. C:b . C:b C:b DQM , DQMU/DQML DQ(output) High-Z DQ(input) Bank0 Active a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Write Bank3 Active Bank3 Write Bank0 Precharge . b Bank3 Write . b+1 .. .. .. .. b b+1 b+2 b+3 Bank3 Write Bank3 Precharge Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL 47 LG Semicon Read / Single Write Cycle 0 1 2 GM72V66841CT/CLT 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a a+1 a+2 a+3 19 20 CLK VIH CKE CS RAS CAS WE A12/A13 Address R:a C:a . C:a C:a R:b DQM , DQMU/DQML DQ(input) a DQ(output) a Bank0 Active CKE Bank0 Read a+1 a+2 a+3 Bank3 Active Bank0 Bank0 Write Read Bank0 Bank3 Precharge Precharge VIH CS RAS CAS WE A12/A13 Address R:a C:a R:b C:a C:b C:c DQM , DQMU/DQML DQ(input) a DQ(output) a Bank0 Active Bank0 Read Bank3 Active a+1 b c a+3 Bank0 Write Bank0 Bank0 Write Write Bank0 Precharge Read/Single Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL 48 LG Semicon Read / Burst Write Cycle 0 1 2 GM72V66841CT/CLT 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A12/A13 Address R:a C:a R:b C:a .. DQM , DQMU/DQML DQ(input) a DQ(output) a Bank0 Active CKE Bank0 Read Bank3 Active C:a R:b a+1 a+2 a+1 a+2 a+3 a+3 Clock Suspend Bank0 Bank3 Precharge Precharge Bank0 Write VIH CS RAS CAS WE A12/A13 Address R:a .. C:a DQM , DQMU/DQML DQ(input) a DQ(output) a Bank0 Active Bank0 Read Bank3 Active a+1 a+1 a+2 a+3 a+3 Bank0 Write Bank0 Precharge Read/Burst Write RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL 49 LG Semicon Full Page Read / Write Cycle GM72V66841CT/CLT CLK CKE VIH CS RAS CAS WE A12/A13 Address R:a C:a .. R:b DQM , DQMU/DQML DQ(output) a a+1 a+2 a+3 a-2 a-1 a . . .. .. a+1 a+2 a+3 a+4 a+5 High-Z DQ(input) Bank0 Active Bank0 Read Burst Stop Bank3 Active Bank3 Precharge Read Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL CKE VIH CS RAS CAS WE A12/A13 Address R:a C:a .. R:b DQM , DQMU/DQML DQ(input) a a+1 a+2 a+3 a+4 a+5 a+6 High-Z DQ(output) Bank0 Active Bank0 Write Bank3 Active . a+1 a+2 a+3 a+4 a+5 . . .. .. .. .. . .. .. .. .. Burst Stop Bank1 Precharge Write Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL 50 LG Semicon Auto Refresh Cycle 0 GM72V66841CT/CLT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK VIH CKE CS RAS CAS WE A12/A13 Address R:a A10=h C:a DQM , DQMU/DQML DQ (input) DQ (output) High-Z tRP Precharge if needed tRC Auto Refresh tRC Auto Refresh Bank0 Active Bank0 Read Refresh Cycle and Read Cycle RAS-CAS Delay=2 CAS Latency=2 Burst Length=4 = VIH or VIL 51 LG Semicon Self Refresh Cycle GM72V66841CT/CLT CLK CKE CKE Low CS RAS CAS WE A12/A13 Address A10=h DQM , DQMU/DQML High-Z DQ tRP Precharge Command if needed Self Refresh Entry Command tRC Self Refresh Exit Ignore Command of No Operation tRC Next Self Refresh Clock Entry Command Enable Next Auto Clock Refresh Enable Self Refresh Cycle RAS-CAS Delay = 3 CAS Latency=3 Burst Length=4 = VIH or VIL 52 LG Semicon Clock Suspend (Active Power Down) Mode 0 1 2 3 4 5 6 7 GM72V66841CT/CLT 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A12/A13(BS) Address R:a C:a R:b C:b DQM , DQMU/DQML a DQ(output) a+1 a+2 DQ(input) a+3 b b+1 b+2 b+3 High-Z Bank3 Bank0 Bank3 Read Suspend Read Precharge Active Start Read Suspend End Active Clock Suspend End Bank0 Active Clock Active Suspend Start Bank0 Read Earliest Bank3 Precharge Read Cycle , RAS-CAS Delay=2 CAS Latency=2 , Burst Length=4 = VIH or VIL CKE CS RAS CAS WE A12/A13(BS) Address R:a C:a R:b C:b DQM , DQMU/DQML High-Z DQ(output) a DQ(input) Bank0 Active Active Clock Suspend Start a+1 a+2 a+3 Bank0 Bank3 Write Suspend Write Active Start Active Clock Suspend End b b+1 b+2 b+3 Bank3 Bank0 Write Precharge Earliest Bank3 Precharge Write Suspend End Write Cycle , RAS-CAS Delay=2 CAS Latency=2 , Burst Length=4 = VIH or VIL 53 LG Semicon Power Down Mode GM72V66841CT/CLT CLK CKE Low CKE CS RAS CAS WE A12/A13(BS) Address R:a A10=1 DQM , DQMU/DQML DQ(input) DQ(output) High-Z tRP Precharge Command if needed Power Down Entry Power Down Mode Exit Active Bank 0 Power Down Cycle RAS-CAS Delay=3 CAS Latency=3 Burst Length=4 = VIH or VIL 54 LG Semicon Power Up Sequence GM72V66841CT/CLT 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 CLK CKE VIH CS RAS CAS WE Address DQM , DQMU/DQML code Valid Valid VIH DQ High-Z tRP All banks Precharge tRC Auto Refresh tRC Auto Refresh tRSA Mode Register Set Bank Active if needed 55 LG Semicon GM72V66841CT/CLT Package Dimensions GM72V66841CT/CLT Series (TTP-54D) Unit: (mm) Preliminary 22.22 22.72 Max 28 10.16 54 0.80 1 +0.10 - 0.05 0.30 0.28+/- 0.05 27 0.13 M 0.80 11.76+/- 0.20 0.91 MAX Dimension including the plating thickness Base material dimension 56 0.50+/- 0.10 Hitachi Code TTP-54D JEDEC Code - EIAJ Code - Weight(reference value) 0.53g 0.68 0.13+/- 0.05 0.125+/- 0.04 0.10 0.145+/- 0.05 1.20 MAX 0~5