ELPIDA HB52RD328DC-A6F

HB52RD328DC-F
EO
256 MB Unbuffered SDRAM S.O.DIMM
32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module
(32 pcs of 16 M × 4 components)
PC100 SDRAM
L
Description
E0111H10 (1st edition)
(Previous ADE-203-1044B (Z))
Feb. 28, 2001
Note:
Pr
The HB52RD328DC is a 16M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory
Module (S.O.DIMM), mounted 32 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP package and 1
piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin Zig
Za g Dua l tabs socke t type compa ct and thin pac kage . The ref ore, it make s high density mounting possible
without surf ace mount tec hnology. It provide s common data inputs and outputs. De coupling ca pac itor s ar e
mounted beside TCP on the module board.
Do not push the cove r or drop the modules in orde r to prote ct fr om mec hanica l def ec ts, which would
be electrical defects.
uc
od
Features
• Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
⎯ Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
⎯ Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
t
This Product became EOL in October, 2005.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52RD328DC-F
L
EO
• 2 variations of burst sequence
⎯ Sequential (BL = 1/2/4/8/full page)
⎯ interleave (BL = 1/2/4/8)
• Programmable CE latency : 2/3 (HB52RD328DC-A6F/A6FL)
: 3 (HB52RD328DC-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
• Low self refresh current: HB52RD328DC-A6FL/B6FL (L-version)
• Full page burst length capability
⎯ Sequential burst
⎯ Burst stop capability
Ordering Information
Pr
Type No.
Frequency
CE latency
Package
Contact pad
HB52RD328DC-A6F
HB52RD328DC-B6F
HB52RD328DC-A6FL
HB52RD328DC-B6FL
100
100
100
100
2/3
3
2/3
3
Small outline DIMM (144-pin)
Gold
MHz
MHz
MHz
MHz
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Data Sheet E0111H10
2
HB52RD328DC-F
Pin Arrangement
EO
Front Side
1pin
59pin
61pin
143pin
2pin
60pin
62pin
144pin
L
Front side
Back Side
Back side
Signal name Pin No.
Signal name Pin No.
Signal name
1
VSS
73
NC
2
VSS
74
CK1
3
DQ0
75
VSS
4
DQ32
76
VSS
5
DQ1
77
NC
6
DQ33
78
NC
7
DQ2
79
NC
8
DQ34
80
NC
9
DQ3
81
VCC
10
DQ35
82
VCC
11
VCC
83
DQ16
12
VCC
84
DQ48
13
DQ4
85
DQ17
14
DQ36
86
DQ49
15
DQ5
87
DQ18
16
DQ37
88
DQ50
17
DQ6
89
DQ19
18
DQ38
90
DQ51
19
DQ7
91
VSS
20
DQ39
92
VSS
21
VSS
93
DQ20
22
VSS
94
DQ52
23
DQMB0
95
DQ21
24
DQMB4
96
DQ53
25
DQMB1
97
DQ22
26
DQMB5
98
DQ54
27
VCC
99
DQ23
28
VCC
100
DQ55
29
A0
101
VCC
30
A3
102
VCC
31
A1
103
A6
32
A4
104
A7
33
A2
105
A8
34
A5
106
A13 (BA0)
35
VSS
107
VSS
36
VSS
108
VSS
37
DQ8
109
A9
38
DQ40
110
A12 (BA1)
39
DQ9
111
A10 (AP)
40
DQ41
112
A11
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Signal name Pin No.
Pr
Pin No.
Data Sheet E0111H10
3
HB52RD328DC-F
Front side
Back side
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
41
DQ10
113
VCC
42
DQ42
114
VCC
43
DQ11
115
DQMB2
44
DQ43
116
DQMB6
45
VCC
117
DQMB3
46
VCC
118
DQMB7
47
DQ12
119
VSS
48
DQ44
120
VSS
49
DQ13
121
DQ24
50
DQ45
122
DQ56
51
DQ14
123
DQ25
52
DQ46
124
DQ57
53
DQ15
125
DQ26
54
DQ47
126
DQ58
55
VSS
127
DQ27
56
VSS
128
DQ59
57
NC
59
NC
61
CK0
63
VCC
65
L
EO
Pin No.
VCC
58
NC
130
VCC
131
DQ28
60
NC
132
DQ60
133
DQ29
62
CKE0
134
DQ61
135
DQ30
64
VCC
136
DQ62
RE
137
DQ31
66
CE
138
DQ63
67
W
139
69
S0
141
71
S1
143
Pr
129
VSS
68
CKE1
140
VSS
SDA
70
NC
142
SCL
VCC
72
NC
144
VCC
t
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Data Sheet E0111H10
4
HB52RD328DC-F
Pin Description
EO
Pin name
Function
A0 to A11
Address input
⎯ Row address
A0 to A11
⎯ Column address
A0 to A9
Bank select address
DQ0 to DQ63
Data-input/output
S0/S1
Chip select
RE
Row address asserted bank enable
CE
Column address asserted
W
DQMB0 to DQMB7
CK0/CK1
BA1, BA0
L
A12/A13
Write enable
Byte input/output mask
Clock input
Clock enable
SDA
Data-input/output for serial PD
SCL
VCC
VSS
NC
Pr
CKE0/CKE1
Clock input for serial PD
Power supply
Ground
No connection
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Data Sheet E0111H10
5
HB52RD328DC-F
Serial PD Matrix*1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits 0
0
0
0
1
1
0
0
0C
12
4
Number of column addresses
bits
0
0
0
0
1
0
1
0
0A
10
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
0
1
0
0
0
0
0
0
40
64
7
Module data width (continued) 0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels 0
0
0
0
0
0
0
1
01
LVTTL
9
L
EO
Byte No. Function described
SDRAM cycle time
(highest CE latency)
10 ns
0
1
0
0
0
0
0
A0
CL = 3
*7
10
SDRAM access from Clock
(highest CE latency)
6 ns
11
Module configuration type
12
Refresh rate/type
13
1
Pr
0
1
1
0
0
0
0
0
60
CL = 3
*7
0
0
0
0
0
0
0
0
00
Non parity
1
0
0
0
0
0
0
0
80
Normal
(15.625 µs)
Self refresh
SDRAM width
0
0
0
14
Error checking SDRAM width
0
0
0
15
0
SDRAM device attributes:
minimum clock delay for backto-back random column
addresses
0
0
16
SDRAM device attributes:
Burst lengths supported
1
0
0
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
18
SDRAM device attributes:
CE latency
0
0
0
19
SDRAM device attributes:
S latency
0
0
0
0
1
0
0
04
16M × 4
0
0
0
0
0
00
—
0
0
0
0
1
01
1 CLK
0
1
1
1
1
8F
1, 2, 4, 8, full
page
0
0
1
0
0
04
4
0
0
1
1
0
06
2, 3
0
0
0
0
1
01
0
t
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0
Data Sheet E0111H10
6
HB52RD328DC-F
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00
Non buffer
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
*7
1
1
1
1
0
0
0
0
F0
0
1
1
0
0
0
0
0
60
L
EO
Byte No. Function described
(-B6F/B6FL) 15 ns
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
(-B6F/B6FL) 8 ns
1
0
0
0
0
0
0
0
80
CL = 2
*7
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock (3rd 0
highest CE latency)
Undefined
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on
module
0
0
1
0
0
0
0
0
20
2 bank
128M byte
32
Address and command signal 0
input setup time
0
1
0
0
0
0
0
20
2 ns*7
33
Address and command signal 0
input hold time
0
0
1
0
0
0
0
10
1 ns*7
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns*7
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns*7
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6F/A6FL)
0
0
0
1
0
0
1
1
13
19
1
0
0
0
0
0
1
1
83
131
Manuf act urer’s J EDEC I D c ode 0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manuf act urer’s J EDEC I D c ode 0
0
0
0
0
0
0
0
00
64
t
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od
(-B6F/B6FL)
Pr
25
Data Sheet E0111H10
7
HB52RD328DC-F
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
72
Manufacturing location
×
×
×
×
×
×
×
×
××
* 3 (ASCII-8bit
code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
1
0
0
1
0
52
R
78
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
79
Manufacturer’s part number
0
0
1
1
0
0
1
1
33
3
80
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
81
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
82
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
83
Manufacturer’s part number
0
1
0
0
0
0
1
1
43
C
84
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
85
Manufacturer’s part number
(-A6D/A6DL)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
L
EO
Byte No. Function described
Pr
(-B6D/B6DL)
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
87
Manufacturer’s part number
0
1
0
0
0
1
1
0
46
F
88
Manufacturer’s part number
(L-version)
0
1
0
0
1
1
0
0
4C
L
Manufacturer’s part number
0
0
1
89
Manufacturer’s part number
0
0
1
90
Manufacturer’s part number
0
0
1
91
Revision code
0
0
1
92
Revision code
0
0
1
93
Manufacturing date
×
×
×
94
Manufacturing date
×
×
×
*6
99 t o 125 Manufacturer specific data
—
—
—
126
Intel specification frequency
0
1
1
127
Intel specification CE# latency 1
support
(-A6FD/A6FDL)
1
0
1
0
(-B6FD/B6FDL)
1
0
0
0
0
0
20
(Space)
0
0
0
0
0
20
(Space)
0
0
0
0
0
20
(Space)
1
0
0
0
0
30
Initial
0
0
0
0
0
20
(Space)
×
×
×
×
×
××
Year code
(BCD)*4
×
×
×
×
×
××
Week code
(BCD)*4
—
—
—
—
—
—
*5
0
0
1
0
0
64
100 MHz
0
0
1
1
1
C7
CL = 2, 3
0
0
1
0
1
C5
CL = 3
Data Sheet E0111H10
8
t
95 to 98 Assembly serial number
uc
od
86
HB52RD328DC-F
L
EO
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A)
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
7. These specifications are defined based on component specification, not module.
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Pr
Data Sheet E0111H10
9
HB52RD328DC-F
Block Diagram
EO
S0
S1
DQMB0
N0, N1
DQ0 to DQ7
DQMB1
CS
DQMB
CS D16
DQMB
DQMB4
I/O0 to I/O3
I/O0 to I/O3
DQ32 to DQ39
CS
DQMB
D0
CS D17
DQMB
CS
DQMB
CS D25
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D18
DQMB
CS
DQMB
CS D26
DQMB
D1
D2
DQMB5
N10, N11
N6, N7
DQ24 to DQ31
CS D19
DQMB
CS
DQMB
CS D27
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D20
DQMB
DQMB6
CS
DQMB
CS D28
DQMB
I/O0 to I/O3
I/O0 to I/O3
DQ48 to DQ55
CS
DQMB
CS
DQMB
D3
D4
DQ40 to DQ47
N12, N13
CS D21
DQMB
CS
DQMB
CS D29
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D22
DQMB
CS
DQMB
CS D30
DQMB
D5
D6
I/O0 to I/O3
CS
DQMB
CS D23
DQMB
D7
I/O0 to I/O3
VCC
VCC (D0 to D31)
C0 to C15
VSS
N14, N15
DQ56 to DQ63
VSS (D0 to D31)
D13
D14
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D31
DQMB
D15
uc
od
I/O0 to I/O3
DQMB7
CLK (D0 to D3, D16 to D19)
CLK (D4 to D7, D20 to D23)
CLK (D8 to D11, D24 to D27)
CLK (D12 to D15, D28 to D31)
CK1
D12
I/O0 to I/O3
RAS (D0 to D31)
CAS (D0 to D31)
A0 to A11 (D0 to D31)
BA0 (D0 to D31)
BA1 (D0 to D31)
CKE (D0 to D15)
CKE (D16 to D31)
WE (D0 to 31)
CK0
D11
I/O0 to I/O3
I/O0 to I/O3
RE
CE
A0 to A11
BA0
BA1
CKE0
CKE1
WE
D10
I/O0 to I/O3
I/O0 to I/O3
Pr
DQMB3
D9
I/O0 to I/O3
I/O0 to I/O3
N4, N5
DQ16 to DQ23
CS D24
DQMB
I/O0 to I/O3
L
DQMB2
D8
I/O0 to I/O3
N2, N3
DQ8 to DQ15
CS
DQMB
N8, N9
I/O0 to I/O3
I/O0 to I/O3
Serial PD
SCL
SCL
A0
A1
A2
SDA
SDA
U0
Notes:
1.SDA pull-up resister is required due to
the open-drain/open-collector output.
2.SCL pull-up resistore is recommended
because of the normal SCL line inactive
"High" state.
D0 to D3: HM5264405F
U0: 2-kbit EEPROM
C0 to C15: 0.1 μF
N0 to N15: Network resistors(10 Ω)
t
Data Sheet E0111H10
10
HB52RD328DC-F
Absolute Maximum Ratings
EO
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
4.0
W
Operating temperature
Topr
0 to +65
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
L
1. Respect to VSS .
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1, 2
Input low voltage
0
0
V
3
VIH
2.0
VCC + 0.3
V
1, 4, 5
VIL
–0.3
0.8
V
1, 6
All voltage referred to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
Others: VIH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS .
t
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Notes: 1.
2.
3.
4.
5.
6.
Pr
Input high voltage
VSS
Data Sheet E0111H10
11
HB52RD328DC-F
VIL/VIH Clamp (Component characteristic)
EO
This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins.
Minimum VIL Clamp Current
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
L
VIL (V)
–1.2
–1
–0.9
–8
–4
–2
–0.8
–0.6
–0.6
0
Pr
–0.4
0
–0.2
0
0
0
0
I (mA)
–10
–15
–20
–25
–30
–35
–2
–1.5
–1
–0.5
0
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od
–5
VIL (V)
t
Data Sheet E0111H10
12
HB52RD328DC-F
Minimum VIH Clamp Current
EO
VIH (V)
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
L
VCC + 0.6
VCC + 0.4
VCC + 0.2
VCC + 0
I (mA)
8
6
4
2
0
0
VCC + 0.5
uc
od
0
VCC + 0
0
Pr
10
0
VCC + 1
VCC + 1.5
VCC + 2
VIH (V)
t
Data Sheet E0111H10
13
HB52RD328DC-F
IOL/IOH Characteristics (Component characteristic)
EO
Output Low Current (I OL)
I OL
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
58
70
188
72
194
1.65
L
151
75
203
1.8
77
209
1.95
77
212
3
80
220
3.45
81
223
1
1.4
1.5
IOL (mA)
200
150
uc
od
Pr
250
min
max
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Vout (V)
t
Data Sheet E0111H10
14
HB52RD328DC-F
Output High Current (I OH ) (Ta = 0 to 65˚C, VCC = 3.0 V to 3.45 V, VSS = 0 V)
EO
I OH
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
L
1.8
–227
–73
–248
–78
–270
–81
–285
1
–89
–345
0
–93
1.65
1.5
1.4
0
–200
0.5
1
–503
1.5
2
2.5
3
3.5
uc
od
IOH (mA)
–100
0
Pr
–67
min
–300
–400
–500
–600
max
Vout (V)
t
Data Sheet E0111H10
15
HB52RD328DC-F
DC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
EO
HB52RD328DC
-A6F/A6FL
-B6F/B6FL
Symbol Min
Max
Operating current
(CE latency = 2)
I CC1
—
1248 —
1248 mA
(CE latency = 3)
I CC1
—
1248 —
1248 mA
Standby current in power down
I CC2P
—
48
—
48
Standby current in power down
(input signal stable)
I CC2PS
—
32
—
Standby current in non power
down
I CC2N
—
320
Active standby current in power
down
I CC3P
—
Active standby current in non
power down
I CC3N
—
L
Parameter
(CE latency = 3)
I CC4
I CC4
Max
Unit
Test conditions
Notes
Burst length = 1
t RC = min
1, 2, 3
mA
CKE = VIL,
t CK = 12 ns
6
32
mA
CKE = VIL, t CK = ∞
7
—
320
mA
CKE, S = VIH,
t CK = 12 ns
4
128
—
128
mA
CKE = VIL,
t CK = 12 ns
1, 2, 6
576
—
576
mA
CKE, S = VIH,
t CK = 12 ns
1, 2, 4
t CK = min, BL = 4
1, 2, 5
Pr
Burst operating current
(CE latency = 2)
Min
—
1168 —
1168 mA
—
1168 —
1168 mA
—
2048 —
2048 mA
t RC = min
2, 3
—
32
32
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
I CC5
Self refresh current
I CC6
Self refresh current (L-version)
I CC6
—
12.8
Input leakage current
I LI
–1
1
Output leakage current
I LO
–1.5
1.5
Output high voltage
VOH
2.4
—
Output low voltage
VOL
—
0.4
—
mA
uc
od
Refresh current
—
12.8
mA
–1
1
µA
0 ≤ Vin ≤ VCC
–1.5
1.5
µA
0 ≤ Vout ≤ VCC
DQ = disable
2.4
—
V
I OH = –4 mA
—
0.4
V
I OL = 4 mA
t
Data Sheet E0111H10
16
HB52RD328DC-F
EO
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
L
Parameter
Max
Unit
Notes
Input capacitance (Address)
CIN
150
pF
1, 2, 4
Input capacitance (RE, CE, W, S, CKE)
CIN
150
pF
1, 2, 4
Input capacitance (CK)
CIN
90
pF
1, 2, 4
Input capacitance (DQMB)
CIN
30
pF
1, 2, 4
CI/O
30
pF
1, 2, 3, 4
Input/Output capacitance (DQ)
Notes: 1.
2.
3.
4.
Pr
Symbol
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Dout.
This parameter is sampled and not 100% tested.
t
uc
od
Data Sheet E0111H10
17
HB52RD328DC-F
AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
EO
HB52RD328DC
-A6F/A6FL
-B6F/B6FL
PC100
Symbol Symbol Min
Max
Min
Max
Unit
Notes
System clock cycle time
(CE latency = 2)
t CK
Tclk
10
—
15
—
ns
1
(CE latency = 3)
t CK
Tclk
10
—
10
—
ns
CK high pulse width
t CKH
Tch
4
—
4
—
ns
1
CK low pulse width
t CKL
Tcl
4
—
4
—
ns
1
1, 2
Access time from CK
(CE latency = 2)
L
Parameter
Tac
—
6
—
8
ns
t AC
Tac
—
6
—
6
ns
t OH
Toh
3
—
3
—
ns
1, 2
CK to Data-out low impedance t LZ
2
—
2
—
ns
1, 2, 3
CK to Data-out high impedance t HZ
—
6
—
6
ns
1, 4
Tsi
3
—
3
—
ns
1, 5, 6
Tpde
3
—
3
—
ns
1
(CE latency = 3)
Data-out hold time
Data-in setup time
Pr
t AC
t AS , t CS,
t DS, t CES
CKE setup time for power down t CESP
exit
t AH, t CH,
t DH, t CEH
Thi
1
—
1
—
ns
1, 5
Ref/Active to Ref/Active
command period
t RC
Trc
70
—
70
—
ns
1
Active to Precharge command
period
t RAS
Tras
50
120000
50
120000
ns
1
Active command to column
command (same bank)
t RCD
Trcd
20
—
20
—
ns
1
Precharge to active command
period
t RP
Trp
20
—
20
—
ns
1
Write recovery or data-in to
precharge lead time
t DPL
Tdpl
10
—
10
—
ns
1
Active (a) to Active (b)
command period
t RRD
Trrd
20
—
20
—
ns
1
Transition time (rise to fall)
tT
1
5
1
5
ns
Refresh period
t REF
—
64
—
64
ms
t
uc
od
Data-in hold time
Data Sheet E0111H10
18
HB52RD328DC-F
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES define CKE setup time to CK rising edge except power down exit command.
t AS /tAH: Address, t CS/tCH: S, RE, CE, W, DQMB
t DS/tDH: Data-in, t CES/tCEH : CKE
EO
Notes: 1.
2.
3.
4.
5.
6.
Test Conditions
• Input and output timing reference levels: 1.5 V
L
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
Pr
t
T
CL
tT
t
uc
od
Data Sheet E0111H10
19
HB52RD328DC-F
Relationship Between Frequency and Minimum Latency
EO
HB52RD328DC
Parameter
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
tCK (ns)
Symbol
Active command to column command
(same bank)
PC100
Symbol
Notes
lRCD
2
1
Active command to active command
(same bank)
lRC
7
= [lRAS+ lRP]
1
Active command to precharge command
(same bank)
lRAS
5
1
Precharge command to active command
(same bank)
lRP
2
1
Write recovery or data-in to precharge
command (same bank)
lDPL
1
1
Active command to active command
(different bank)
lRRD
2
1
L
10
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
Pr
Self refresh exit time
Tdpl
lSREX
Tsrx
1
2
lAPW
Tdal
3
= [lDPL + lRP]
7
= [lRC]
3
lSEC
(CE latency = 3)
lHZP
lHZP
Last data out to active command
(auto precharge) (same bank)
lAPR
Last data out to precharge (early precharge)
(CE latency = 2)
(CE latency = 3)
lEP
lEP
Column command to column command
lCCD
Write command to data in latency
lWCD
DQMB to data in
lDID
DQMB to data out
lDOD
CKE to CK disable
lCLE
Register set to active command
lRSA
uc
od
Precharge command to high impedance
(CE latency = 2)
Troh
2
Troh
3
1
–1
–2
Tccd
1
Tdwd
0
Tdqm
0
Tdqz
2
Tcke
1
Tmrd
1
t
Data Sheet E0111H10
20
HB52RD328DC-F
HB52RD328DC
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
EO
Parameter
PC100
Symbol
tCK (ns)
Symbol
S to command disable
lCDD
0
Power down exit to command input
lPEC
1
Burst stop to output valid data hold
(CE latency = 2)
lBSR
1
lBSR
2
(CE latency = 3)
(CE latency = 3)
L
Burst stop to output high impedance
(CE latency = 2)
Burst stop to write data ignore
10
lBSH
2
lBSH
3
lBSW
0
Notes
t
uc
od
Pr
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP].
Data Sheet E0111H10
21
HB52RD328DC-F
Pin Functions
EO
CK0/CK1 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K
rising edge.
S 0/S 1 (in pu t p in ): Whe n S is Low, the command input cyc le bec omes valid. Whe n S is High, all inputs ar e
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules,
they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the
combination of their voltage levels. For details, refer to the command operation section.
L
A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive
command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or
wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10
def ines the pre cha rge mode. Whe n A10 = High at the pre cha rge command cyc le, both banks ar e pre cha rged.
B ut whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is
precharged.
Pr
A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1,
bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is
selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected.
CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next
C K rising edge is valid. If C KE is Low, the next C K rising edge is invalid. This pin is used for powe r-dow n
mode, clock suspend mode and self refresh mode.
uc
od
DQMB 0 to DQMB 7 (in pu t p in s): R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low,
the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
t
Data Sheet E0111H10
22
HB52RD328DC-F
Command Operation
EO
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE
Symbol
n-1 n
S
RE
CE
W
A0
A12/A13 A10 to A11
Ignore command
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
H
×
L
H
H
L
×
×
×
Column address and read command READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
H
×
L
H
L
H
V
H
V
Column address and write command WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
H
×
L
H
L
L
V
H
V
Burst stop in full page
L
Command
BST
READ A
WRIT A
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
PALL
H
×
L
L
H
L
×
H
×
REF/SELF H
V
L
L
L
H
×
×
×
MRS
×
L
L
L
L
V
V
V
Precharge all bank
Refresh
Mode register set
Pr
Row address strobe and bank active ACTV
H
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
uc
od
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command input
at the clock. However, the internal status is held.
No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page) and
is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the
start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition, the
start address of burst read is determined by the column address and the bank select address (BA). After the read
operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
t
Data Sheet E0111H10
23
HB52RD328DC-F
EO
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the
burst wr ite mode is sele cted, the column addr ess and the bank sele ct addr ess (B A) bec ome the burst wr ite start
addr ess. Whe n the single wr ite mode is sele cted, data is only wr itten to the loca tion spec ified by the column
address and the bank select address (BA).
Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this
command is illegal.
L
Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by bank
sele ct addr ess (B A) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2
is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13.
If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low
and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Pr
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the
one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mod e re gister set [M RS ]: The S DRA M module has a mode re giste r that def ines how it oper ates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
re giste r conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode
register set command to set up the mode register.
t
uc
od
Data Sheet E0111H10
24
HB52RD328DC-F
DQMB Truth Table
EO
CKE
Command
Symbol
n-1
n
DQMB
Write enable/output enable
ENB
H
×
L
Write inhibit/output disable
MASK
H
×
H
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: I DID is needed.
Read: I DOD is needed.
L
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other
hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
Pr
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held
(the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or burst wr ite by setting DQMB .
For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
CKE
n
S
RE
CE
W
Address
Clock suspend mode entry
H
L
×
×
×
×
×
Any
Clock suspend
L
Clock suspend
Clock suspend mode exit
L
Idle
Auto-refresh command (REF)
H
Idle
Self-refresh entry (SELF)
H
Idle
Power down entry
H
Command
Active
H
Self refresh
Self refresh exit (SELFX)
L
L
Power down
Power down exit
L
L
Note: H: VIH. L: VIL. ×: VIH or VIL.
uc
od
n-1
Current state
L
×
×
×
×
×
H
×
×
×
×
×
H
L
L
L
H
×
L
L
L
L
H
×
L
L
H
H
H
×
L
H
×
×
×
×
H
L
H
H
H
×
H
H
×
×
×
×
H
L
H
H
H
×
H
H
×
×
×
×
t
Data Sheet E0111H10
25
HB52RD328DC-F
EO
Clock susp en d mod e en tr y: The S DRA M module ente rs cloc k suspend mode fr om ac tive mode by setting
C KE to Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k
suspend mode changes depending on the current status (1 clock before) as shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the
bank active status.
RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to
be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted.
However, the internal state is held.
L
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock susp en d mod e exit : The S DRA M module exits fr om cloc k suspend mode by setting C KE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Pr
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module starts
auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M module. F or
eve ry auto- ref resh cyc le, the interna l addr ess counte r is update d. Ac cordingly, 4096 time s ar e re quired to
refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state.
In addition, since the pre cha rge for all banks is automatica lly per forme d af ter auto- ref resh, no pre cha rge
command is required after auto-refresh.
uc
od
S elf-r ef re sh en tr y [S E LF] : Whe n this command is input during the ID LE state, the S DRA M module starts
self- re fre sh oper ation. Af te r the exe cution of this command, self- re fre sh continues while C KE is Low. S inc e
self-refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module enters
powe r down mode. In powe r down mode, powe r consumption is suppre sse d by cutting off the initia l input
circuit.
S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M module ca n exit
from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state.
Powe r d own exit : Whe n this command is exe cute d at the powe r down mode, the S DRA M module ca n exit
from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
t
Data Sheet E0111H10
26
HB52RD328DC-F
Function Truth Table
EO
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM module. The following table assumes that CKE is high.
Current state
S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
H
BA, RA
ACTV
ILLEGAL*4
L
H
L
BA, A10
PRE, PALL
NOP*6
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
L
H
H
L
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
×
NOP
NOP
L
×
BST
NOP
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
H
BA, RA
ACTV
Bank and row active
L
BA, A10
PRE, PALL
NOP
L
H
×
L
L
L
MODE
H
×
×
×
×
L
H
H
H
×
L
H
H
L
×
L
H
L
H
BA, CA, A10 READ/READ A
Begin read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
uc
od
Row active
Pr
H
L
Idle
L
L
L
REF, SELF
Refresh
MRS
Mode register set
DESL
NOP
NOP
NOP
BST
NOP
t
Data Sheet E0111H10
27
HB52RD328DC-F
Current state
RE
CE
W
Address
Command
Operation
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10 READ/READ A
Continue burst read to CE
latency and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and
Precharge
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
MODE
MRS
ILLEGAL
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
Read with autoprecharge
L
×
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
BA, A10
PRE, PALL
ILLEGAL*4
L
H
×
REF, SELF
ILLEGAL
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10 READ/READ A
Term burst and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
BST
ILLEGAL
t
uc
od
Write
H
Pr
L
EO
Read
S
Data Sheet E0111H10
28
HB52RD328DC-F
S
RE
CE
W
Address
Command
Operation
Write with autoprecharge
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
MODE
MRS
ILLEGAL
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
ILLEGAL*5
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*5
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
L
L
Refresh (autorefresh)
H
uc
od
Pr
L
EO
Current state
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If t RRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
t
Data Sheet E0111H10
29
HB52RD328DC-F
From PRECHARGE state, command operation
EO
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE state
after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
L
To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
Pr
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
uc
od
T o [PR E] , [PA LL ]: The se commands set the S DRA M module to pre cha rge mode. (H oweve r, an interva l of
tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE latency,
the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
t
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
Data Sheet E0111H10
30
HB52RD328DC-F
EO
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the
SDRAM module then enters precharge mode.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
L
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
Pr
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode.
uc
od
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM
module enters precharge mode.
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
T o [D ES L] , [N OP] , [B S T] : Af te r an auto- ref resh cyc le (a fter tRC), the S DRA M module automatica lly ente rs
the IDLE state.
t
Data Sheet E0111H10
31
HB52RD328DC-F
Simplified State Diagram
EO
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
L
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
Pr
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
CKE
READ
WRITE
WITH
AP
READ
WRITE
WRITEA
CKE
CKE
CKE_
CKE
POWER
ON
READ
SUSPEND
READ
WITH AP
READA
PRECHARGE
POWER
APPLIED
READ
PRECHARGE
CKE_
WRITEA
SUSPEND
WRITE
WITH AP
Read
CKE_
uc
od
READ
WITH AP
WRITE
WITH AP
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
t
Data Sheet E0111H10
32
HB52RD328DC-F
Mode Register Configuration
EO
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode
register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9 A8: (OPCODE ): The S DRA M module has two types of wr ite modes. One is the
burst write mode, and the other is the single write mode. These bits specify write mode.
B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column
address specified in the write cycle.
L
B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
Pr
A2, A1, A0: (BL): These pins specify the burst length.
A13
A12
A11
A10
A9
A8
OPCODE
A7
A6
0
0
0
0
0
1
R
0
1
0
2*
0
1
1
3
1
X
X
R
A8
0
0
0
0
0
0
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
1
Note: only -A6.
Write mode
BT
0 Sequential
1
Burst read and single write
R
A2
A1
A0
BL
A3 Burst Type
Burst read and burst write
R
A3
uc
od
0
R
A9
A4
LMODE
A6 A5 A4 CAS Latency
A13 A12 A11 A10
A5
Interleave
A2 A1 A0
Burst Length
BT=0
BT=1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
t
Data Sheet E0111H10
33
HB52RD328DC-F
Burst Sequence
EO
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A1
0
0
0
0
0
1
L
A2
A0 Sequential
Interleave
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
Pr
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
t
uc
od
Data Sheet E0111H10
34
HB52RD328DC-F
Operation of the SDRAM module
EO
Read/Write Operations
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the
status of the bank sele ct addr ess (B A) pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11
pins at the bank active command cycle. An interval of tRCD is required between the bank active command input
and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the
(CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
L
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column
address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts
after the number of clocks specified by the CE Latency. The CE Latency can be set to 2 or 3.
Whe n the burst length is 1, 2, 4 or 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the
successive burst-length data has been output.
Pr
The CE latency and burst length must be specified at the mode register.
CE Latency
CK
Command
Address
Dout
ACTV
Row
CL = 2
CL = 3
READ
Column
out 0
uc
od
t RCD
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CE latency
Burst Length = 4
t
Data Sheet E0111H10
35
HB52RD328DC-F
Burst Length
EO
CK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
out 0 out 1 out 2 out 3
Dout
BL = 4
L
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
BL = full page
out 0-1
out 0
out 1
BL : Burst Length
CE Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8)
of the mode register.
Pr
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to
1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess
and the bank select address (BA) at the write command set cycle.
CK
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page
uc
od
t RCD
Command
in 8
in 0-1
in 0
in 1
CE Latency = 2, 3
t
Data Sheet E0111H10
36
HB52RD328DC-F
EO
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite
oper ation, data is only wr itten to the column addr ess and the bank sele ct addr ess (B A) spec ified by the wr ite
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CK
Command
Address
Auto Precharge
WRIT
ACTV
Row
Column
L
Din
t RCD
in 0
Pr
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a
re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d
for the same bank after the execution of this command must be the bank active (ACTV) command. In addition,
an interval defined by lAPR is required before execution of the next command.
CE latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CK
CL=2 Command
ACTV
READ A
lRAS
Dout
uc
od
Burst Read (Burst Length = 4)
ACTV
out0
out1
out2
out3
lAPR
CL=3 Command
ACTV
READ A
lRAS
Dout
ACTV
out0
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
t
Data Sheet E0111H10
37
HB52RD328DC-F
EO
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a
burst write or single write operation, a precharge command need not be executed after each write operation. The
command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV )
command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next
command.
Burst Write (Burst Length = 4)
CK
L
Command
ACTV
ACTV
WRIT A
IRAS
Din
in0
in1
in2
in3
lAPW
Pr
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
Command
ACTV
ACTV
WRIT A
IRAS
Din
uc
od
CK
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
t
Data Sheet E0111H10
38
HB52RD328DC-F
Full-page Burst Stop
EO
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a
full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The
timing from command input to the last data changes depending on the CE latency setting. In addition, the BST
command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CE latency
BST to valid data
BST to high impedance
2
1
2
3
2
3
L
CE Latency = 2, Burst Length = full page
CK
Dout
Pr
BST
Command
out
out
out
out
out
out
l BSH = 2 cycle
l BSR = 1 cycle
CK
BST
Command
Dout
uc
od
CE Latency = 3, Burst Length = full page
out
out
out
out
out
out
l BSR = 2 cycle
out
l BSH = 3 cycle
t
Data Sheet E0111H10
39
HB52RD328DC-F
EO
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input
during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt
cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command.
Burst Length = full page
CK
BST
Command
L
Din
in
PRE/PALL
in
t DPL
I BSW = 0 cycle
t
uc
od
Pr
Data Sheet E0111H10
40
HB52RD328DC-F
Command Intervals
EO
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address of
the same bank as the preceding read command execution, the second read can be performed after an interval of
no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the
second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
Command
Address
ACTV
Row
L
CK
READ
READ
Column A Column B
Pr
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
CE Latency = 3
Burst Length = 4
Bank 0
uc
od
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad
commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad
that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout
Dout
t
Bank0
Active
CE Latency = 3
Burst Length = 4
Data Sheet E0111H10
41
HB52RD328DC-F
Write command to Write command interval:
EO
1. Same bank, same ROW address: When another write command is executed at the same ROW address of
the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less
than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Row
BA
Din
WRIT
Column A Column B
in A0
in B0
in B1
in B2
in B3
Column =A Column =B
Write
Write
Pr
Bank0
Active
WRIT
L
Address
ACTV
Burst Write Mode
Burst Length = 4
Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a
bank-active command.
uc
od
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite
command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
Bank3 Bank0 Bank3
Active Write Write
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
t
Data Sheet E0111H10
42
HB52RD328DC-F
Read command to Write command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the
same bank as the preceding read command, the write command can be performed after an interval of no less than
1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
CK
Command
CL=3
Din
L
CL=2
DQMB
READ WRIT
in B0
in B1
in B2
in B3
Burst Length = 4
Burst write
High-Z
Dout
Pr
READ to WRITE Command Interval (2)
CK
Command
WRIT
uc
od
DQMB
READ
2 clock
CL=2
Dout
CL=3
Din
High-Z
High-Z
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that
the output buffer becomes High-Z before data input.
t
Data Sheet E0111H10
43
HB52RD328DC-F
Write command to Read command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the
same bank as the preceding write command, the read command can be performed after an interval of no less than
1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cyc le bef ore the re ad
command is executed.
WRITE to READ Command Interval (1)
CK
DQMB
Din
WRIT
READ
L
Command
in A0
Dout
out B0
out B1
out B2
Pr
Column = A
Write
Column = B
Read
CE Latency
Column = B
Dout
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
WRITE to READ Command Interval (2)
Command
WRIT
READ
DQMB
Din
in A0
in A1
Dout
uc
od
CK
out B0
Column = A
Write
out B1
CE Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot
be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive
command.
t
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data
will continue to be written until one clock before the read command is executed (as in the case of the same bank
and the same address).
Data Sheet E0111H10
44
HB52RD328DC-F
Read with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by
the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond
command.
Read with Auto Precharge to Read Command Interval (Different bank)
CK
BA
Dout
READ A
READ
L
Command
bank0
Read A
out A0
out A1
out B0
bank3
Read
out B1
CE Latency = 3
Burst Length = 4
Pr
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
uc
od
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one
bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval (Different bank)
CK
Command
WRIT A
WRIT
BA
Din
in A0
bank0
Write A
in A1
in B0
bank3
Write
in B1
Note: Internal auto-precharge starts at the timing indicated by "
in B2
in B3
Burst Length = 4
".
2. Same bank: The consecutive write command (the same bank) is illegal.
t
Data Sheet E0111H10
45
HB52RD328DC-F
Read with auto precharge to Write command interval
EO
Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input. The
internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CK
Command
READ A
WRIT
DQMB
L
BA
CL = 2
CL = 3
Din
in B0
Dout
in B1
in B2
in B3
High-Z
Pr
bank0
Read A
Burst Length = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet E0111H10
46
HB52RD328DC-F
Write with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Howe ver , in ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad
command is executed. The internal auto-precharge of one bank starts at the next clock of the second command.
Write with Auto Precharge to Read Command Interval (Different bank)
CK
Command
DQMB
Din
READ
L
BA
WRIT A
in A0
Dout
out B0
Pr
bank0
Write A
out B1
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by "
out B2
out B3
CE Latency = 3
Burst Length = 4
".
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet E0111H10
47
HB52RD328DC-F
Read command to Precharge command interval (same bank):
EO
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after
the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the
precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be
assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 2, Burst Length = 4
Command
L
CK
PRE/PALL
READ
Dout
out A0
out A1
CL=2
CK
Command
READ
out A3
l EP = -1 cycle
Pr
CE Latency = 3, Burst Length = 4
out A2
PRE/PALL
uc
od
Dout
out A0
CL=3
out A1
out A2
out A3
l EP = -2 cycle
t
Data Sheet E0111H10
48
HB52RD328DC-F
READ to PRECHARGE Command Interval (same bank): To stop output data
EO
CE Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 2
L
CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
PRE/PALL
Pr
Dout
READ
out A0
High-Z
lHZP = 3
t
uc
od
Data Sheet E0111H10
49
HB52RD328DC-F
EO
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d
for the same bank as the write command that preceded it, the minimum interval between the two commands is 1
cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQMB
for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank):
Burst Length = 4 (To stop write operation)
CK
DQMB
Din
WRIT
PRE/PALL
L
Command
tDPL
Pr
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
Burst Length = 4 (To write all data)
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
uc
od
tDPL
in A1
in A2
in A3
tDPL
t
Data Sheet E0111H10
50
HB52RD328DC-F
Bank active command interval:
EO
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank Active to Bank Active for Same Bank
CK
Command
ACTV
ACTV
Address
ROW
ROW
L
BA
t RC
Bank 0
Active
Bank 0
Active
Pr
2. In the case of different bank-active commands: The interval between the two bank-active commands must
be no less than tRRD.
Bank Active to Bank Active for Different Bank
CK
Address
ACTV
uc
od
Command
ACTV
ROW:0
ROW:1
BA
t RRD
Bank 0
Active
Bank 3
Active
t
Data Sheet E0111H10
51
HB52RD328DC-F
EO
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and
executing a bank-active command must be no less than lRSA .
CK
Command
Address
MRS
ACTV
CODE
BS & ROW
L
I RSA
Mode
Register Set
Bank
Active
DQMB Control
Pr
The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.
Re adin g: Whe n data is re ad, the output buff er ca n be contr olle d by DQMB . B y setting DQMB to Low, the
output buff er bec omes Low- Z, ena bling data output. B y setting DQMB to High, the output buff er bec omes
High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency
of DQMB during reading is 2 clocks.
t
uc
od
Writ in g: Input data ca n be maske d by DQMB . B y setting DQMB to Low, data ca n be wr itten. In addition,
when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of
DQMB during writing is 0 clock.
Data Sheet E0111H10
52
HB52RD328DC-F
Reading
EO
CK
DQMB
Dout
High-Z
out 0
out 1
out 3
lDOD = 2 Latency
L
Writing
CK
;
;;
Pr
DQMB
Din
in 0
in 1
in 3
l DID = 0 Latency
t
uc
od
Data Sheet E0111H10
53
HB52RD328DC-F
Refresh
EO
Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW
addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64
ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter
auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required.
L
S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held
Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter mina te d by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all
refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after exiting
from self-refresh mode.
Pr
Others
Powe r- down mod e: The S DRA M module ente rs powe r-dow n mode whe n C KE goes Low in the ID LE state.
In powe r down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down
mode continues while C KE is held Low. In addition, by setting C KE to High, the S DRA M module exits fr om
the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not
performed.
uc
od
Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M
module ente rs cloc k suspend mode. Dur ing cloc k suspend mode, exte rnal input signals ar e ignore d and the
interna l state is maintained. Whe n C KE is drive n High, the S DRA M module ter mina te s cloc k suspend mode,
and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high before
power up, the large current flows from these pins to VCC through the diodes.
t
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF).
S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping
DQMB to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus conte ntion
on memory system formed with a number of device.
Data Sheet E0111H10
54
HB52RD328DC-F
Initialization sequence
Power up sequence
EO
VCC
100 μs
200 μs
0V
CKE, DQMB
Low
CK
Low
S, DQ
Low
L
Power stabilize
t
uc
od
Pr
Data Sheet E0111H10
55
HB52RD328DC-F
Timing Waveforms
;;;
;;;;
EO
Read Cycle
t CK
t CKH t CKL
CK
;
;
;
;;;;;;
;
;
;
;;;;;;
;; ;;
t RC
VIH
CKE
t CS t CH
t CS t CH
RE
t CS t CH
CE
t CS t CH
L
S
t RP
t RAS
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
A12/A13
t AS t AH
A10
t AS t AH
Pr
W
t AS t AH
Address
t AS t AH
t AS t AH
t AS t AH
t CH
DQMB
Din
t AC
Dout
t AC
Bank 0
Read
t LZ
t OH
uc
od
t CS
Bank 0
Active
t CS t CH
t CS t CH
t AC
t OH
t AC
t OH
Bank 0
Precharge
t HZ
t OH
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet E0111H10
56
;
;
;
;
;
;;;;
HB52RD328DC-F
Write Cycle
EO
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t RP
;; ;
;
;;
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
L
t CS t CH
CE
t CS t CH
W
t AS t AH
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t CS t CH
t AS t AH
A12/A13
Pr
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
DQMB
t AS t AH
t AS t AH
t AS t AH
t CH
Din
t DH t DS t DH t DS
t DH
uc
od
t DS t DH tDS
t DPL
Dout
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet E0111H10
57
HB52RD328DC-F
;
;;; ;
;
EO
;
;
;;;;;;;;
;
;
;
;;;;;;
;;;;;;
;;
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
b+3
b’
b’+1
b’+2
b’+3
18
CK
CKE
VIH
S
RE
CE
W
Address
valid
DQMB
Dout
L
BA
code R: b
C: b’
C: b
b
High-Z
Din
Precharge
If needed
l RSA
l RCD
Output mask
Pr
l RP
Mode
Bank 3
register Active
Set
Bank 3
Read
l RCD = 3
CE latency = 3
Burst length = 4
= VIH or VIL
t
uc
od
Data Sheet E0111H10
58
;
;;;;;;;
;
;
;
;;;;;;;
;; ;
HB52RD328DC-F
Read Cycle/Write Cycle
EO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
Dout
CKE
Bank 0
Active
VIH
S
RE
a
a+1 a+2 a+3
L
Din
Bank 0
Read
Bank 3
Active
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
CE
W
Address
R:a
C:a
R:b
DQMB
Pr
BA
C:b
C:b'
C:b"
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1 a+2 a+3
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
t
uc
od
Data Sheet E0111H10
59
;
;;;;;;
;
;;
HB52RD328DC-F
Read/Single Write Cycle
;
; ;;
;
;
;
;
EO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a' C:a
DQMB
a
Bank 0
Active
CKE
L
Din
Dout
VIH
Bank 0
Read
a
a+1 a+2 a+3
Bank 3
Active
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
S
RE
W
BA
Address
R:a
C:a
DQMB
Din
Dout
Pr
CE
R:b
a
Bank 0
Read
Bank 3
Active
a+1
C:b C:c
a
b
c
a+3
Bank 0
Write
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
uc
od
Bank 0
Active
C:a
Read/Single write
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
t
Data Sheet E0111H10
60
HB52RD328DC-F
Read/Burst Write Cycle
; ;;
;
EO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;;;;
;;;
0
CK
CKE
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a'
DQMB
a
Bank 0
Active
CKE
L
Din
Dout
VIH
Bank 0
Read
a
a+1 a+2 a+3
a+1 a+2 a+3
Bank 3
Active
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
S
RE
W
BA
Address
R:a
C:a
DQMB
Pr
CE
R:b
C:a
a
Din
Dout
a
Bank 0
Read
Bank 3
Active
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 0
Precharge
uc
od
Bank 0
Active
a+1
Read/Burst write
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
t
Data Sheet E0111H10
61
HB52RD328DC-F
Full Page Read/Write Cycle
EO
;;;
;;;;
;;
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
DQMB
Dout
Din
Bank 0
Read
a+1
VIH
S
RE
CE
a+3
High-Z
Bank 3
Active
Burst stop
W
BA
Address
a+2
Bank 3
Precharge
L
CKE
Bank 0
Active
a
R:a
C:a
R:b
Pr
DQMB
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1
a+2
a+3
Bank 3
Active
a+4
a+5
a+6
Burst stop
Bank 3
Precharge
t
uc
od
Data Sheet E0111H10
62
;;;;;;;;
;;;;;;;
HB52RD328DC-F
EO
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;;;;;;;;;;;;;;;;;;
;;;;;;;;; ;;;;;;;;;;
;; ;
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
a
a+1
CK
CKE
VIH
S
RE
CE
W
BA
Address
L
DQMB
Din
Dout
Auto Refresh
tRC
Active
Bank 0
Auto Refresh
Read
Bank 0
Pr
Self Refresh Cycle
CK
Refresh cycle and
Read cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
l SREX
S
RE
CE
W
BA
A10=1
DQMB
Din
uc
od
CKE Low
CKE
Address
High-Z
t RC
t RP
Precharge
If needed
C:a
R:a
A10=1
High-Z
Dout
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
t
Data Sheet E0111H10
63
;
;
;;;;;
;
;;;
HB52RD328DC-F
Clock Suspend Mode
;
;
;;;;;;;;;;;;
;
;
;
;
;
;
;;;;;;
EO
t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
CK
CKE
RE
CE
W
BA
R:a
C:a
R:b
C:b
DQMB
L
Dout
a
Din
Bank0 Active clock
Active suspend start
CKE
S
Active clock Bank0
suspend end Read
a+1 a+2
Bank3
Active
a+3
b
High-Z
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
CE
Address
Pr
W
C:a R:b
R:a
DQMB
C:b
High-Z
Dout
Din
a
Bank0
Active
Active clock
suspend start
19
20
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
b+1 b+2 b+3
Earliest Bank3
Precharge
Write cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
RE
BA
18
Read cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
S
Address
17
Write suspend
start
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
t
uc
od
Data Sheet E0111H10
64
HB52RD328DC-F
Power Down Mode
EO
;
;
;
;
;
;;;;;;
;
;
;;;;;;
;
;
;
; ;;;
;
;
;;;;;
;
CK
CKE Low
CKE
S
RE
CE
L
W
BA
Address
R: a
A10=1
DQMB
Pr
Din
High-Z
Dout
tRP
Precharge command
If needed
Power down entry
Power down
mode exit
Active Bank 0
;;;
;;;;;;;;
;;;;;;;;
uc
od
Initialization Sequence
Power down cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
0
1
2
3
4
5
6
CK
CKE
VIH
S
RE
CE
W
DQMB
8
9
10
48
49
50
51
53
52
code
valid
Address
7
VIH
54
55
Valid
High-Z
DQ
t RP
t RC
Auto Refresh
t RSA
tRC
Auto Refresh
Mode register
Set
Bank active
If needed
t
All banks
Precharge
Data Sheet E0111H10
65
HB52RD328DC-F
Physical Outline
67.60
2.661
3.80 Max
0.150 Max
(Datum -A-)
1
23.20
0.913
2.50
0.098
B
4.60
0.181
4.60
0.181 32.80
1.291
2-R2.00
2-R0.079
uc
od
Component area
(back)
4.00 ± 0.10
0.157 ± 0.004
2
3.70
0.146
1.00 ± 0.10
0.039 ± 0.004
Pr
2.10
0.083
23.20
0.913
A
32.80
1.291
144
3.30
0.130
4.00 Min
0.157 Min
L
20.00
0.787
Component area
(front)
3.20 Min
0.126 Min
2R3.00 Min
2R0.118 Min
143
31.75
1.250
EO
Unit: mm
inch
2.00 Min
0.079 Min
(Datum -A-)
Detail B
Detail A
(DATUM -A-)
0.80
0.031
2.5
0.098
R0.75
R0.030
4.00 ± 0.10
0.157 ± 0.004
0.25 Max
0.010 Max
0.100 Min
2.55 Min
0.60 ± 0.05
0.024 ± 0.002
1.50 ± 0.10
0.059 ± 0.004
t
Data Sheet E0111H10
66
HB52RD328DC-F
Cautions
EO
L
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third
party’s patent, copyright, trademark, or other intellectual property rights for information contained in this
document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights,
including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when
used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other
consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
t
uc
od
Pr
Data Sheet E0111H10
67