LINER LTC2494CUHF-PBF

LTC2494
16-Bit 8-/16-Channel ΔΣ ADC
with PGA and Easy Drive
Input Current Cancellation
DESCRIPTION
FEATURES
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Up to 8 Differential or 16 Single-Ended Inputs
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise
Programmable Gain from 1 to 256
Integrated High Accuracy Temperature Sensor
GND to VCC Input/Reference Common Mode Range
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
2x Speed Mode/Reduced Power Mode (15Hz Using
Internal Oscillator and 80μA at 7.5Hz Output)
No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Tiny 5mm × 7mm QFN Package
APPLICATIONS
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Direct Sensor Digitizer
Direct Temperature Measurement
Instrumentation
Industrial Process Control
The LTC®2494 is a 16-channel (8-differential), 16-bit, No
Latency ΔΣ™ ADC with Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current
errors and the shortcomings of on-chip buffering through
automatic cancellation of differential input current. This
allows large external source impedances, and rail-to-rail
input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2494 includes programmable gain, a high accuracy temperature sensor and an integrated oscillator. This
device can be conﬁgured to measure an external signal
(from combinations of 16 analog input channels operating in single ended or differential modes) or its internal
temperature sensor. The integrated temperature sensor
offers 1/2°C resolution and 2°C absolute accuracy. The
LTC2494 can be conﬁgured to provide a progammable
gain from 1 to 256 in 8 steps.
The LTC2494 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the ﬁrst conversion, after a new channel is
selected, is valid.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Data Acquisition System with Temperature Compensation
Absolute Temperature Error
5
2.7V TO 5.5V
4
MUXOUT/
ADCIN
VCC
REF
+
+
IN
16-BIT ΔΣ ADC
WITH EASY-DRIVE
IN–
10μF
REF –
SDI
SCK
SDO
CS
4-WIRE
SPI INTERFACE
3
ABSOLUTE ERROR (°C)
CH0
CH1
•
•
•
CH7
CH8 16-CHANNEL
MUX
•
•
•
CH15
0.1μF
2
1
0
–1
–2
–3
COM
–4
TEMPERATURE
SENSOR
FO
MUXOUT/
ADCIN
OSC
2494 TA01a
–5
–55
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2494 TA01b
2494fb
1
LTC2494
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH15, COM) ................–0.3V to (VCC + 0.3V)
REF+, REF– ................................–0.3V to (VCC + 0.3V)
ADCINN, ADCINP, MUXOUTP,
MUXOUTN ................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2494C ................................................ 0°C to 70°C
LTC2494I ............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
GND
GND
SDI
FO
CS
SDO
SCK
TOP VIEW
38 37 36 35 34 33 32
GND 1
31 GND
NC 2
30 REF–
GND 3
29 REF+
GND 4
28 VCC
GND 5
27 MUXOUTN
GND 6
26 ADCINN
39
COM 7
25 ADCINP
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH2 10
22 CH14
CH3 11
21 CH13
20 CH12
CH4 12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2494CUHF#PBF
LTC2494CUHF#TRPBF
2494
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2494IUHF#PBF
LTC2494IUHF#TRPBF
2494
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
2494fb
2
LTC2494
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The ● denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
Resolution (No Missing Codes)
Integral Nonlinearity
Offset Error
Offset Error Drift
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
Output Noise
Internal PTAT Signal
Internal PTAT Temperature Coefﬁcient
Programmable Gain
CONDITIONS
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
2.7V ≤ VCC ≤ 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 13)
TA = 27°C (Note 14)
MIN
16
TYP
MAX
2
1
0.5
10
20
●
●
5
●
32
0.1
●
32
0.1
15
15
15
0.6
27.8
●
28.0
93.5
UNITS
Bits
ppm of VREF
ppm of VREF
μV
nV/°C
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF
ppm of VREF
μVRMS
28.2
1
mV
μV/°C
256
ELECTRICAL CHARACTERISTICS (2X SPEED)
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
Resolution (No Missing Codes)
Integral Nonlinearity
Offset Error
Offset Error Drift
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Output Noise
Programmable Gain
CONDITIONS
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
5V ≤ VCC ≤ 2.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC
MIN
16
●
●
TYP
MAX
2
1
0.2
100
20
2
●
32
0.1
●
32
0.1
0.85
●
1
UNITS
Bits
ppm of VREF
ppm of VREF
mV
nV/°C
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF/°C
μVRMS
128
CONVERTER CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
PARAMETER
Input Common Mode Rejection DC
Input Common Mode Rejection 60Hz ±2%
Input Common Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 60Hz ±2%
Input Normal Mode Rejection 50Hz/60Hz ±2%
Reference Common Mode Rejection DC
Power Supply Rejection DC
Power Supply Rejection, 50Hz ±2%
Power Supply Rejection, 60Hz ±2%
CONDITIONS
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
VREF = 2.5V, IN+ = IN– = GND
VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9)
VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9)
●
●
●
●
●
●
●
MIN
140
140
140
110
110
87
120
TYP
120
120
140
120
120
120
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
2494fb
3
LTC2494
ANALOG INPUT AND REFERENCE
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
CONDITIONS
GND – 0.3V
MIN
TYP
VCC + 0.3V
MAX
UNITS
V
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel)
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range (IN+ – IN–)
●
–FS
+FS
V
FS
Full Scale of the Differential Input (IN+ – IN–)
●
0.5VREF/Gain
LSB
Least Signiﬁcant Bit of the Output Code
●
FS/216
REF+
Absolute/Common Mode REF+ Voltage
●
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
●
GND
REF+ – 0.1V
V
●
0.1
V
VREF
Reference Voltage Range (REF+ – REF–)
CS(IN+)
IN+ Sampling Capacitance
CS(IN–)
IN– Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
11
pF
IDC_LEAK(IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
●
–10
1
10
nA
IDC_LEAK(IN–)
IDC_LEAK(REF+)
IDC_LEAK(REF–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
●
–10
1
10
nA
REF+ DC Leakage Current
Sleep Mode, REF+ = VCC
Sleep Mode, REF– = GND
●
–100
1
100
nA
●
–100
1
100
nA
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
VCC
V
11
REF– DC Leakage Current
VIN = 2VP-P DC to 1.8MHz
pF
50
ns
120
dB
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage (CS, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
●
MIN
VIL
Low Level Input Voltage (CS, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
●
VIL
Low Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
●
IIN
Digital Input Current (CS, FO, SDI)
0V ≤ VIN ≤ VCC
●
–10
IIN
Digital Input Current (SCK)
0V ≤ VIN ≤ VCC (Notes 10, 15)
●
–10
CIN
Digital Input Capacitance (CS, FO, SDI)
CIN
Digital Input Capacitance (SCK)
(Notes 10, 15)
VOH
High Level Output Voltage (SDO)
IO = –800μA
●
VOL
Low Level Output Voltage (SDO)
IO = 1.6mA
●
VOH
High Level Output Voltage (SCK)
IO = –800μA (Notes 10, 17)
●
IO = 1.6mA (Notes 10, 17)
●
VOL
Low Level Output Voltage (SCK)
IOZ
Hi-Z Output Leakage (SDO)
●
TYP
MAX
UNITS
VCC – 0.5
V
0.5
V
VCC – 0.5
V
0.5
V
10
μA
10
μA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
μA
POWER REQUIREMENTS
The ● denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
●
Conversion Current (Note 12)
Temperature Measurement (Note 12)
Sleep Mode (Note 12)
●
●
●
TYP
MAX
5.5
V
160
200
1
275
300
2
μA
μA
μA
2.7
UNITS
2494fb
4
LTC2494
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 16)
tHEO
tLEO
tCONV_1
Conversion Time for 1x Speed Mode
tCONV_2
Conversion Time for 2x Speed Mode
fISCK
MAX
UNITS
●
MIN
10
4000
kHz
External Oscillator High Period
●
0.125
50
μs
External Oscillator Low Period
●
0.125
50
μs
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
●
●
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
●
●
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
20556/fEOSC (in kHz)
ms
ms
ms
ms
38.4
fEOSC/8
kHz
kHz
Internal SCK Frequency
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
TYP
DISCK
Internal SCK Duty Cycle
(Notes 10, 17)
●
fESCK
External SCK Frequency Range
(Notes 10, 11, 15)
●
tLESCK
External SCK Low Period
(Notes 10, 11, 15)
●
125
ns
tHESCK
External SCK High Period
(Notes 10, 11, 15)
●
125
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
●
0.61
tDOUT_ESCK
External SCK 24-Bit Data Output Time
(Notes 10, 11, 15)
t1
CS↓ to SDO Low
●
0
200
ns
t2
CS↑ to SDO High Z
●
0
200
ns
t3
CS↓ to SCK↑
Internal SCK Mode
●
0
200
t4
CS↓ to SCK↑
External SCK Mode
●
50
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
t5
SCK Set-Up Before CS↓
t7
SDI Setup Before SCK↑
(Note 5)
t8
SDI Hold After SCK↑
(Note 5)
45
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise speciﬁed.
VREFCM = VREF/2, FS = 0.5VREF/Gain
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise speciﬁed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
%
kHz
0.64
24/fESCK (in kHz)
●
(Note 5)
0.625
192/fEOSC (in kHz)
55
4000
●
ms
ms
ms
ns
ns
200
ns
15
ns
●
50
ns
●
100
ns
●
100
ns
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
2494fb
5
LTC2494
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
–45°C
1
25°C
0
85°C
–1
–2
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
INL (ppm OF VREF)
2
1
–45°C, 25°C, 85°C
0
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–0.75
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
8
4
0
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
85°C
25°C
–45°C
–4
–8
12
85°C
2
–45°C
0
–4
4
Noise Histogram (6.8sps)
12
12
–0.75
–4
–12
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
NUMBER OF READINGS (%)
1.25
2494 G06
Long-Term ADC Readings
5
10,000 CONSECUTIVE
READINGS
RMS = 0.59μV
VCC = 2.7V
AVERAGE = –0.19μV
VREF = 2.5V
10 VIN = 0V
TA = 25°C
8 GAIN = 256
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
4 TA = 25°C, RMS NOISE = 0.60μV, GAIN = 256
3
6
4
2
1
0
–1
–2
–3
2
2
85°C
–45°C
0
Noise Histogram (7.5sps)
14
4
25°C
2494 G05
14
6
1.25
2494 G03
–8
2494 G04
NUMBER OF READINGS (%)
8
4
–12
–1.25
2.5
10,000 CONSECUTIVE
READINGS
RMS = 0.60μV
VCC = 5V
AVERAGE = –0.69μV
VREF = 5V
10 VIN = 0V
TA = 25°C
8 GAIN = 256
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
25°C
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
–0.75
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
TUE (ppm OF VREF)
12
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
–1
2494 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
–45°C, 25°C, 85°C
0
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2494 G01
12
1
–2
–3
–1.25
2.5
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
ADC READING (μV)
INL (ppm OF VREF)
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
–4
0
0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.2
1.8
2494 G07
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.2
1.8
2494 G08
–5
0
10
30
40
20
TIME (HOURS)
50
60
2494 G09
2494fb
6
LTC2494
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
0.9
RMS Noise vs VIN(CM)
1.0
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
RMS NOISE (μV)
RMS NOISE (μV)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
0.9
0.8
0.7
0.6
0.5
RMS Noise vs Temperature (TA)
1.0
0.8
0.7
0.6
–1
0
2
1
3
5
4
OFFSET ERROR (ppm OF VREF)
0.5
0.8
0.7
0.6
0.5
0.4
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
0
–0.1
–0.2
–0.3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
0
–0.1
–0.2
1
2
3
VREF (V)
5
4
–1
75
90
2494 G16
0
1
3
2
VIN(CM) (V)
5
4
0.2
0.1
Offset Error vs VREF
0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0
–0.1
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
0
–0.1
–0.2
–0.3
2.7
6
2494 G15
OFFSET ERROR (ppm OF VREF)
0.1
0.1
Offset Error vs VCC
0.3
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.2
0.2
2494 G14
Offset Error vs Temperature
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
–0.3
0
2494 G13
0.3
90
Offset Error vs VIN(CM)
0.3
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
0.9
0.6
75
2494 G12
RMS Noise vs VREF
0.7
0 15 30 45 60
TEMPERATURE (°C)
2494 G11
1.0
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
0.4
2.7
0.4
–45 –30 –15
6
VIN(CM) (V)
RMS NOISE (μV)
RMS NOISE (μV)
0.8
0.6
0.4
2.5
RMS Noise vs VCC
0.9
0.7
0.5
2494 G10
1.0
0.8
0.5
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
0.9
RMS NOISE (μV)
1.0
–0.2
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2494 G17
–0.3
0
1
2
3
VREF (V)
4
5
2494 G18
2494fb
7
LTC2494
TYPICAL PERFORMANCE CHARACTERISTICS
On-Chip Oscillator Frequency
vs VCC
310
310
306
304
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
300
–45 –30 –15
306
304
0 15 30 45 60
TEMPERATURE (°C)
75
300
90
–120
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
–80
–80
–120
–120
–140
30600
–140
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
30650
30700
30750
FREQUENCY AT VCC (Hz)
Sleep Mode Current
vs Temperature
2.0
500
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
CS GND
FO = EXT OSC
TA = 25°C
450
SUPPLY CURRENT (μA)
SLEEP MODE CURRENT (μA)
180
1.0
0.8
VCC = 2.7V
400
350
300
250
2494 G25
VCC = 2.7V
140
120
0 15 30 45 60
TEMPERATURE (°C)
75
90
2494 G24
3
2
VCC = 5V
VCC = 3V
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
1
0
25°C, 85°C
–1
200
–45°C
–2
100
90
VCC = 5V
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
150
75
FO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
100
–45 –30 –15
30800
0.4
0.2
1M
160
Conversion Current
vs Output Data Rate
VCC = 5V
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
2494 G23
2494 G22
FO = GND
1.8 CS = VCC
SCK = NC
1.6
SDO = NC
1.4 SDI = GND
10
2494 G21
200
–60
–100
0 15 30 45 60
TEMPERATURE (°C)
1
Conversion Current
vs Temperature
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 FO = GND
TA = 25°C
–100
0
–45 –30 –15
–140
CONVERSION CURRENT (μA)
–60
0.6
5.5
0
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
1.2
–80
PSRR vs Frequency at VCC
REJECTION (dB)
REJECTION (dB)
–40
–60
2494 G20
PSRR vs Frequency at VCC
–20
–40
–100
302
2494 G19
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
INL (ppm OF VREF)
302
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
308
FREQUENCY (kHz)
FREQUENCY (kHz)
308
PSRR vs Frequency at VCC
0
REJECTION (dB)
On-Chip Oscillator Frequency
vs Temperature
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 G26
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
2.5
2494 G27
2494fb
8
LTC2494
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
1
85°C
0
–45°C, 25°C
–1
–2
16
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
INL (ppm OF VREF)
2
INL (ppm OF VREF)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
Noise Histogram
(2x Speed Mode)
1
85°C
0
–45°C, 25°C
–1
RMS = 0.85μV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
GAIN = 128
10
TA = 25°C
NUMBER OF READINGS (%)
3
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
8
6
4
–2
2
–3
–1.25
–0.75
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–0.75
2494 G28
1.0
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
GAIN = 128
0.2
1
0
194
192
190
188
186
180
5
–1
1
0
3
VIN(CM) (V)
2
4
5
2494 G31
220
–40
210
200
190
4
3.5
VCC (V)
4.5
5
5.5
2494 G34
160
–60
–80
–100
–120
170
0
90
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
180
50
75
2494 G33
REJECTION (dB)
OFFSET ERROR (μV)
OFFSET ERROR (μV)
100
0 15 30 45 60
TEMPERATURE (°C)
PSRR vs Frequency at VCC
(2x Speed Mode)
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
230
150
3
160
–45 –30 –15
6
0
240
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
2.5
190
Offset Error vs VREF
(2x Speed Mode)
250
2
200
2494 G32
Offset Error vs VCC
(2x Speed Mode)
200
210
170
182
4
220
180
184
3
2
VREF (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
230
OFFSET ERROR (μV)
196
OFFSET ERROR (μV)
RMS NOISE (μV)
0.8
240
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
TA = 25°C
198
188.6
Offset Error vs Temperature
(2x Speed Mode)
200
0.4
183.8
186.2
OUTPUT READING (μV)
2494 G30
Offset Error vs VIN(CM)
(2x Speed Mode)
0.6
181.4
2494 G29
RMS Noise vs VREF
(2x Speed Mode)
0
0
179
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–140
0
1
2
3
VREF (V)
4
5
2494 G35
1
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
2494 G36
2494fb
9
LTC2494
TYPICAL PERFORMANCE CHARACTERISTICS
PSRR vs Frequency at VCC
(2x Speed Mode)
RREJECTION (dB)
–20
–40
–60
0
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
–40 IN– = GND
FO = GND
–60 TA = 25°C
–20
REJECTION (dB)
0
PSRR vs Frequency at VCC
(2x Speed Mode)
–80
–80
–100
–100
–120
–120
–140
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2494 G37
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2494 G38
PIN FUNCTIONS
GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground current ﬂow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All eight pins must be connected to ground
for proper operation.
ADCINN (Pin 26): Negative ADC Input. Tie to the output
of a buffer/ampliﬁer driven by MUXOUTN or tie directly
to MUXOUTN.
NC (Pin 2): No Connection, this pin can be left ﬂoating
or tied to GND.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
COM (Pin 7): The common negative input (IN–) for all
single-ended multiplexer conﬁgurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
VIN = (IN+ – IN–) from –0.5 • VREF/Gain to 0.5 • VREF /Gain.
Outside this input range, the converter produces unique
over-range and under-range output codes.
CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be programmed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Used
to drive an external buffer/ampliﬁer or can be shorted
directly to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Tie to the output
of a buffer/ampliﬁer driven by MUXOUTP or tie directly
to MUXOUTP.
MUXOUTN (Pin 27): Negative Multiplexer Output. Used
to drive an external buffer/ampliﬁer or can be shorted
directly to ADCINN.
REF+ (Pin 29), REF– (Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage VREF = (REF+
– REF–) sets the full-scale range (–0.5 • VREF/Gain to 0.5
• VREF/Gain) for all input channels. When performing an
on-chip temperature measurement, the minimum value
of REF = 2V.
SDI (Pin 34): Serial Data Input. This pin is used to select the
gain, line frequency rejection mode, 1x or 2x speed mode,
temperature sensor, as well as the input channel. The serial
data input is applied under control of the serial clock (SCK)
during the data output/input operation. The ﬁrst conversion
following a new input or mode change is valid.
2494fb
10
LTC2494
PIN FUNCTIONS
FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When FO is
connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may
also be overridden by driving the FO pin with an external
clock in order to change the output rate and the digital
ﬁlter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin . In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain ﬂoating.
FUNCTIONAL BLOCK DIAGRAM
TEMP
SENSOR
VCC
INTERNAL
OSCILLATOR
MUXOUTP ADCINP
GND
–
CH0
CH1
CH15
COM
•
•
•
+
DIFFERENTIAL
3RD ORDER
ΔΣ MODULATOR
MUX
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF +
REF –
SERIAL
INTERFACE
SDI
SCK
SDO
CS
DECIMATING FIR
ADDRESS
2494 BD
MUXOUTN ADCINN
Figure 1. Functional Block Diagram
2494fb
11
LTC2494
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2494 TC01
2494 TC02
TIMING DIAGRAMS
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
CS
t1
SDO
t2
Hi-Z
Hi-Z
tKQMIN
t3
tKQMAX
SCK
t7
t8
SDI
2494 TD01
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK (SCK LOW with CS↓)
CS
t1
SDO
t2
Hi-Z
Hi-Z
t5
tKQMIN
t4
tKQMAX
SCK
t7
t8
SDI
2494 TD02
SLEEP
DATA IN/OUT
CONVERSION
2494fb
12
LTC2494
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2494 is a multi-channel, low power, delta-sigma,
analog-to-digital converter with an easy-to-use, 4-wire
interface and automatic differential input current cancellation. Its operation is made up of four states (See Figure 2).
The converter’s operating cycle begins with the conversion, followed by the sleep state, and ends with the data
input/output cycle. The 4-wire interface consists of serial
data output (SDO), serial clock (SCK), chip select (CS)
and serial data input (SDI).The interface, timing, operation
cycle, and data output format is compatible with Linear’s
entire family of ΔΣ converters.
Initially, at power up, the LTC2494 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS in HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indeﬁnitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the ﬁrst rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the ﬁrst rising edge of SCK, the
POWER UP
IN+= CH0, IN–= CH1
GAIN = 1, 50/60Hz,1X
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial data
output pin (SDO) under the control of the serial clock pin
(SCK). Data is updated on the falling edge of SCK allowing
the user to reliably latch data on the rising edge of SCK (See
Figure 3). The conﬁguration data for the next conversion
is also loaded into the device at this time. Data is loaded
from the serial data input pin (SDI) on each rising edge
of SCK. The data input/output cycle is concluded once 24
bits are read out of the ADC or when CS is brought HIGH.
The device automatically initiates a new conversion and
the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2494
offers several ﬂexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2494 data output has no latency, ﬁlter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input or
mode, is valid and accurate to the full speciﬁcations of
the device.
The LTC2494 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
CONVERT
SLEEP
CS = LOW
AND
SCK
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
2494 F02
Figure 2. LTC2494 State Transition Diagram
Easy Drive Input Current Cancellation
The LTC2494 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
2494fb
13
LTC2494
APPLICATIONS INFORMATION
transparently removes the differential input current. This
enables external RC networks and high impedance sensors to directly interface to the LTC2494 without external
ampliﬁers. The remaining common mode input current
is eliminated by either balancing the differential input
impedances or setting the common mode input equal to
the common mode reference (see Automatic Differential
Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling
signals to swing beyond ground or up to VCC. Moreover,
the cancellation does not interfere with the transparent
offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained
even with external RC networks.
Power-Up Sequence
The LTC2494 automatically enters an internal reset state
when the power supply voltage, VCC, drops below approximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection, and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channels IN+ = CH0 and
IN– = CH1 with simultaneous 50Hz/60Hz rejection 1x output
rate, and gain = 1. The ﬁrst conversion following a POR
cycle is accurate within the speciﬁcation of the device if
the power supply voltage is restored to (2.7V to 5.5V)
before the end of the POR interval. A new input channel,
rejection mode, speed mode, temperature selection, or
gain can be programmed into the device during this ﬁrst
data input/output cycle.
The LTC2494 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter output noise is determined by the thermal noise of the front
end circuits, and as such, its value in nano volts is nearly
constant with reference voltage. A decrease in reference
voltage will not signiﬁcantly improve the converter’s effective resolution. On the other hand, a decreased reference
will improve the converter’s overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute, common mode range for CH0 to CH15 and COM input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD projection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2494 converts the bipolar differential
input signal VIN = IN+ + IN– (where IN+ and IN– are the
selected input channels), from –FS = –0.5 • VREF/Gain to
+FS = 0.5 • VREF/Gain where VREF = REF+ – REF–. Outside
this range, the converter indicates the overrange or the
underrange condition using distinct output codes.
Signals applied to the input (CH0 to CH15, COM) may
extend 300mV below ground and above VCC. In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA input
leakage current will develop a 1ppm offset error on a 5k
resistor if VREF = 5V. This error has a very strong temperature dependency.
MUXOUT/ADCIN
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for the
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF–).
The output of the multiplexer (MUXOUT) and the input
to the ADC (ADCIN) can be used to perform input signal
conditioning on any of the selected input channels or simply shorted together for direct digitization. If an external
ampliﬁer is used, the LTC2494 automatically calibrates
both the offset and drift of this circuit and the Easy Drive
sampling scheme enables a wide variety of ampliﬁers to
be used.
2494fb
14
LTC2494
APPLICATIONS INFORMATION
In order to achieve optimum performance, if an external
ampliﬁer is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
conversion is complete, if CS is brought LOW, EOC will be
driven LOW indicating the conversion is complete and the
result is ready to be shifted out of the device.
Chip Select (CS)
SERIAL INTERFACE PINS
The LTC2494 transmits the conversion result, reads the
input conﬁguration, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface can be
used to access the converter status. During the data output
state, it is used to read the conversion result, program the
input channel, rejection frequency, speed multiplier, select
the temperature sensor and set the gain.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be conﬁgured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply ﬂoating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Speciﬁc
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB ﬁrst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once the
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the ﬁrst and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input
channel, rejection frequency, speed multiplier, gain, and to
access the integrated temperature sensor. Data is shifted
into the device during the data output/input state on the
rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2494 serial output stream is 24 bits long. The
ﬁrst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB ﬁrst. The
remaining 4 bits are always LOW.
Bit 23 (ﬁrst output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is HIGH-Z when CS is
HIGH.
2494fb
15
LTC2494
APPLICATIONS INFORMATION
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If the selected input (VIN = IN+ – IN–) is
greater than or equal to 0V, this bit is HIGH. If VIN < 0,
this bit is LOW.
Bit 20 (fourth output bit) is the most signiﬁcant bit (MSB)
of the result. This bit in conjunction with Bit 21 also provides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2494 Status Bits
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 • VREF/Gain
0
0
1
1
0V ≤ VIN < 0.5 • VREF/Gain
0
0
1
0
–0.5 • VREF/Gain ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF/Gain
0
0
0
0
Input Range
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB ﬁrst.
Bit 4 is the least signiﬁcant bit (LSB16).
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device, CS
must ﬁrst be driven LOW. EOC is seen at the SDO pin of
the device once CS is pulled LOW. `E`O`C changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the ﬁrst
rising edge of SCK. Bit 22 is shifted out of the device on
the ﬁrst falling edge of SCK. The ﬁnal data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF/Gain
to +FS = 0.5 • VREF /Gain. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
CS
1
2
3
4
5
1
0
EN
SGL
ODD
EOC
“0”
SIG
MSB
6
7
8
9
A2
A1
A0
EN2
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
24
SCK
(EXTERNAL)
DON'T CARE
SDI
SDO
Hi-Z
IM
FA
FB
Hi-Z
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
CONVERSION
SLEEP
DON'T CARE
BIT 9
DATA INPUT/OUTPUT
BIT 0
CONVERSION
2494 F03
Figure 3. Channel Selection, Conﬁguration Selection and Data Output Timing
2494fb
16
LTC2494
APPLICATIONS INFORMATION
Table 2. LTC2494 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
…
BIT 4
BITS 3 TO 0
VIN* ≥ FS**
0
0
1
1
0
0
0
…
0
0000
FS** – 1LSB
0
0
1
0
1
1
1
…
1
0000
0.5 • FS**
0
0
1
0
1
0
0
…
0
0000
0.5 • FS** – 1LSB
0
0
1
0
0
1
1
…
1
0000
0
0
0
1
0
0
0
0
…
0
0000
–1LSB
0
0
0
1
1
1
1
…
1
0000
–0.5 • FS**
0
0
0
1
1
0
0
…
0
0000
–0.5 • FS** – 1LSB
0
0
0
1
0
1
1
…
1
0000
–FS**
0
0
0
1
0
0
0
…
0
0000
VIN* < –FS**
0
0
0
0
1
1
1
…
1
0000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF /Gain.
INPUT DATA FORMAT
The LTC2494 serial input word is 16 bits long and contains
two distinct sets of data. The ﬁrst set (SGL, ODD, A2, A1,
A0) is used to select the input channel. The second set of
data (IM, FA, FB, SPD, GS2, GS1, GS0) is used to select
the frequency rejection, speed mode (1x, 2x), temperature
measurement, and gain.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 – CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
1x output rate (auto-calibration enabled), and gain = 1. The
ﬁrst conversion automatically begins at power up using this
default conﬁguration. Once the conversion is complete, a
new word may be written into the device.
The ﬁrst three bits shifted into the device consist of two
preamble bits and an enable bit. These bits are used to
enable the device conﬁguration and input channel selection. Valid settings for these three bits are 000, 100 and
101. Other combinations should be avoided. If the ﬁrst
three bits are 000 or 100, the following data is ignored
(don’t care) and the previously selected input channel and
conﬁguration remain valid for the next conversion.
If the ﬁrst three bits shifted into the device are 101, then
the next ﬁve bits select the input channel for the next
conversion cycle (see Table 3).
The ﬁrst input bit following the 101 sequence (SGL) determines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels
can be selected to form a differential input. For SGL = 1, one
of 16 channels is selected as the positive input. The negative
input is COM for all single ended operations. The remaining
4 bits (ODD, A2, A1, A0) determine which channel(s) is/are
selected and the polarity (for a differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
conﬁguration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter conﬁguration. This is useful in systems using
the same rejection/speed for all input channels and for
backward compatibility with the LTC2418/LTC2414 families
of delta sigma ADCs.
The second set of conﬁguration data can be loaded into the
device by setting EN2 = 1 (see Table 4). The ﬁrst bit (IM)
is used to select the internal temperature sensor. If IM = 1,
the following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next 2 bits (FA and FB) are used to set the rejection
frequency. The next bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the ﬁnal conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
up to 15Hz with no latency). When IM = 1 (temperature
measurement), SPD, GS2, GS1, GS0 will be ignored and
the device will operate in 1x mode. The ﬁnal 3 bits (GS2,
2494fb
17
LTC2494
APPLICATIONS INFORMATION
Table 3 Channel Selection
MUX ADDRESS
CHANNEL SELECTION
ODD/
SGL SIGN
A2
A1
A0
0
1
*0
0
0
0
0
IN+
IN–
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
2494fb
18
LTC2494
APPLICATIONS INFORMATION
Table 4. Converter Conﬁguration
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN SGL ODD A2 A1 A0 EN2
0
X
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Any
1
1
Input
Channel
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IM
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
FA
X
X
FB
X
X
Any
Rejection
Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SPD
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GS2 GS1 GS0
X
X
X
X
X
X
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Any
Speed
Any
Gain
X
X
X
X
GS1, GS0) are used to select the gain. The conﬁguration
remains valid until a new input word with EN = 1 (the ﬁrst
3 bits are 101) and EN2 = 1 is shifted into the device.
Rejection Mode (FA, FB)
The LTC2494 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated 4th order digital low pass ﬁlter, the LTC2494
rejects line frequency noise. In the default mode, the
LTC2494 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2494 can be
conﬁgured to reject 50Hz or 60Hz to better than 110dB.
Speed Mode (SPD)
Every conversion cycle, two conversions are combined to
remove the offset (default mode). This result is free from
offset and drift. In applications where the offset is not
critical, the auto-calibration feature can be disabled with
the beneﬁt of twice the output rate. While operating in the
X
X
X
X
X
X
X
X
X
X
X
X
CONVERTER CONFIGURATION
Keep Previous
Keep Previous
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 264, Autocalibration
External Input, Gain = 1, 2x Speed
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, Simultaneous 50Hz/60Hz Rejection
Temperature Input, 50Hz Rejection
Temperature Input, 60Hz Rejection
Reserved, Do Not Use
2x mode (SPD = 1), the linearity and full-scale errors are
unchanged from the 1x mode performance. In both the 1x
and 2x mode there is no latency. This enables input steps
or multiplexer changes to settle in a single conversion
cycle easing system overhead and increasing the effective
conversion rate. During temperature measurements, the 1x
mode is always used independent of the value of SPD.
GAIN (GS2, GS1, GS0)
The input referred gain of the LTC2494 is adjustable
from 1 to 256 (see Tables 5a and 5b). With a gain of 1,
the differential input range is ±VREF/2 and the common
mode input range is rail-to-rail. As the gain is increased,
the differential input range is reduced to ±0.5 • VREF/Gain
but the common mode input range remains rail-to-rail.
As the differential gain is increased, low level voltages
are digitized with greater resolution. At a gain of 256, the
LTC2494 digitizes an input signal range of ±9.76mV with
over 16,000 counts.
2494fb
19
LTC2494
APPLICATIONS INFORMATION
Table 5a. Performance vs Gain in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
4
8
16
32
64
128
256
Input Span
±2.5
±0.625
±0.312
±0.156
±78m
±39m
±19.5m
±9.76m
V
LSB
38.1
9.54
4.77
2.38
1.19
0.596
0.298
0.149
μV
65536
65536
65536
65536
65536
65536
32768
16384
Counts
Noise Free Resolution*
UNIT
Gain Error
5
5
5
5
5
5
5
8
Offset Error
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ppm of FS
μV
UNIT
Table 5b. Performance vs Gain in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN
Input Span
LSB
Noise Free Resolution*
1
2
4
8
16
32
64
128
±2.5
±1.25
±0.625
±0.312
±0.156
±78m
±39m
±19.5m
V
38.1
19.1
9.54
4.77
2.38
1.19
0.596
0.298
μV
65536
65536
65536
65536
65536
65536
45875
22937
Counts
Gain Error
5
5
5
5
5
5
5
5
Offset Error
200
200
200
200
200
200
200
200
ppm of FS
μV
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
Temperature Sensor
The LTC2494 includes an integrated temperature sensor.
The temperature sensor is selected by setting IM = 1.
During temperature readings, MUXOUTN/MUXOUTP
remains connected to the selected input channel. The
ADC internally connects to the temperature sensor and
performs a conversion.
The digital output is proportional to the absolute temperature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5μV/°C independent of VREF.
Slope calibration is not required if the reference voltage
(VREF) is known. A 5V reference has a slope of 2.45
LSBs16/°C. The temperature is calculated from the output
code (where DATAOUT16 is the decimal representation of
the 16-bit result) for a 5V reference using the following
formula:
TK = DATAOUT16/2.45 in Kelvin
If a different value of VREF is used, the temperature output
is:
If the value of VREF is not known, the slope is determined by
measuring the temperature sensor at a known temperature
TN (in °K) and using the following formula:
SLOPE = DATAOUT16/TN
This value of slope can be used to calculate further temperature readings using:
TK = DATAOUT16/SLOPE
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TC = TK – 273
SERIAL INTERFACE TIMING MODES
The LTC2494’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several ﬂexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (FO = LOW) or an external oscillator connected
to the FO pin. For each mode, the operating cycle, data
input format, data output format, and performance remain
the same. Refer to Table 6 for a summary.
TK = DATAOUT16 • VREF/12.25 in Kelvin
2494fb
20
LTC2494
APPLICATIONS INFORMATION
5
1020
VCC = 5V
VREF = 5V
960 SLOPE = 2.45 LSB /K
16
4
ABSOLUTE ERROR (°C)
3
DATAOUT16
800
640
480
320
2
1
0
–1
–2
–3
160
0
–4
0
100
200
300
TEMPERATURE (K)
–5
–55
400
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2494 F04
2494 F05
Figure 5. Absolute Temperature Error
Figure 4. Internal PTAT Digital Output vs Temperature
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
SCK
CONVERSION
DATA OUTPUT CONNECTION AND
SOURCE CYCLE CONTROL
CONTROL
WAVEFORMS
External SCK, Single Cycle
Conversion
External
CS and SCK
CS and SCK
Figures 6, 7
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 8
Internal SCK, Single Cycle
Conversion
Internal
CS↓
CS↓
Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 11
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the ﬁrst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the ﬁrst rising
edge). The channel selection and converter conﬁguration
mode will be used for the following conversion cycle. If
the input channel or converter conﬁguration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the ﬁrst rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK.
On the 24th falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
2494fb
21
LTC2494
APPLICATIONS INFORMATION
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2494
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF +
30
REF –
8
•
•
•
ANALOG
INPUTS
FO
15
16
•
•
•
23
7
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
24
SCK
(EXTERNAL)
SDI
DON'T CARE
IM
FA
FB
DON'T CARE
Hi-Z
SDO
Hi-Z
2494 F06
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
CONVERSION
SLEEP
BIT 12 BIT 11
BIT 10
BIT 9
DATA INPUT/OUTPUT
BIT 0
CONVERSION
Figure 6. External Serial Clock, Single Cycle Operation
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conﬁguration remains
unchanged. In order to program both the input channel
and converter conﬁguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
2494fb
22
LTC2494
APPLICATIONS INFORMATION
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
FO
LTC2494
0.1μF
29
REFERENCE
VOLTAGE
0.1V TO VCC
REF +
30
REF –
8
•
•
•
•
•
•
38
SCK
CH0
•
•
•
15
16
ANALOG
INPUTS
34
SDI
CH7
SDO
CH8
•
CS
4-WIRE
SPI INTERFACE
37
36
•
•
23
CH15
7
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
DON'T CARE
Hi-Z
2494 F07
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
CONVERSION
SLEEP
BIT 15
DATA INPUT/OUTPUT
CONVERSION
SLEEP
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
2.7V TO 5.5V
10μF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2494
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF +
30
REF –
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
3-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
24
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
IM
FA
SLEEP
DON'T CARE
2494 F08
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
CONVERSION
FB
BIT 12 BIT 11 BIT 10
DATA INPUT/OUTPUT
BIT 9
BIT 0
CONVERSION
Figure 8. External Serial Clock, 3-Wire Operation (CS = 0)
2494fb
23
LTC2494
APPLICATIONS INFORMATION
On the falling edge of EOC, the conversion result is loading into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and `E`O`C is
output to the SDO pin. EOC= 1 while the conversion is in
progress and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (FO is tied LOW),
the ﬁrst rising edge of SCK occurs 12μs (tEOCTEST = 12μs)
after the falling edge of CS. If FO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
If CS remains LOW longer than tEOCTEST, the ﬁrst rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be ﬂoating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
FO
LTC2494
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
REF +
SDI
30
REF –
SCK
8
•
•
•
15
16
ANALOG
INPUTS
•
•
•
VCC
29
23
7
34
CH0
•
•
•
CH7
SDO
CH8
•
CS
OPTIONAL
10k
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
<tEOCTEST
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
24
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
FB
DON'T CARE
Hi-Z
2494 F09
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
CONVERSION
SLEEP
BIT 12 BIT 11
DATA INPUT/OUTPUT
BIT 10
BIT 9
BIT 0
CONVERSION
Figure 9. Internal Serial Clock, Single Cycle Operation
2494fb
24
LTC2494
APPLICATIONS INFORMATION
After the 24th rising edge of SCK a new conversion automatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
unchanged. In order to program both the input channel
and converter conﬁguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling CS HIGH any time between the 1st rising edge and
the 24th falling edge of SCK (see Figure 10). On the rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conﬁguration remains
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is ﬂoating or driven HIGH.
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2494
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF +
30
REF –
8
•
•
•
ANALOG
INPUTS
FO
15
16
•
•
•
23
7
<tEOCTEST
VCC
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
OPTIONAL
10k
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
SLEEP
DON'T CARE
Hi-Z
2494 F10
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
CONVERSION
FB
BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
DATA INPUT/OUTPUT
CONVERSION
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Conﬁguration Selection
2494fb
25
LTC2494
APPLICATIONS INFORMATION
2.7V TO 5.5V
10µF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2494
0.1µF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF +
30
–
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
REF
VCC
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
OPTIONAL
10k
38
3-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
15
16
SPD
GS2
GS1
GS0
24
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
FB
2494 F11
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
BIT 12 BIT 11
DATA INPUT/OUTPUT
CONVERSION
DON'T CARE
BIT 10
BIT 9
BIT 0
CONVERSION
Figure 11. Internal Serial Clock, Continuous Operation
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has ﬁnished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the rising edge of SCK (including the ﬁrst rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is ﬂoating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2494’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. If CS goes HIGH before the time tEOCtest,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
2494fb
26
LTC2494
APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY
The LTC2494 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2494’s digital interface is easy to use. Its digital
inputs SDI, FO, CS, and SCK (in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as
100μs.
The digital input signal range is 0.5V to VCC – 0.5V. During
transitions, the CMOS input circuits draw dynamic current. For optimal performance, application of signals to
the serial data interface should be reserved for the sleep
and data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital interface and the external oscillator pin (FO) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difﬁcult when shared control lines are used and multiple
reﬂections occur.
Parallel termination near the input pin of the LTC2494 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depending on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, FO) remain static during the conversion cycle and
no degradation occurs. On the other hand, if an external
oscillator is used (FO driven externally) it is active during
the conversion cycle. Moreover, the digital ﬁlter rejection
is minimal at the clock rate applied to FO. Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
Driving the Input and Reference
The input and reference pins of the LTC2494 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simpliﬁed equivalent circuit is
shown in Figure 12.
When using the LTC2494’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant
is less then 580ns the errors introduced by the sampling
process are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low impedance source. In this case, complete settling occurs even
with large external bypass capacitors. The inputs (CH0 to
CH15, COM), on the other hand, are typically driven from
larger source resistances. Source resistances up to 10k
may interface directly to the LTC2494 and settle completely;
however, the addition of external capacitors at the input
terminals in order to ﬁlter unwanted noise (anti-aliasing)
results in incomplete settling.
The LTC2494 offers two methods of removing these errors.
The ﬁrst is automatic differential input current cancellation (Easy Drive) and the second is the insertion of buffer
between the MUXOUT and ADCIN pins, thus isolating the
input switching from the source resistance.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
2494fb
27
LTC2494
APPLICATIONS INFORMATION
IIN+
IN+
INPUT
MULTIPLEXER
INTERNAL
SWITCH
NETWORK
EXTERNAL
CONNECTION
100Ω
( )
I IN+
10k
MUXOUTP
ADCINP
AVG
(
I REF +
IIN–
IREF+
AVG
≈
AVG
VIN(CM) − VREF(CM)
=
(
0.5 • REQ
1.5VREF + VREF(CM) – VIN(CM)
0.5 • REQ
)–
VIN2
VREF • REQ
where :
100Ω
IN–
)
( )
= I IN–
VREF = REF + − REF −
10k
MUXOUTN
⎛ REF + – REF − ⎞
VREF(CM) = ⎜
⎟
⎜⎝
⎟⎠
2
ADCINN
EXTERNAL
CONNECTION
REF+
CEQ
12pF
10k
VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS
⎛ IN+ – IN− ⎞
VIN(CM) = ⎜
⎟
⎜⎝
⎟⎠
2
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz/60Hz MODE
(
IREF–
)
REQ = 0.833 • 1012 /fEOSC EXTERNAL OSCILLATOR
10k
REF–
2494 F12
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 12. LTC2494 Equivalent Analog Input Circuit
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns requied
for 1ppm accuracy. For example, a 10k bridge driving a
0.1μF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2494 uses a propriatary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
of buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current in the negative input (IIN–). Over the complete
conversion cycle, the average input current (IIN+ – IIN–)
is zero. While the differential input current is zero, the
common mode input current (IIN+ + IIN–)/2 is proportional
to the difference between the common mode input voltage (VIN(CM)) and the common mode reference voltage
(VREF(CM)).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com-
mon mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74μA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a ﬁxed offset
error but do not effect the linearity or full scale reading.
A 1% mismatch in a 1k source resistance leads to a 74μV
shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2494, leading
to little degradation in accuracy. Mismatches in source
2494fb
28
LTC2494
APPLICATIONS INFORMATION
impedances lead to gain errors proportional to the difference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will
remove this error.
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifer.
The LTC6078 is an excellent ampliﬁer for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2494 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op-amp output enabling stable operation.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA Max) results
in a small offset shift. A 1k source resistance will create a
1μV typical and a 10μV maximum offset voltage.
Reference Current
Automatic Offset Calibration of External Buffers/
Ampliﬁers
Similar to the analog inputs, the LTC2494 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
In addition to the Easy Drive input current cancellation,
the LTC2494 enables an external amplifer to be inserted
between the multiplexer output and the ADC input (see
Figure 13). This is useful in applications where balanced
source impedances are not possible. One pair of external
buffers/amplifers can be shared between all 17 analog
inputs. The LTC2494 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
combination of front end switching and digital processing. Since the external ampliﬁer is placed between the
For relatively small values of external reference capacitance (CREF < 1nF), the voltage on the sampling capacitor
settles for reference impedances of many kΩ (if CREF =
100pF up to 10k will not degrade the performance) (see
Figures 14, 15).
LTC2494
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
SDI
SCK
SDO
CS
2
–
1/2 LTC6078
3
6
1k
0.1μF
+
–
1/2 LTC6078
5
1
+
7
1k
0.1μF
2494 F13
Figure 13. External Buffers Provide High Impedance Inputs and Ampliﬁer Offsets are Automatically Cancelled.
2494fb
29
LTC2494
APPLICATIONS INFORMATION
90
60
50
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
400
+FS ERROR (ppm)
70
+FS ERROR (ppm)
500
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
80
20
300
CREF = 1μF, 10μF
CREF = 0.1μF
200
CREF = 0.01μF
10
100
0
–10
0
10
1k
100
RSOURCE (Ω)
10k
0
100k
200
0
600
400
RSOURCE (Ω)
800
1000
2494 F14
Figure 14. +FS Error vs RSOURCE at VREF (Small CREF)
2494 F16
Figure 16. +FS Error vs RSOURCE at VREF (Large CREF)
0
10
0
–20
–30
–100
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–FS ERROR (ppm)
–FS ERROR (ppm)
–10
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 FO = GND
TA = 25°C
–90
10
0
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
–400
1k
100
RSOURCE (Ω)
–500
10k
100k
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
1000
2494 F17
2494 F15
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01μF) full-scale and linearity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operating in simultaneous 50Hz/60Hz mode)(see Figures 16
and 17). If the input common mode voltage is equal to
the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100Ω of reference resistance
results (see Figure 18). In applications where the input
and reference common mode voltages are different, the
errors increase. A 1V difference in between common mode
input and common mode reference results in a 6.7ppm
INL error for every 100Ω of reference resistance.
Figure 17. –FS Error vs RSOURCE at VREF (Large CREF)
10
INL (ppm OF VREF)
Figure 15. –FS Error vs RSOURCE at VREF (Small CREF)
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
– 0.5
– 0.3
0.1
– 0.1
VIN/VREF (V)
0.3
0.5
2494 F18
Figure 18. INL vs Differential Input Voltage and Reference
Source Resistance for CREF > 1μF
2494fb
30
LTC2494
APPLICATIONS INFORMATION
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ﬁltering. Combined
with a large oversample ratio, the LTC2494 signiﬁcantly
simpliﬁes anti-aliasing ﬁlter requirements. Additionally,
the input current cancellation feature allows external low
pass ﬁltering without degrading the DC performance of
the device.
The SINC4 digital ﬁlter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures
19 and 20). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = FEOSC/20 when operating with an external oscillator
of frequency FEOSC.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
Figure 20. Input Normal Mode Rejection, Internal Oscillator
and 60Hz Rejection Mode
0
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2494 F19
Figure 19. Input Normal Mode Rejection, Internal Oscillator
and 50Hz Rejection Mode
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
Figure 21. Input Normal Mode Rejection at DC
0
–40
0
2494 F21
–10
–30
fN = fEOSC/5120
–10
0
–20
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2494 F20
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
When using the internal oscillator, the LTC2494 is designed
to reject line frequencies. As shown in Figure 21, rejection nulls occur at multiples of frequency fN, where fN is
determined by the input control bits FA and FB (fN = 50Hz
or 60Hz or 55Hz for simultaneous rejection). Multiples of
the modulator sampling rate (fS = fN • 256) only reject noise
to 15dB (see Figure 22), if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
INPUT NORMAL MODE REJECTION (dB)
Normal Mode Rejection and Anti-aliasing
0
INPUT NORMAL MODE REJECTION (dB)
In addition to the reference sampling charge, the reference
ESD projection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100Ω reference
resistance will create a 0.5μV full scale error.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2494 F22
Figure 22. Input Normal Mode Rejection at fS = 256 • fN
2494fb
31
LTC2494
APPLICATIONS INFORMATION
Using the 2x speed mode of the LTC2494 alters the rejection characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 28 and 29. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 30).
NORMAL MODE REJECTION (dB)
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2494 third
order modulator resolves this problem and guarantees
stability with input signals 150% of full-scale. In many
industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted volt
level error sources with several volts of peak-to-peak
noise. Figures 26 and 27 show measurement results for
the rejection of a 7.5V peak-to-peak noise source (150%
of full scale) applied to the LTC2494. From these curves,
it is shown that the rejection performance is maintained
even in extremely noisy environments.
0
MEASURED DATA
CALCULATED DATA
–20
–40
–80
–100
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2494 F23
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
0
MEASURED DATA
CALCULATED DATA
–20
–40
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2494 F24
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
An increase in fEOSC over the nominal 307.2kHz will translate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection.
When using the integrated temperature sensor, the internal
NORMAL MODE REJECTION (dB)
When using its internal oscillator, the LTC2494 produces up
to 15 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insigniﬁcantly short. When
operating with an external conversion clock (FO connected
to an external oscillator), the LTC2494 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
– 60
0
Output Data Rate
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
– 60
–120
NORMAL MODE REJECTION (dB)
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 23, 24,
and 25. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
– 60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2494 F25
Figure 25. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
oscillator should be used (FO = 0) or an external oscillator
applied to FO, fEOSC, should be set to 307.2kHz Max.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
2494fb
32
LTC2494
APPLICATIONS INFORMATION
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
– 60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2494 F26
0
INPUT NORMAL REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
–20
–40
–60
–80
–100
–120
0
Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
8fN
2494 F28
Figure 28. Input Normal Mode Rejection 2x Speed Mode
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
0
–40
– 60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2494 F27
Figure 27. Measure Input Normal Mode Rejection vs Input
Frequency With input Perturbation of 150% (50Hz Notch)
INPUT NORMAL REJECTION (dB)
NORMAL MODE REJECTION (dB)
fN
–20
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
2494 F29
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full scale errors, and
decreased resolution (see Figures 31 to 38).
Figure 29. Input Normal Mode Rejection 2x Speed Mode
–70
NORMAL MODE REJECTION (dB)
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
–80
NO AVERAGE
–90
–100
–110
WITH
RUNNING
AVERAGE
–120
–130
–140
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2494 F30
Figure 30. Input Normal Mode Rejection 2x Speed Mode with
and Without Running Averaging
2494fb
33
LTC2494
APPLICATIONS INFORMATION
40
3000
30
TA = 85°C
20
10
0
–500
2500
TA = 85°C
2000
–10
1500
TA = 25°C
1000
TA = 85°C
–2000
–2500
–3500
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F31
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F33
Figure 33.–FS Error vs Output Data
Rate and Temperature
Figure 32. +FS Error vs Output Data
Rate and Temperature
20
18
TA = 25°C, 85°C
RESOLUTION (BITS)
14
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
12
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
16
TA = 25°C
TA = 85°C
14
12 VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F34
VIN(CM) = VREF(CM)
VIN = 0V
15 FO = EXT CLOCK
TA = 25°C
10
VCC = VREF = 5V
5
0
–5
VCC = 5V, VREF = 2.5V
–10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F36
2494 F35
Figure 35. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
18
18
16
16
VCC = 5V, VREF = 2.5V, 5V
14
VIN(CM) = VREF(CM)
12 VIN = 0V
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F37
Figure 37. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
RESOLUTION (BITS)
RESOLUTION (BITS)
Figure 34. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
OFFSET ERROR (ppm OF VREF)
18
16
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
2494 F32
Figure 31. Offset Error vs Output Data
Rate and Temperature
RESOLUTION (BITS)
TA = 25°C
–3000
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
–1000
–1500
500
TA = 25°C
0
0
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
–FS ERROR (ppm OF VREF)
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
Figure 36. Offset Error vs Output Data
Rate and Reference Voltage
VCC = VREF = 5V
VCC = 5V, VREF = 2.5V
14
VIN(CM) = VREF(CM)
VIN = 0V
12 REF– = GND
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2494 F38
Figure 38. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
2494fb
34
LTC2494
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.15 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
5.00 ± 0.10
(2 SIDES)
3.15 ± 0.10
(2 SIDES)
0.75 ± 0.05
0.00 – 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
37 38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.40 ± 0.10
0.200 REF 0.25 ± 0.05
0.200 REF
0.00 – 0.05
0.75 ± 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.50 BSC
R = 0.115
TYP
(UH) QFN 0205
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2494fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2494
TYPICAL APPLICATION
External Buffers Provide High Impedance Inputs and Ampliﬁer Offsets are Automatically Cancelled.
LTC2494
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
SDI
SCK
SDO
CS
2
–
1/2 LTC6078
3
6
1k
0.1μF
+
–
1/2 LTC6078
5
1
7
1k
0.1μF
+
2494 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2413
24-Bit, No Latency ΔΣ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ΔΣ ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
LTC2440
High Speed, Low Noise 24-Bit ΔΣ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2480
Pin Compatible with LTC2482/LTC2484
Pin Compatible with LTC2483/LTC2485
LTC2482
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, I2C
Interface, Programmable Gain, and Temperature Sensor
16-Bit ΔΣ ADC with Easy Drive Inputs
LTC2483
16-Bit ΔΣ ADC with Easy Drive Inputs, and I2C Interface
Pin Compatible with LTC2481/LTC2485
LTC2484
24-Bit ΔΣ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
LTC2485
24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface, and
LTC2481
LTC2486
LTC2496
LTC2498
Pin Compatible with LTC2480/LTC2484
Pin Compatible with LTC2481/LTC2483
Temperature Sensor
16-Bit 2-/4-Channel ΔΣ ADC with PGA and Temperature Sensor Pin Compatible with LTC2492/LTC2488
16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current
Cancellation
24-Bit ΔΣ ADC with SPI Interface and Temperature Sensor
Pin Compatible with LTC2494/LTC2449/LTC2498
Pin Compatible with LTC2494/LTC2496/LTC2449
2494fb
36 Linear Technology Corporation
LT 1008 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007

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