LX5261 ® TM 27-Line LVD SCSI Source/Sink Regulator P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION WWW . Microsemi .C OM each capable of sourcing / sinking 200mA, along with a buffered 1.3V output for DIFSENS signaling. The LX5261 features on-chip trimming of the internal voltage enabling precise output voltages; typically +/- 1% of its specified value. Thermal Shutdown and Current Limiting is integrated onchip. The LX5261 is available in the 16pin SOIC (DP) package. The LX5261 is a source/sink regulator designed to provide the correct reference voltages and bias currents for SCSI LVD applications. With the proper LVD termination network (475Ω, 121Ω, 475Ω), the LX5261 assures that LVD performance is compliant to the SPI-2 (Ultra2), SPI3 (Ultra160) and SPI-4 (Ultra320) specification. The LX5261 provides two fixed regulated outputs (1.75V and 0.75V) Compliant with SPI-2 (Ultra2), SPI-3 (Ultra160), and SPI-4 (Ultra320) 2.7V to 5.25V Operation 200mA Source/Sink Capability DIFSENS Line Driver Current Limit and Thermal Protection Pin Compatible With Unitrode UCC561 IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com TYPICAL APPLICATION 1.3V Reference VTERM 2.7V to 5.25V + - 2 1.3V +/- 0.1V 7 DIFSENS 4.7uF 1.75V Reference + - 1.75V +/- 0.05V 200mA source/sink 6 475 1% VOUT1 L1121 1% 4.7uF 0.75V Reference GND + - 4 0.75V +/- 0.05V 200mA source/sink 3 475 1% VOUT2 L1+ 27 LVD Pairs 4.7uF 475 1% L27- 475 1% 121 1% L27+ LX5261 PACKAGE ORDER INFO SOIC DP 16-Pin TA (°C) RoHS Compliant / Pb-free Transition DC: 0440 0 to 70 LX5261CDP Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX5261CDP-TR) Copyright © 2000 Rev. 1.0c, 2005-02-08 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX5261 ® TM 27-Line LVD SCSI Source/Sink Regulator P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS PACKAGE PIN OUT Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. N/C 1 16 N/C VTERM 2 15 N/C VOUT2 3 14 N/C GND 4 13 HSGND HSGND 5 12 HSGND VOUT1 6 11 N/C DIFSENS 7 10 N/C N/C 8 9 N/C THERMAL DATA WWW . Microsemi .C OM Term Power (VTERM) .........................................................................................................6V Operating Junction Temperature..................................................................................... 150°C Storage Temperature Range..............................................................................-65°C to 150°C RoHS / Pb-freePeak Package Solder Reflow Temperature (40 second maximum exposure) ........................................................................ 260°C (+0, -5) DP PACKAGE DP (Top View) NC – No Internal Connection 16-Pin SOIC THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 111.8 °C/W RoHS / Pb-free 100% Matte Tin Lead Finish Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. θJA can vary significantly depending on mounting technique. (See Application Notes Section: Thermal considerations) FUNCTIONAL PIN DESCRIPTION PIN NAME DESCRIPTION VOUT1 1.75V Regulated Output. Capable of sourcing/sinking 200mA. VOUT2 0.75V Regulated Output. Capable of sourcing/sinking 200mA. Power supply pin for terminator. Connect to SCSI bus VTERM. Usually decoupled by one 4.7µF low-ESR capacitor. It is absolutely necessary to connect this pin to the VTERM DIFSENS HSGND Copyright © 2000 Rev. 1.0c, 2005-02-08 1.3V buffered output for DIFSENS signaling. Regulator ground pin. Connect to ground. Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a heat sink only, and not a true ground connection. It is recommended that these pins be connected to ground, but can be left floating. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 PACKAGE DATA GND decoupling capacitor through a very low impedance (big traces to PCB). Keeping distances very short from the decoupling capacitors is somewhat layout dependent and some applications may benefit from high frequency decoupling with 0.1µF capacitors at VTERM pin. LX5261 27-Line LVD SCSI Source/Sink Regulator ® TM P RODUCTION D ATA S HEET Parameter Symbol VTERM LX5261 Typ Units Max VTERM 2.7 5.25 0 5.0 V TJ 0 70 °C Signal Line Voltage Operating Junction Temperature Min WWW . Microsemi .C OM RECOMMENDED MAX OPERATING CONDITIONS V ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C, and VTERM = 3.3V. Parameter ` ` Symbol Test Conditions Min LX5261 Typ Max 35 40 mA 5.25 V Units TERMPWR Section VTERM Supply Current ITERM VTERM Voltage VTERM No Load 2.7 Regulator Section 1.75V Regulator VREG1 -125mA < IOUT < 125mA, 2.7V < VIN < 5.25V 1.7 1.75 1.8 V 1.3V Regulator VDIFS DIFSENS; No Load 1.2 1.3 1.4 V 0.75V Regulator VREG2 -125mA < IOUT < 125mA, 2.7V < VIN < 5.25V 0.7 0.75 1.75V Regulator Source Current ISRC1 VOUT = 1.25V 1.75V Regulator Sink Current ISNK1 VOUT = 2.25V 1.75V Source Current Limit 0.8 V -200 mA 200 mA -700 mA 1.75V Sink Current Limit 700 mA mA 1.3V Regulator Source Current IDIFS_SRC DIFSENS; 0V -5 -15 1.3V Regulator Sink Current IDIFS_SNK DIFSENS = 2.4V 50 200 µA -200 mA 0.75V Regulator Source Current ISRC2 VOUT = 0.25V 0.75V Regulator Sink Current ISNK2 VOUT = 1.25V 0.75V Source Current Limit 200 mA -700 mA 0.75V Sink Current Limit 700 mA ELECTRICALS Copyright © 2000 Rev. 1.0c, 2005-02-08 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 LX5261 27-Line LVD SCSI Source/Sink Regulator ® TM P RODUCTION D ATA S HEET 1.3V Reference 1.3V +/- 0.1V + VTERM 2 WWW . Microsemi .C OM BLOCK DIAGRAM 7 DIFSENS - 1.75V Reference 1.75V +/- 0.05V 200mA source/sink + 6 VOUT1 GND 4 0.75V Reference 0.75V +/- 0.05V 200mA source/sink + 3 VOUT2 - Figure 1 – LX5261 Block Diagram APPLICATION INFORMATION LVD SCSI with Resistor Stack The LX5261 is used with a LVD resistor network (475Ω, 121Ω, 475Ω) to meet LVD SCSI performance. Connecting the top side of the LVD resistor network to the 1.75V regulated output (VREG1, pin 6), and the bottom side of the LVD resistor network to the 0.75 regulated output (VREG2, pin 3) provides the correct bias voltage, differential impedance, common mode differential impedance, and common mode voltage required by the SPI-2 through SPI-4 SCSI specification (see Figure 2. below). The LX5261 is designed to drive up to 27 LVD pairs. + 1.75V +/- 0.05V 200mA source/sink 6 VOUT1 27 475 1% Ln- Units 107.3 100 to 110 ohm Differential Bias Voltage 112.9 100 to 125 mV Common Mode Impedance 237 100 to 300 ohm Common Mode Voltage 1.25 1.2 to 1.3 V Parameter 4.7uF + 0.75V +/- 0.05V 200mA source/sink 3 VOUT2 4.7uF 121 1 of 27 1% LVD Pairs 27 475 1% LX5261 BLOCK DIAGRAM SCSI Standard Differential Impedance - Ln+ Figure 2 – LX5261 with LVD Resistor Stack Copyright © 2000 Rev. 1.0c, 2005-02-08 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 4 LX5261 ® TM 27-Line LVD SCSI Source/Sink Regulator P RODUCTION D ATA S HEET DP WWW . Microsemi .C OM MECHANICAL DRAWINGS 16-Pin Small Outline Package (SOIC) Narrow Body F B 1 2 P 3 D G A L C K Dim M INCHES MIN MAX 0.385 0.394 0.150 0.158 0.053 0.069 0.014 0.018 0.030 0.050 BSC 0.007 0.010 0.004 0.010 0.189 0.205 0 8 0.228 0.244 0.004 MECHANICALS A B C D F G J K L M P *LC MILLIMETERS MIN MAX 9.78 10.01 3.81 4.01 1.35 1.75 0.35 0.46 0.77 1.27 BSC 0.19 0.25 0.10 0.25 4.82 5.21 0 8 5.79 6.20 0.10 J Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm (.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2000 Rev. 1.0c, 2005-02-08 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 LX5261 TM ® 27-Line LVD SCSI Source/Sink Regulator P RODUCTION D ATA S HEET WWW . Microsemi .C OM NOTES NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2000 Rev. 1.0c, 2005-02-08 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6