INFINEON ICB1FL02G

Datash eet Version 1.2, F ebruary 2006
ICB1FL02G
Smart Ballast Control IC for
Fluorescent Lamp Ballasts
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
ICB1FL02G
Revision History:
2006-02-08
Previous Version:
2005-06-06 (ICB1FL01G)
Page
Subjects (major changes since last revision)
19
Min Duration of EOL1
25
Preheating Time updated
26
EOL Current Threshold, AC & DC
Datasheet
Edition 2006-02-08
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ICB1FL02G
Smart Ballast Control IC for
Fluorescent Lamp Ballasts
Product Highlights
• Lowest Count of external Components
• HV-Driver with coreless Transformer Technology
• Improved Reliability and minimized Spread due to
digital and optimized analog control functions
Description
Features PFC
•
•
•
•
PG-DSO-18-1
Discontinuous Conduction Mode PFC
Integrated Compensation of PFC Control Loop
Adjustable PFC Current Limitation
Adjustable PFC Bus Voltage
LVS1
HSGND
LSGD
LSCS
RF P H
RF R U N
VCC
GN D
PFCCS
HSVCC
RE S
PFCVS
HSGD
RT P H
PFCGD
IC B 1 F L 02 G
PFCZCD
90 ... 270 V AC
LVS2
The Smart Ballast IC is designed to control a Fluorescent
Lamp Ballast including a Discontinuous Conduction
Mode Power Factor Correction (PFC), a lamp Inverter
Control and a High Voltage Level Shift Half-Bridge
Driver.
Features Lamp Ballast Inverter
The application requires a minimum of external
• Supports Restart after Lamp Removal and End-of- components. There are integrated low pass filters and an
internal compensation for the PFC voltage loop control.
Life Detection in Multi-Lamp Topologies
Preheating time is adjustable by a single resistor only in
• End-of-Life (EOL) detected by adjustable +/the range between 0 and 2000ms. In the same way the
Thresholds of sensed lamp voltage
• Rectifier Effect detected by ratio of +/- Amplitude of preheating frequency and run frequency are set by
resistors only. The control concept covers requirements
Lamp Voltage
• Detection of different capacitive Mode Operations for T5 lamp ballasts such as detection of end-of-life and
detection of capacitive mode operation and other
• Adjustable Inverter Overcurrent Shutdown
• Self-adaption of Ignition Time from 40ms to 235ms protection measures even in multilamp topologies.
• Parameters adjustable by Resistors only
ICB1FL02G is easy to use and easy to design and
• Pb-free lead plating; RoHS compliant
therefore a basis for a cost effective solution for
fluorescent lamp ballasts.
Type
Package
ICB1FL02G
PG-DSO-18-1
Datasheet Version 1.2
3
February 2006
ICB1FL02G
Table of Contents
Page
1
1.1
1.2
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration PG-DSO-18-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3
3.1
3.2
3.3
3.4
3.5
3.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PFC Preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Detection of End-of-Life and Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . .14
Detection of capacitive mode operating conditions . . . . . . . . . . . . . . . . . . .15
Interruption of Operation and Restart after Lamp Removal . . . . . . . . . . . . .16
4
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6
6.1
6.2
6.3
6.3.1
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.3
6.3.3.1
6.3.3.2
6.3.3.3
6.3.3.4
6.3.3.5
6.3.3.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PFC Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PFC Current Sense (PFCCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PFC Zero Current Detector (PFCZCD) . . . . . . . . . . . . . . . . . . . . . . . .23
PFC Bus Voltage Sense (PFCVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PFC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PFC Gate Drive (PFCGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Inverter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Inverter Control (RFRUN, RFPH, RTPH) . . . . . . . . . . . . . . . . . . . . . .25
Inverter Low Side Current Sense (LSCS) . . . . . . . . . . . . . . . . . . . . . .25
Restart after Lamp Removal (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Lamp Voltage Sense (LVS1, LVS2) . . . . . . . . . . . . . . . . . . . . . . . . . .26
Inverter Low Side Gate Drive (LSGD) . . . . . . . . . . . . . . . . . . . . . . . . .27
Inverter High Side Gate Drive (HSGD) . . . . . . . . . . . . . . . . . . . . . . . .28
7
7.1
7.2
7.3
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Operating Behaviour of a Ballast for a single Fluorescent Lamp . . . . . . . . .29
Design Equations of a Ballast Application . . . . . . . . . . . . . . . . . . . . . . . . . .30
Multilamp Ballast Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Datasheet Version 1.2
4
February 2006
ICB1FL02G
Pin Configuration and Description
1
Pin Configuration and Description
1.1
Pin Configuration PG-DSO-18-1
Pin
Symbol
Function
1
LSCS
Low side current sense (inverter)
2
LSGD
Low side gate drive (inverter)
3
VCC
Supply voltage
4
GND
Controller ground
5
PFCGD
PFC gate drive
6
PFCCS
PFC current sense
7
PFCZCD PFC zero current detector
8
PFCVS
PFC voltage sense
9
RFRUN
Set R for run frequency
10
RFPH
Set R for preheating frequency
11
RTPH
Set R for preheating time
12
RES
Restart after lamp removal
13
LVS1
Lamp voltage sense 1
14
LVS2
Lamp voltage sense 2
15
n.e.
Not existing
16
n.e.
Not existing
17
HSGND
High side ground
18
HSVCC
High side supply voltage
19
HSGD
High side gate drive
20
HSGND
High side ground
1
20
HSGND
LSGD
2
19
HSGD
VCC
3
18
HSVCC
GND
4
17
HSGND
PFCGD
5
PFCCS
6
PFCZCD
7
PFCVS
ICB1FL02G
LSCS
1.2
LSCS (Low side current sense, Pin 1)
This pin is directly connected to the shunt resistor
which is located between the Source terminal of the
low-side MOSFET of the inverter and ground.
Internal clamping structures and filtering measures
allow for sensing the Source current of the low-side
inverter MOSFET without additional filter components.
There is a first threshold of 0,8V, which provides a
couple of increasing steps of frequency during ignition
mode, if exceeded by the sensed current signal for a
time longer than 250ns. If the sensed current signal
exceeds a second threshold of 1,6V for longer than
400ns during all operating modes, a latched shut down
of the IC will be the result.
LSGD (Low side gate drive, Pin 2)
The Gate of the low-side MOSFET in a half-bridge
inverter topology is controlled by this pin. There is an
active L-level during UVLO (undervoltage lockout) and
a limitation of the max. H-level at 11V during normal
operation. Turning on the MOSFET softly (with reduced
diDRAIN/dt), the Gate drive voltage rises within 220ns
from L-level to H-level. The fall time of the Gate drive
voltage is less than 50ns in order to turn off quickly.
This measure produces different switching speeds
during turn-on and turn-off as it is usually achieved with
a diode in parallel to a resistor in the Gate drive loop. It
is recommended to use a resistor of about 15Ohm
between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor. The
dead time between LSGD signal and HSGD signal is
1800ns typically.
VCC (Supply voltage, Pin 3)
This pin provides the power supply of the ground
related section of the IC. There is a turn-on threshold at
14V and an UVLO threshold at 10,5V. Upper supply
voltage level is 17,5V. There is an internal zener diode
clamping Vcc at 16V (2mA typically). The zener current
is internally limited to 5mA max. For higher current
levels an external zener diode is required. Current
consumption during UVLO and during fault mode is
less than 150µA. A ceramic capacitor close to the
supply and GND pin is required in order to act as a lowimpedance power source for Gate drive and logic
signal currents.
16
15
14
LVS2
8
13
LVS1
RFRUN
9
12
RES
RFPH
10
11
RTPH
GND (Ground, Pin 4)
This pin is connected to ground and represents the
ground level of the IC for supply voltage, Gate drive
and sense signals.
PG-DSO-18-1 (300mil)
Datasheet Version 1.2
Pin Description
5
February 2006
ICB1FL02G
Pin Configuration and Description
and source current of the sense pin, when the voltage
of the ZCD winding exceeds the internal clamping
levels (6,3V and -2,9V @ 4mA) of the IC.
If the sensed level of the ZCD winding is not sufficient
(e.g. during start-up), an internal start-up timer will
initiate a new cycle every 40µs after turn-off of the PFC
Gate drive.
PFCGD (PFC gate drive, Pin 5)
The Gate of the MOSFET in the PFC preconverter
designed in boost topology is controlled by this pin.
There is an active L-level during UVLO and a limitation
of the max. H-level at 11V during normal operation.
Turning on the MOSFET softly (with a reduced diDRAIN/
dt), the Gate drive voltage rises within 220ns from Llevel to H-level. The fall time of the Gate voltage is less
than 50ns in order to turn off quickly. A resistor of about
10Ohm between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor is
recommended.
The PFC section of the IC controls a boost converter as
a PFC preconverter in discontinuous conduction mode
(DCM). Typically the control starts with Gate drive
pulses with an on-time of 1µs increasing up to 24µs and
a off-time of 40µs. As soon as a sufficient ZCD (zero
current detector) signal is available, the operating
mode changes from a fixed frequent operation to an
operation with variable frequency. During rated and
medium load conditions we get an operation with
critical conduction mode (CritCM), that means
triangular shaped currents in the boost converter choke
without gaps when reaching the zero level and variable
operating frequency. During light load (detected by the
internal error amplifier) we get an operation with
discontinuous conduction mode (DCM), that means
triangular shaped currents in the boost converter choke
with gaps when reaching the zero level and variable
operating frequency in order to avoid steps in the
consumed line current.
PFCVS (PFC voltage sense, Pin 8)
The intermediate circuit voltage (bus voltage) at the
smoothing capacitor is sensed by a resistive divider at
this pin. The internal reference voltage for rated bus
voltage is 2,5V. There are further thresholds at 0,375V
(15% of rated bus voltage), 1,83V (73% of rated bus
voltage) and 2,725V (109% of rated bus voltage) for
detecting open control loop, undervoltage and
overvoltage.
RFRUN (Set R for run frequency, Pin 9)
A resistor from this pin to ground sets the operating
frequency of the inverter during run mode. Typical run
frequency range is 20kHz to 100kHz. The set resistor
RRFRUN can be calculated based on the run frequency
fRUN according to the equation
R
RFPH (Set R for preheating frequency, Pin 10)
A resistor from this pin to ground sets together with the
resistor at pin 9 the operating frequency of the inverter
during preheat mode. Typical preheat frequency range
is run frequency (as a minimum) to 150kHz. The set
resistor RRFPH can be calculated based on the preheat
frequency fPH and the resistor RRFRUN according to the
equation:
R RFRUN
R
= -------------------------------------------------RFPH
f PH ⋅ R RFRUN
---------------------------------------- – 1
8
5 ⋅ 10 ΩHz
PFCCS (PFC current sense, Pin 6)
The voltage drop across a shunt resistor located
between Source of the PFC MOSFET and GND is
sensed with this pin. If the level exceeds a threshold of
1V for longer than 260ns the PFC Gate drive is turned
off as long as the ZCD (zero current detector) enables
a new cycle. If there is no ZCD signal available within
40µs after turn-off of the PFC Gate drive, a new cycle
is initiated from an internal start-up timer.
The total value of both resistors RRFPH and RRFRUN
switched in parallel should not be less than 3,3kOhm.
PFCZCD (PFC zero current detection, Pin 7)
This pin senses the point of time when the current
through the boost inductor becomes zero during offtime of the PFC MOSFET in order to initiate a new
cycle. The moment of interest appears when the
voltage of the separate ZCD winding changes from
positive to negative level which represents a voltage of
zero at the inductor windings and therefore the end of
current flow from lower input voltage level to higher
output voltage level. There is a threshold with
hysteresis, for increasing voltage a level of 1,5V, for
decreasing voltage a level of 0,5V, that detects the
change of inductor voltage. A resistor connected
between ZCD winding and sense input limits the sink
Datasheet Version 1.2
8
5 ⋅ 10 ΩHz
= ----------------------------RFRUN
f
RUN
RTPH (Set R for preheating time, Pin 11)
A resistor from this pin to ground sets the preheating
time of the inverter during preheat mode. A set resistor
range from zero to 18kOhm corresponds to a range of
preheating time from zero to 2000ms subdivided in 127
steps.
RES (Restart after lamp removal, Pin 12)
A source current out of this pin via resistor and filament
to ground monitors the existence of the low-side
filament of the fluorescent lamp for restart after lamp
6
February 2006
ICB1FL02G
Pin Configuration and Description
During run mode the lamp voltage is sensed by the AC
current fed into this pin via resistors. Exceeding one of
the two thresholds of either +215µA or -215µA cycle by
cycle for longer than 610µs, the interpretation of this
event is a failure due to EOL1 (end-of-life). A rectifier
effect (EOL2) is assumed if the ratio of the sequence of
positive and negative amplitudes is above 1,15 or
below 0,85 for longer than 500ms. A failure due to
EOL1 or EOL2 changes the operating mode from run
mode into a latched fault mode that stops the operation
until a reset occurs by lamp removal or by cycle of
power.
EOL1 and EOL2 require an AC current with
zerocrossings at LVS-Pin for a reliable detection. A DC
current at LVS-Pin results in a definite turn-off action
acc. to EOL1 only if the sensed current exceeds the
threshold ILVSEOLDC= +/-175µA (typically).
If the functionality of this pin is not required (e.g. for
single lamp designs) it can be disabled by connecting
this pin to ground.
removal. A capacitor from this pin directly to ground
eliminates a superimposed AC voltage that is
generated as a voltage drop across the low-side
filament. With a second sense resistor the filament of a
paralleled lamp can be included into the lamp removal
sense.
During typical start-up with connected filaments of the
lamp a current source IRES3 (20µA) is active as long as
Vcc> 10,5V and VRES< VRESC1 (1,6V). An open Lowside filament is detected, when VRES> VRESC1. Such a
condition will prevent the start-up of the IC. In addition
the comparator threshold is set to VRESC2 (1,3V) and
the current source changes to IRES4 (17µA). Now the
system is waiting for a voltage level lower than VRESC2
at the RES-Pin that indicates a connected low-side
filament, which will enable the start-up of the IC.
An open high-side filament is detected when there is no
sink current ILVSsink (15µA) into both of the LVS-Pins
before the VCC start-up threshold is reached. Under
these conditions the current source at the RES-Pin is
IRES1 (41µA) as long as Vcc> 10,5V and VRES< VRESC1
(1,6V) and the current source is IRES2 (34µA) when the
threshold has changed to VRESC2 (1,3V). In this way the
detection of the high-side filament is mirrored to the
levels on the RES-Pin.
Finally there is a delay function implemented at the
RES-Pin. When a fault condition happens e.g. by an
end-of-life criteria the inverter is turned-off. In some
topologies a transient AC lamp voltage may occur
immediately after shut down of the Gate drives which
could be interpreted as a lamp removal. In order to
generate a delay for the detection of a lamp removal
the capacitor at the RES-Pin is charged by the IRES3
(20µA) current source up to the threshold VRESC1 (1,6V)
and discharged by an internal resistor RRESdisch , which
operates in parallel to the external sense resistor at this
pin, to the threshold VRESC3 (0,375V). The total delay
amounts to 32 of these cycles, which corresponds to a
delay time between 30ms to 100ms dependent on
capacitor value.
In addition this pin is applied to sense capacitive mode
operation by use of a further capacitor connected from
this pin to the nod of the high-side MOSFET’s Source
terminal and the low-side MOSFET’s Drain terminal.
The sense capacitor and the filter capacitor are acting
as a capacitive voltage divider that allows for detecting
voltage slopes versus timing sequence and therefore
indicating capacitive mode operation. A typical ratio of
the capacitive divider is 410V/2,2V which results in the
capacitor values e.g. of 10nF and 53pF (56pF).
LVS2 (Lamp voltage sense 2, Pin 14)
Same functionality as LVS1 (pin 13) for monitoring a
paralleled lamp circuit.
HSGND (High side ground, Pin 17)
This pin is connected to the Source terminal of the
high-side MOSFET, which is also the nod of high-side
and low-side MOSFET. This pin represents the floating
ground level of the high-side driver and high-side
supply.
HSVCC (High side supply voltage, Pin 18)
This pin provides the power supply of the high-side
ground related section of the IC. An external capacitor
between pin 15 and 16 acts like a floating battery which
has to be recharged cycle by cycle via high voltage
diode from low-side supply voltage during on-time of
the low-side MOSFET. There is an UVLO threshold
with hysteresis that enables high-side section at 10,1V
and disables it at 8,4V.
HSGD (High side gate drive, Pin 19)
The Gate of the high-side MOSFET in a half-bridge
inverter topology is controlled by this pin. There is an
active L-level during UVLO and a limitation of the max.
H-level at 11V during normal operation. The switching
characteristics are the same as described for LSGD
(pin 2). It is recommended to use a resistor of about
15Ohm between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor.
The dead time between LSGD signal and HSGD signal
is 1800ns typically.
LVS1 (Lamp voltage sense 1, Pin 13)
Before the IC enters the softstart mode this pin has to
sense a sink current above 26µA (max) which is fed via
resistors from the bus voltage across the high-side
filament of the fluorescent lamp in order to monitor the
existence of the filament for restart after lamp removal.
Together with LVS2 (pin 14) and RES (pin 12) the IC
can monitor the lamp removal of totally 4 lamps.
Datasheet Version 1.2
HSGND (High side ground, Pin 20)
This pin is internally connected with pin 17.
7
February 2006
Figure 1
Datasheet Version 1.2
8
RES
12
10
8
RFPH
9
PFCVS
RFRUN
14
RTPH
LVS2
13
11
LVS1
R2
R1
OP1
Av= 2.5
0,375V
1,3V
1,6V
C5
C4
C3
CAPLOAD-RES
54k
C3
5µs
Blank
VBUS OPEN
LOOP DETECT
PFC_VS
VBUS
UNDERVOLTAGE
5µs
Blank
C2
N+1
N+2
V PEAK(N+1)
&
G6
LVS1_L
LVS2_L
OFF_H
LAMP_INSERT_H
UVLO_L
OPEN_LOOP_L
INVERTER
OVERCURRENT
OPERATION ABOVE
RUN FREQUENCY
END-OF-LIFE 1
CAPACITIVE LOAD 2
T1
5µs
Blank
5µs
Blank
5µs
Blank
Delay generator
for activating
lamp removal
after fault latch
is set.
Lamp insert
detection for
VRES < 1,6V
during
power down.
T1
0,24V
C2
INV1
G2
D Q
G3
D Q
G1
=
min.duration
of effect:
610µs
&
&
VDS
VDS
Q
R
1
Q
FAULT
LATCH
S
1
f
vre
OPEN_FILAMENT
CAPLOAD1
LVS1
LVS2
ERROR_LOGIC
POWER_DOWN_L
LAMP_INSERT_H
CAPLOAD2
CAP LOAD2
CAP LOAD1
Capacitive Load
Detection
1
min.duration of effect:
400ns
235ms
after end of preheat mode
1
1
Up & Down
Counter
min.duration
of effect:
500ms
END-OF-LIFE 2
LVS2
LVS1
END-OF-LIFE 1
Q
> 1,15.........=> Q = H
= 0,85..1,15=> Q = L
< 0,85….....=> Q = H
VPEAK(N)
VPEAK(N+1)
LSGDIN_H
HSGDIN_H
END-OF-LIFE 2
CAPACITIVE LOAD 1
OPEN FILAMENT
VBUS OVERVOLTAGE
1
G5
N
V PEAK(N)
Peak Rectification
5,0V
I3= 20µA; VRES< 1,6V; V CC> 10,5V; ILVS > 15µA; or during run mode
I1= 41µA; VRES< 1,6V; V CC> 10,5V; ILVS < 15µA;
I4= 17µA; VRES> 1,6V; V CC> 10,5V; ILVS > 15µA;
3,2V
I2= 34µA; VRES> 1,6V; V CC> 10,5V; ILVS < 15µA;
C1
D Q
I5= 41µA & 0µA alternating for 32 cycles as a delay;
VTH= 0,375V
VTH= 1,83V
VBUS
OVERVOLTAGE
5µs
Blank
PFC_PWM_IN
DIGITAL LOOP
CONTROL
I LVS
EOLACTIVE_H
C1
VREF= 2,50V
8-Bit ADC
-215µA
+215µA
C3
VCC
1
G4
T1
EN=L => Status Latched
D Q
G3
EN
C4
V TH1= 2,725V
V TH2= 2,625V
LVS_2
D3
LINSERT_H
C1
2,0V
EOLOFF_L
&
G2
POWER_DOWN_L
OFF_H
15µA
D1
LVS_1
ILVS
D2
C2
1
G1
R1
OP
Bias Cell1
C2
C1
OFF_H
MCLOCK_SPI
Master
Clock
SPI
for
Test
Mode
POWERSUPPLY
G3
&
5µs
Blank
5V
UVLO
5µs
Blank
PHEND_H
5,0V
Int. Supply
T1
VCO
dac7, dac4 =
GND during
run mode,
otherwise
transient
voltage levels
(0..2,5V)
OSC
IoscÆ fosc
Bandgap
Vref=2.5V
VTH=10,5V
POWER_DOWN_L
OSC
DSC
dac7
C1
dac7
IOSC
5,0V
Oscillator
T1
VTH1=14,0V
VTH2=10,5V VDD_good_H
Digital
sequential
control
PHEND_H
Z1
16V
@2mA
VCC
dac4
T2
Softstart and
Preheat Mode T2
Other Modes
Bias Cell3
OP
Preheat Mode
Other Modes
Bias Cell2
OP
R1
Bias Cell1
OP
Other Modes
Run Mode
PREHEAT_TIMER
RTPH
S1
2,0V
dac7
RFPH
S3
2,5V
RFRUN
2,5V
S2
dac7
S1
dac4
t
1,8µs
Dead
time
PWM
inverter
PFCPWM
Start-up
timer
off-time
40µs
DSC
PFC_PWM_IN
PFCGDIN
PFC
PWM &
Control
G1
VTH1=1,5V
VTH2=0,5V
C2
PFC_ZCD
D3
D1
D2
1,6V
LSGD
T1
T2
D1
D2
1.0V
PFCCS
R2
D2
D1
D1
C1
PFCGD
R1
Z1
T1
T2
0,8V
INVCLIM
C2
C1
D1
D2
HSGD
T1
T2
Z1
Z1
5,0V
VCC
1
260ns
Blank
PFC_CLIM
t
1
VCC
G1
250ns
Blank
IGN-LIM
0 220ns
1
G1
400ns
Blank
INV_OC
t
V GATE slope control
Z1
=12V
PFCGDIN
INVPWM
DSC
HS
0 220ns
V GATE slope control
Z1
=12V
0 220ns
VGATE slope control
Z1
=12V
LS
LS
HS
Coreless T.
PFCZCD
PFCCS
PFCGD
LSCS
GND
LSGD
VCC
HSGND
HSGD
HSVCC
7
6
5
1
4
2
3
17
19
18
2
I1 = 5µA
L = off
5V H = on
ICB1FL02G
Blockdiagram
Blockdiagram
Simplified Blockdiagram of ICB1FL02G
February 2006
ICB1FL02G
Functional Description
3
Functional Description
3.1
Typical operating levels during start-up
The control of the ballast should be able to start the operation within less than 100ms. Therefore the current
consumption of the IC is less than 150µA during UVLO. With a small start-up capacitor (about 1µF) and a power
supply, that feeds within 100µs (charge pump of the inverter) the IC can cover this feature.
As long as the Vcc is less than 10,5V, the current consumption is typically 80µA. Above a Vcc voltage level of
10,5V the IC checks whether the lamp(s) are assembled by detecting a current across the filaments. The low-side
filament is checked from a source current (20µA typ.) out of pin RES, that produces a voltage drop at the sense
resistor, which is connected via low-side filament to ground. An open filament is detected, when the voltage level
at pin RES is above 1,6V. The high-side filament (or the high-side of a series topology) is checked by a current
(15µA typ.) into the LVS pin. An open high-side filament causes a higher source current (41µA / 34µA typ.) out of
pin RES in order to exceed the 1,6V threshold. If one of both filaments is not able to conduct the test current, the
control circuit is disabled. The IC is enabled as soon as a sufficient current is detected across the filaments or the
supply voltage drops below the UVLO threshold (10,5V) e.g. by turn-off and turn-on of mains switch.
VCC
14,0V
10,5V
UVLO
START-UP
HYSTERESIS
IC ACTIVE
SOFTSTART
t
IVCC
80µA
80µA
<150µA
5mA
+ QGate
t
VRES
3,2V
1,6V
<3,2V
t
IRES
20µA
20µA
t
ILVS
>15µA
>15µA
< +/- 2,5mA
Figure 2
t
Progress of levels during a typical start-up.
When the previous conditions are fulfilled, and Vcc has reached the start-up threshold (14V), there is finally a
check of the Bus voltage. If the level is less than 15% of rated Bus voltage, the IC is waiting in power down mode
until the voltage increases. If the level is above 109% of rated Bus voltage there is no Gate drive, but an active
IC. The supply voltage Vcc will fall below the UVLO threshold and a new start-up attempt is initiated.
As soon as start-up conditions are fulfilled the IC starts driving the inverter with the start-up frequency of 125kHz.
Now the complete control including timers and the PFC control can be set in action. There are current limitation
thresholds for PFC preconverter and ballast inverter equipped with spike filters. The PFC current limitation
interrupts the on-time of the PFC MOSFET if the voltage drop at shunt resistor exceeds 1V and restarts after next
input from ZCD. The inverter current limitation operates with a first threshold of 0,8V which increases the operating
frequency during ignition mode if exceeded. A second threshold is provided at 1,6V that stops the whole control
circuit and latches this event as a fault.
Datasheet Version 1.2
9
February 2006
ICB1FL02G
Functional Description
VCC
16,0V
14,0V
10,5V
LS FILAMENT OPEN
UVLO HS FILAMENT CLOSED
START-UP
HYSTERESIS
IVCC
80µA
LAMP REMOVAL VRES> 1,3V IC ACTIVE
SOFTSTART
LS + HS OPEN
t
<170µA
80µA
<150µA
5mA
+ QGate
t
VRES
5,0V
3,2V
1,6V
1,3V
<3,2V
t
IRES
20µA
20µA
34µA
17µA
17µA
20µA
t
ILVS
>15µA
>15µA
>15µA
< +/- 2,5mA t
POWER
DOWN
SIGNAL
H
t
Figure 3
Start-up with LS filament broken and subsequent lamp removal.
VCC
16,0V
14,0V
10,5V
HS FILAMENT OPEN
UVLO LS FILAMENT CLOSED
START-UP
HYSTERESIS
IVCC
80µA
LAMP REMOVAL VRES> 1,3V IC ACTIVE
LS + HS OPEN
SOFTSTART
80µA
t
5mA
+ QGate
<150µA
<170µA
t
VRES
5,0V
3,2V
1,6V
1,3V
<3,2V
1,3V
t
IRES
20µA
41µA
34µA
34µA
17µA
20µA
t
ILVS
>15µA
>15µA
< +/- 2,5mA t
POWER
DOWN
SIGNAL
H
t
Figure 4
Start-up with HS filament broken and subsequent lamp removal.
Datasheet Version 1.2
10
February 2006
ICB1FL02G
Functional Description
3.2
PFC Preconverter
PFC is starting with a fixed frequent operation (ca. 25kHz), beginning with an on-time of 1µs and an off-time of
40µs. The on-time is enlarged every 400µs to a maximum on-time of 23µs. The control switches over into critical
conduction mode (CritCM) operation as soon as a sufficient ZCD signal is available. There is an overvoltage
threshold at 109% of rated Bus voltage that stops PFC Gate drive as long as the Bus voltage has reached a level
of 105% of rated Bus voltage again. The compensation of the voltage control loop is completely integrated. The
internal reference level of the Bus voltage sense (PFCVS) is 2,5V with high accuracy.
The PFC control operates in CritCM in the range of 23µs > on-time > 2,3µs. For lower loads the control operates
in discontinuous conduction mode (DCM) with an on-time down to 0,5µs and an increasing off-time. With this
control method the PFC preconverter covers a stable operation from 100% of load to 0,1% .
D5
VBUS
R3
90 ...
270 VAC
PFCZCD
R7
LVS1
L1
LVS2
D1...4
C2
PFCVS
R2
PFCCS
C7
Vcc
Figure 5
R F RUN
R6
VCC
D9
GND
C3 R9
HSGND
LSGD
LSCS
R ES
R4
C1
HSVCC
R T PH
PFCGD
LRFI
R F PH
R8
Q1
IC B1FL02G
HSGD
R1
R5 R12 R13
Circuit Diagram of the PFC preconverter section.
Overvoltage, undervoltage and open loop detection at pin PFCVS are sensed by analog comparators. The BUS
voltage loop control is provided by a 8bit sigma-delta A/D-Converter with a sampling rate of 400µs and a resolution
of 4mV/bit. So a range of +/- 0,5V from the reference level of 2,50V is covered. The digital error signal has to pass
a digital notch filter in order to suppress the AC voltage ripple of twice of the mains frequency. A subsequent error
amplifier with PI characteristic cares for stable operation of the PFC preconverter. During ignition and pre-run
mode the notch filter is bypassed in order to increase control loop reaction.
The zero current detection is sensed by a separate pin PFCZCD. The information of finished current flow during
demagnetization is required in CritCM and in DCM as well. The input is equipped with a special filtering including
a blanking of typically 500ns and is combined with a large hysteresis between the thresholds of typically 0,5V and
1,5V. In case of bad coupling between primary inductor winding and secondary ZCD-winding an additional filtering
by a capacitor at ZCD pin might be necessary in order to avoid mistriggering by long lasting oscillations during
switching slopes of the PFC MOSFET.
PFCVS
Σ∆-ADC
SRate 400µs
Res 4mV/bit
PFCGD
Notch
Filter
PI Loop
Control
Pulse width
Generator
Undervoltage
73% +/- 2,5%
Overcurrent
Protection
1,0V +/-5%
Overvoltage
109% +/-2,0%
ZCD
1,50V / 0,5V
Start-up
Open Loop
Detection
15% +/- 20%
Clock
600kHz
Gate
Driver
PFCCS
PFCZCD
Figure 6
Reference
2,50V
+/-1,5%
Structure of the mixed digital and analog control of PFC preconverter.
Datasheet Version 1.2
11
February 2006
ICB1FL02G
Functional Description
Discontinuous Conduction Mode <> Critical Conduction Mode
Relative Power %
identification markings unfilled
Operating Frequency (kHz) at VIN = VOUT/2
identification markings filled
1000
100
100
10
10
1
0,1
0
32
64
96
128
160
192
224
1
256
Digital Control Steps
Figure 7
Relative output power and operating frequency of PFC control at VIN = VOUT /2 versus control step.
Discontinuous Conduction Mode <> Critical Conduction Mode
10
100
1
10
0
0
32
64
96
128
160
192
224
identification markings filled
1000
Operating Frequency (kHz) at VIN = VOUT/2
On-Time (µs)
identification markings unfilled
100
1
256
Digital Control Steps
Figure 8
On-time and operating frequency of PFC control at VIN = VOUT /2 versus control step.
Datasheet Version 1.2
12
February 2006
ICB1FL02G
Functional Description
3.3
Typical operating levels during start-up
Within 10ms after start-up the inverter shifts operating frequency from 125kHz to the preheating frequency set by
resistor at pin RFPH. Preheating time can be selected by programming resistor at RFPH pin in steps of 17ms from
0ms to 2000ms.
After preheating the operating frequency of the inverter is shifted downwards in 40ms typically to the run
frequency. During this frequency shifting the voltage and current in the resonant circuit will rise when operating
close to the resonant frequency with increasing voltage across the lamp. As soon as the lower current sense level
(0,8V) is reached, the frequency shift downwards is stopped and increased by a couple of frequency steps in order
to limit the current and the ignition voltage also. The procedure of shifting the operating frequency up and down
in order to stay within the max ignition level is limited to a time frame of 235ms. If there is no ignition within this
time the control is disabled and the status is latched as a fault mode.
Typical variation of operating frequency during start-up
125kHz
f,V
Frequency
65kHz
50kHz
40kHz
Lamp Voltage
10ms
0-2000ms
40-235ms
250ms
Softstart
Preheating
Ignition
Pre-Run
t
Normal Operation
Softstart proceeds in 15 steps à 650µs according ∆fPH = (120kHz - f PH)/ 15steps.
Ignition proceeds in 127 steps à 324µs according ∆fIGN = (fPH - fRUN)/ 127steps.
Figure 9
Typical variation of operating frequency and lamp voltage during start-up.
1000
900
800
Ignition
Lamp Voltage
700
600
500
400
Without
Load
300
Run
200
100
With
Load
After
Ignition
0
10000
Preheating
100000
Operating Frequency
Figure 10
Typical lamp voltage versus operating frequency due to load change of the resonant circuit.
Datasheet Version 1.2
13
February 2006
ICB1FL02G
Functional Description
3.4
Detection of End-of-Life and Rectifier Effect
After ignition the lamp voltage breaks down to its run voltage level (typically 50Vpeak to 300Vpeak). Reaching the
run frequency there follows a time period of 250ms called Pre-Run Mode, in which some of the monitoring features
(EOL1, EOL2, Cap.Load1) are still disabled. In the subsequent Run Mode the End-of-life (EOL) monitoring is
enabled. The event EOL1 is detected by measuring the positive and negative peak level of the lamp voltage by a
current fed into the LVS pin (R17, R18,R19 in Fig. 11). If the sensed current exceeds 215µA for longer than 610µs
the status end-of-life (EOL1) or the exceeding of the maximum output power is detected. In Fig. 12 the different
levels of the sensed lamp voltage are illustrated.
R17
PFCZCD
R18
R10
Q2
HSGND
R11
Figure 11
C10
Q3
LSGD
D7
RES
RFPH
D9
D6
R30
Vcc
C5
C4
LSCS
RFRUN
VCC
GND
PFCCS
L2
HSVCC
RTPH
PFCVS
C2
ICB1FL02G
HSGD
PFCGD
R19
R15 R16
LVS1
LVS2
VBUS
R5 R12 R13
R14
C6
C8
R20
D8
C9
D10
C7
Circuit diagram of the lamp inverter section.
+ Shut down level
+ Ignition level
VLAMP-IGN
+ EOL Threshold
IVL+PEAKI/IV L-PEAKI
0
t
VLAMP-RUN
- EOL Threshold
- Ignition level
- Shut down level
Figure 12
Sensed lamp voltage levels.
Datasheet Version 1.2
14
February 2006
ICB1FL02G
Functional Description
2,5
2,4
2,3
Ratio of higher Amplitude / smaller Amplitude
2,2
2,1
2
1,9
1,8
1,7
1,6
1,5
1,4
1,3
1,2
1,1
1
0
50
I
Figure 13
LVS
100
150
= Lamp Voltage / Sense Resistor [uA]
200
250
of smaller Amplitude
Maximum ratio of amplitudes versus sense current.
Furthermore the rectification effect (EOL2) is detected when the ratio of the higher amplitude divided by the
smaller amplitude of the lamp voltage is bigger than illustrated in Fig. 13. for longer than 500ms. The ratio is
evaluated each cycle of the lamp voltage. The limit of the ratio increases dependend on the peak current of the
smaller amplitude of the lamp voltage from 1,15 at ILVS= 200µA nonlinear to 1,4 at ILVS= 50µA.
If the EOL2 conditions are detected, the control is disabled and the status is latched as a failure mode. Measuring
the duration of incorrect operating conditions is done by a check every 4ms. If the fault condition is existing, a
counter counts up, if the fault condition is not existing, the counter counts down. So we get an integration of the
fault events that allows a very effective monitoring of strange operating conditions.
The detection of EOL1 and EOL2 requires an AC current input at the sense pins LVS1 and LVS2 for proper
operation. A DC current at pin LVS will lead to a defined reaction only, if the level exeeds 175µA (typically) for
longer than 610µs which results in a shut down and change over into the latched failure mode.
3.5
Detection of capacitive mode operating conditions
If there happens a situation like an open resonant circuit (e.g. a sudden break of the tube) the voltage across the
resonant capacitor and current through the shunt of the low-side inverter MOSFET rise quickly. This event is
detected by inverter current limitation (1,6V) and results in shut down of the control. This status is latched as a
failure mode.
In another kind of failure the operation of the inverter may leave the zero voltage switching (ZVS) and move into
capacitive mode operation or into operation below resonance. There are two different levels for capacitive mode
detection implemented in the IC. A first criteria detects low deviations from ZVS (CapLoad1) and changes
operation into fault mode, if this operation lasts longer than 500ms. For CapLoad1 the same counter is used as
for the end-of-life evaluation.
Datasheet Version 1.2
15
February 2006
ICB1FL02G
Functional Description
A second threshold detects severe deviations such as rectangular shapes of voltage during operation below
resonance (CapLoad2). Then the inverter is turned off as soon as these conditions last longer than 610µs and the
IC changes over into fault mode. The evaluation of the failure condition is done by an up and down counter which
samples the status every 40µs.
CapLoad1 is sensed in the moment when low-side Gate drive is turned on. If the voltage level at pin RES is above
the VREScap threshold (typ. 0,24V) related to the level VRESLLV, conditions of CapLoad1 are assumed.
CapLoad2 is sensed in the moment when the high-side Gate drive is turned on. If the voltage level at pin RES is
below the VREScap threshold related to the level VRESLLV, conditions of CapLoad2 are assumed. As the reference
level VRESLLV is a floating level, it is updated every on-time of the low-side MOSFET.
D10 limits voltage transients at pin RES that can occur during removal of the lamp in run mode.
VDSLS
t
IDLS
V RES
VRESCAP
VRESLLV
tCAPM1
tCAPM2
t
Gate HS
t
Gate LS
Deadtime
Figure 14
3.6
t
Levels and points in time for detection of CapLoad1 and CapLoad2.
Interruption of Operation and Restart after Lamp Removal
In the event of a failing operation the fault latch is set after the specified reaction time (e.g. 500ms at EOL2). Then
the Gate drives are shut down immediately, the control functions are disabled and the current consumption is
reduced to a level of 150µA (typically). Vcc is clamped by internal zener diode to max 17,5V at 2mA. So the
internal zener diode is only designed to limit Vcc when fed from the start-up current, but not from the charge pump
supply! There is a current limitation at the internal zener diode function (max 5mA at Vcc= 17,5V) in order to avoid
conflicts with the clamping level of the external zener diode.
The capacitor at pin RES is discharged and charged during 32 cycles in order to generate a delay of several 10ms.
The delay is implemented for avoiding malfunctions in detecting the lamp removal due to voltage transients that
can occur after shut down. The reset of the fault latch happens after exceeding the 1,6V threshold at pin RES and
enabling the IC after lamp removal and subsequent decreasing voltage level at pin RES below the 1,3V threshold.
Datasheet Version 1.2
16
February 2006
ICB1FL02G
Functional Description
The status failure mode is kept as long until a lamp removal is detected (interruption of current across filaments
and detection of the return of the current) or the supply voltage drops below UVLO. After a break down of the
supply voltage below the undervoltage lockout (UVLO) threshold the IC resets any failure latch and will try to
restart as soon as Vcc exceeds the start-up threshold.
An undervoltage (75%) of the bus voltage will not be latched as a fault condition. If the undervoltage lasts longer
than 80µs the Gate drives are switched off and the IC tries to restart after a Vcc hysteresis has been passed.
VCC
16,0V
14,0V
LAMP
REMOVAL
LS + HS
OPEN
V
10,5V
FAULT LATCH
IC
ACTIVE SET E.G. BY EOL
>1,3V
RES
IC ACTIVE
SOFTSTART
t
IVCC
5mA
+ QGate
<170µA
<150µA
5mA
+ QGate
t
VRES
5,0V
3,2V
1,6V
1,3V
0,375V
1,6V
<3,2V
1,3V
t
IRES
41µA
20µA
20µA
>15µA
20µA
t
>15µA
>15µA
< +/- 2,5mA t
TRANSIENT
AT LVS PIN
H
FAULT
LATCH
SIGNAL
Figure 15
17µA
32 CYCLES (>50ms typically)
ILVS
<2,5mA
POWER
DOWN
SIGNAL
34µA
H
t
SET SIGNAL
RESET SIGNAL
t
Interruption of operation by a fault condition and subsequent lamp removal.
Datasheet Version 1.2
17
February 2006
Figure 16
Datasheet Version 1.2
18
Cap.Load1; EOL1,2
active
active
active
active
active
(605µs)
(300ns)
(80µs)
0ms …2000ms
Preheating
active, & 0,8V
active
active
active
40ms …235ms
Ignition
10,5 < Vcc < 16,0V;
F_PH < f < F_RUN
10,5 < Vcc < 16,0V;
f= F_RUN
Fault Mode: disabled by Lamp Removal or UVLO ;
10,5 < Vcc < 16,0V; IS< 150µA; IRES= 20µA
active
Overcurrent Inverter 1,6V
Capacitive Load 2
active
1,0V
Overcurrent PFC
active
<15%
BUS Open Loop
BUS Undervoltage <75%
active
35ms
10ms
Monitoring Softstart
BUS Overvoltage >109%
62ms
UVLO
10,5 < Vcc < 16,0V;
f= F_PH
Vcc > 14,0V & VRES< 1,6V=> Start
125kHz < f < F_PH;
active
active
active
active
250ms
Pre-Run
10,5 < Vcc < 16,0V; IRES= 20µA;
f= F_RUN
active
active
active
active
active
act,Restart
active
500ms
Run
Earliest
Stop
by EOL
4
10,5 < Vcc < 14,0V; IS< 150µA; IRES= 20µA
Mains Switch turned on; 0 < Vcc < 10,5V; IS< 80µA; IRES= 0µA
ICB1FL02G
State Diagram
State Diagram
State Diagram
February 2006
ICB1FL02G
Protection Functions
5
Protection Functions
Detection active during
+/- Peak Level of Lamp Voltage
above threshold
EOL1
610µs
X
Power down,
latched Fault Mode
Ratio of +/- amplitudes of lamp
voltage > 1.15 or < 0.85
EOL2
500ms
X
Power down,
latched Fault Mode
No zero voltage switching
Cap.Load 1
500ms
X
Power down,
latched Fault Mode
Voltage at Pin RES > 3.0V
Open Filament
500ms
X
Power down,
latched Fault Mode
Bus voltage > 109% of rated level
in active operation
Overvoltage
500ms
X
Power down,
latched Fault Mode
Bus voltage > 109% of rated level
10µs after power up
Overvoltage
Bus voltage > 109% of rated level
in active operation
PFC
Overvoltage
5µs
Bus voltage < 75% of rated level
Undervoltage
80µs
Bus voltage < 15% of rated level
Open Loop
Detection
1µs
Capacitive Load,
Operation below resonance
Cap.Load 2
610µs
Run frequency can not be achieved
No Ignition
235ms
Voltage at Pin RES > 1.6V
before power up
LS open
Filament
1ms
Prevents power up
Current into Pin LVS1 < 12µA
HS open
Filament
1ms
Prevents power up
Current into Pin LVS2 < 12µA
HS open
Filament
1ms
Prevents power up
Voltage at Pin PFCCS > 1.0V
PFC
Overcurrent
260ns
Voltage at Pin LSCS > 0.8V
Inverter Current
Limit
250ns
Voltage at Pin LSCS > 1.6V
Inverter
Overcurrent
400ns
Supply voltage at Pin VCC < 14.0V
before power up
Below startup
threshold
1µs
Supply voltage at Pin VCC < 10.5V
after power up
Below UVLO
threshold
1µs
Datasheet Version 1.2
Consequence
Softstart
10ms
Preheat Mode
0 - 2000ms
Ignition Mode
40 - 235ms
Pre-Run Mode
250ms
Run Mode
Fault-Type
Min. Duration
of Effect
Description of Fault
Gate drivers off, restart
after VCC hysteresis
X
X
X
X
X
X
X
X
X
X
Turn-off PFC MOSFET
until Bus Voltage < 105%
X
Gate drivers off, restart
after VCC hysteresis
X
Power down
X
Power down,
latched Fault Mode
X
X
X
X
Power down,
latched Fault Mode
X
X
X
X
X
X
Turn-off PFC MOSFET
immediately
Increases the Operating
Frequency
X
X
Power Down, Latched
Fault Mode
Prevents power up
X
19
X
X
X
X
Power Down, Reset of
Latched Fault Mode
February 2006
ICB1FL02G
Electrical Characteristics
6
Note:
6.1
Note:
Electrical Characteristics
All voltages without the high side signals are measured with respect to ground (pin 4). The high side
voltages are measured with respect to pin17/20. The voltage levels are valid if other ratings are not
violated.
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 3
(VCC) and pin 18 (HSVCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
LSCS Voltage
VLSCS
-5
6
V
LSCS Current
ILSCS
-3
3
mA
LSGD Voltage
VLSGD
-0.3
Vcc+0.3
V
internally clamped to 11V
VCC Voltage
VVCC
-0.3
18
V
see VCC Zener Clamp
VCC Zener Clamp Current
IVCCzener
-5
5
mA
IC in Power Down Mode
PFCGD Voltage
VPFCGD
-0.3
Vcc+0.3
V
internally clamped to 11V
PFCCS Voltage
VPFCCS
-5
6
V
PFCCS Current
IPFCCS
-3
3
mA
PFCZCD Voltage
VPFCZCD
-3
6
V
PFCZCD Current
IPFCZCD
-5
5
mA
PFCVS Voltage
VPFCVS
-0.3
5.3
V
RFRUN Voltage
VRFRUN
-0.3
5.3
V
RFPH Voltage
VRFPH
-0.3
5.3
V
RTPH Voltage
VRTPH
-0.3
5.3
V
RES Voltage
VRES
-0.3
5.3
V
LVS1 Current1
ILVS1_1
-1
1
mA
IC in Power Down Mode
LVS1 Current2
ILVS1_2
-3
3
mA
IC in Active Mode
LVS2 Current1
ILVS2_1
-1
1
mA
IC in Power Down Mode
LVS2 Current2
ILVS2_2
-3
3
mA
IC in Active Mode
HSGND Voltage
VHSGND
-900
900
V
referring to GND
HSGND, Voltage Transient
dVHSGND/dt
-40
40
V/ns
HSVCC Voltage
VHSVCC
-0.3
18
V
referring to HSGND
HSGD Voltage
VHSGD
-0.3
VHSVCC+
0.3
V
internally clamped to 11V
referring to HSGND
PFCGD Peak Source Current
IPFCGDsomax
—
150
mA
< 100ns
PFCGD Peak Sink Current
IPFCGDsimax
—
700
mA
< 100ns
LSGD Peak Source Current
ILSGDsomax
—
75
mA
< 100ns
LSGD Peak Sink Current
ILSGDsimax
—
400
mA
< 100ns
HSGD Peak Source Current
IHSGDsomax
—
75
mA
< 100ns
Datasheet Version 1.2
20
February 2006
ICB1FL02G
Electrical Characteristics
HSGD Peak Sink Current
IHSGDsimax
—
400
mA
Junction Temperature
Tj
-25
150
°C
Storage Temperature
TS
-55
150
°C
Max possible Power Dissipation
Ptot
—
2
W
PG-DSO-18-1, Tamb = 25°C
Thermal Resistance (Both Chips)
Junction-Ambient
RthJA
—
60
K/W
PG-DSO-18-1
Thermal Resistance (HS Chips)
Junction-Ambient
RthJAHS
—
120
K/W
PG-DSO-18-1
Thermal Resistance (LS Chips)
Junction-Ambient
RthJALS
—
120
K/W
PG-DSO-18-1
260
°C
wave sold. acc.JESD22A111
2
kV
Human body model1)
Soldering Temperature
ESD Capability
1)
VESD
—
< 100ns
According to EIA/JESD22-A114-B (discharging an 100pF capacitor through an 1.5kΩ series resistor).
6.2
Operating Range.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
HSVCC Supply Voltage
VHSVCC
VHSVCCoff
17.0
V
referring to HSGND
HSGND Supply Voltage
VHSGND
-900
900
V
referring to GND
VCC Supply Voltage
VVCC
VVCCoff
17.5
V
LSCS Voltage Range
VLSCS
-4
5
V
PFCVS Voltage Range
VPFCVS
0
4
V
PFCCS Voltage Range
VPFCCS
-4
5
V
PFCZCD Current Range
IPFCZCD
-4
4
mA
V
IC in Power Down Mode
LVS1, LVS2 Voltage Range
VLVS1,LVS2
-0.3
1)
LVS1, LVS2 Current Range
ILVS1,LVS2
2)
300
µA
IC in Power Down Mode
LVS1, LVS2 Current Range
ILVS1,LVS2
-2.5
2.5
mA
IC in Active Mode
Junction Temperature
Tj
-25
125
°C
Adjustable Preheating Frequency
Range set by RFPH
FRFPH
FRFRUN
150
kHz
Adjustable Run Frequency Range
set by RFRUN
FRFRUN
20
100
kHz
Adjustable Preheating Time
Range set by RTPH
tRTPH
0
1980
ms
Set Resistor for Run Frequency
RFRUN
5
25
kΩ
Set Resistor for Preheating
Frequency (RFRUN parallel RFPH)
RFRUN
II RFPH
3.3
Set Resistor for Preheating Time RTPH
kΩ
0
20
1)
Limited by maximum of current range at LVS1, LVS2
2)
Limited by minimum of voltage range at LVS1, LVS2
Datasheet Version 1.2
21
kΩ
February 2006
ICB1FL02G
Electrical Characteristics
6.3
6.3.1
Note:
Characteristics
Power Supply Section
The electrical characteristics involve the spread of values given within the specified supply voltage and
junction temperature range TJ from – 25 °C to 125 °C. Typical values represent the median values, which
are related to 25°C. If not otherwise stated, a supply voltage of VCC = 15 V and VHSVCC = 15V is assumed
and the IC operates in active mode. Furthermore all voltages are referring to GND if not otherwise
mentioned.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
High Side Leakage Current
IHSGNDleak
0.01
2
µA
VHSGND = 800V
VGND = 0V
VCC Quiescent Current
IVCCqu1
80
120
µA
VVCC = VVCCoff - 0.5V
VCC Quiescent Current
IVCCqu2
110
150
µA
VVCC = VVCCon - 0.5V
VCC Supply Current with
Inactive Gates
IVCCsup1
5
7
mA
VPFCVS > 2.725V
VCC Supply Current in
Latched Fault Mode
IVCClatch
—
110
170
µA
VRES = 5V
LS VCC Turn-On Threshold
LS VCC Turn-Off Threshold
LSVCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
13.6
10.0
3.2
14.1
10.5
3.6
14.6
11.0
4.0
V
V
V
VCC Zener Clamp Voltage
VVCCclmp
15.7
16.3
16.9
V
IVCC = 2mA
VRES = 5V
VCC Zener Clamp Current
IVCCzener
2.5
—
5
mA
VVCC = 17.5V
VRES = 5V
HSVCC Quiescent Current
IHSVCCqu1)
—
170
250
µA
VHSVCC = VHSVCCon -0.5V
HSVCC Supply Current with
Inactive Gate
IHSVCCsup11)
—
0.65
1.2
mA
9.6
7.9
1.4
10.1
8.4
1.7
10.7
9.1
2.0
V
V
V
VHSVCCon1)
HSVCC Turn-On Threshold
HSVCC Turn-Off Threshold
VHSVCCoff1)
HSVCC Turn-On/Off Hysteresis VHSVCChys1)
1)
With reference to High Side Ground HSGND
Datasheet Version 1.2
22
February 2006
ICB1FL02G
Electrical Characteristics
6.3.2
PFC Section
6.3.2.1
PFC Current Sense (PFCCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Turn-Off Threshold
VPFCCSoff
0.95
1.0
1.05
V
Duration of Overcurrent for turn-off
tPFCCSoff
200
250
320
ns
Spike Blanking
tblanking
140
200
260
ns
PFCCS Bias Current
IPFCCSbias
-0.5
0.5
µA
VPFCCS = 1.5V
Unit
Test Condition
6.3.2.2
PFC Zero Current Detector (PFCZCD)
Parameter
Symbol
Limit Values
min.
typ.
max.
Zero Crossing Upper Threshold
VPFCZCDup
1.4
1.5
1.6
V
Zero Crossing Lower Threshold
VPFCZCDlow
0.4
0.5
0.6
V
Zero Crossing Hysteresis
VPFCZCDhys
Clamping of Positive Voltages
VPFCZCDpclp
5.0
6.3
7.0
V
IPFCZCD = 4mA
Clamping of Negative Voltages
VPFCZCDnclp
-3.5
-2.9
-2.0
V
IPFCZCD = 4mA
PFCZCD Bias Current
IPFCZCDbias
-0.5
0.5
µA
VPFCZCD = 1.7V
PFCZCD Ringing Suppression Time
tringsup
350
650
ns
6.3.2.3
1.0
500
V
PFC Bus Voltage Sense (PFCVS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Trimmed Reference Voltage
VPFCVSref
2.47
2.5
2.53
V
Overvoltage Upper Detection Limit
VPFCVSup
2.675
2.725
2.78
V
Overvoltage Lower Detection Limit
VPFCVSlow
2.57
2.625
2.67
V
Overvoltage Hysteresis
VPFCVShys
70
100
130
mV
Undervoltage Detection Limit
VPFCVSuv
1.79
1.83
1.87
V
Undervoltage Shut Down
VPFCVSsd
0.30
0.375
0.45
V
Bias Current (ESD-Stress<1KV)
IPFCVSbias
-1
1
µA
VPFCVS = 2.5V
Bias Current (ESD-Stress>1KV)
IPFCVSbias
-2.5
2.5
µA
VPFCVS = 2.5V
Datasheet Version 1.2
23
February 2006
ICB1FL02G
Electrical Characteristics
6.3.2.4
PFC PWM Generation
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Initial On-Time
tPFCon-initial
0.6
1
1.4
µs
VPFCZCD = 0V
Max. On-Time
tPFCon-max
19
23.5
28
µs
0.45V < VPFCVS <
2.45V
Repetition Time when missing Zero
Crossing
tPFCrep
45
55
66
µs
VPFCZCD = 0V
Off-time when missing ZCD Signal
tPFCoff
35
42
49
µs
6.3.2.5
PFC Gate Drive (PFCGD)
Parameter
Symbol
Limit Values
min.
PFCGD Low Voltage
PFCGD High Voltage
VPFCGDlow
VPFCGDhigh
typ.
Unit
Test Condition
max.
0.4
0.7
0.9
V
IPFCGD = 5mA
0.4
0.75
1.1
V
IPFCGD = 20mA
-0.1
0.3
0.6
V
IPFCGD = -20mA
10.2
11
11.8
V
IPFCGD = -20mA
9.0
—
—
V
IPFCGD = -1mA
VVCC = VVCCoff +
0.3V
8.5
—
—
V
IPFCGD = -5mA
VVCC = VVCCoff +
0.3V
IPFCGD = 20mA
VVCC = 5V
PFCGD Voltage Active Shut Down
VPFCGDsd
0.4
0.75
1.1
V
PFCGD Peak Source Current
IPFCGDsource
—
100
—
mA
Rload = 4Ω
+ CLoad = 3.3nF1)
PFCGD Peak Sink Current
IPFCGDsink
—
-500
—
mA
Rload = 4Ω
+ CLoad = 3.3nF1)
PFCGD Rise Time
2V < VLSGD < 8V
tPFCGDrise
110
220
400
ns
Rload = 4Ω
+ CLoad = 3.3nF
PFCGD Fall Time
8V > VLSGD > 2V
tPFCGDfall
20
45
70
ns
Rload = 4Ω
+ CLoad = 3.3nF
1)
The parameter is not subject to production test - verified by design/characterization
Datasheet Version 1.2
24
February 2006
ICB1FL02G
Electrical Characteristics
6.3.3
Inverter Section
6.3.3.1
Inverter Control (RFRUN, RFPH, RTPH)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Fixed Start-Up Frequency
Fstartup
112
125
138
kHz
Duration of Soft Start, shift F from
Start-Up to Preheating Frequency
tsoftstart
9.0
11.0
13.5
ms
Preheating Frequency
FRFPH1
97.0
100
103.0
kHz
RRFPH = 10kΩ
RRFRUN = 10kΩ
Run Frequency
FRFRUN1
49.0
50.0
51.0
kHz
RRFRUN = 10kΩ
Preheating Time
tRTPH1
720
900
1080
ms
RRTPH = 8.06kΩ
Preheating Time
tRTPH2
50
90
130
ms
RRTPH = 806Ω1)
Current Source Preheating Time
IRTPH
132
140
148
µA
Min. Duration of Ignition, shift F from
Preheating to Run Frequency
tIGNITION
34
40
48
ms
1)
Max. Duration of Ignition, shift F from
Preheating to Run Frequency
tNOIGNITION
210
235
290
ms
1)
Duration of Pre-Run, time period after
operating frequency has reached Run
Frequency first time after ignition
tPRERUN
210
250
290
ms
1)
Minimum Duration of fault condition
by EOL2, Cap.Load 1, Open filament
and Overvoltage for entering latched
Fault Mode
tCAPLOAD1
420
500
580
ms
1)
Minimum Duration of fault condition
by EOL1, Cap.Load 2 for entering
latched Fault Mode
tCAPLOAD2
520
610
750
µs
1)
The parameter is not subject to production test - verified by design/characterization
6.3.3.2
Inverter Low Side Current Sense (LSCS)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Current Limit Threshold during
Ignition Mode
VLSCSlimit
0.76
0.80
0.84
V
Duration of Current above Threshold
for enabling Frequency Increase
tLSCSlimit
200
250
320
ns
Overcurrent Shut Down Threshold
VLSCSovc
1.55
1.60
1.65
V
Duration of Overcurrent for entering
Latched Fault Mode
tLSCSovc
320
400
480
ns
Bias Current LSCS
ILSCSbias
-0.5
0.5
µA
Inverter Dead Time between LS off
and HS on
tdeadtime
1.50
2.0
µs
Datasheet Version 1.2
25
1.75
Test Condition
VLSCS = 1.5V
February 2006
ICB1FL02G
Electrical Characteristics
6.3.3.3
Restart after Lamp Removal (RES)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Low-side Open Filament Threshold
VRESofil
3.1
3.2
3.3
V
Capacitive Load Detection Threshold
VREScap
0.18
0.24
0.30
V
Discharge Resistor during Latched
Fault Mode
RRESdisch
37
54
70
kΩ
I1 Current Source
IRES1
-54.3
-41
-30.0
µA
VRES=1V;
LVS1=5µA
I2 Current Source
IRES2
-46
-34
-24.2
µA
VRES=2V;
LVS1=5µA
I3 Current Source
IRES3
-27.0
-20
-15.1
µA
VRES=1V;
LVS1=50µA
I4 Current Source
IRES4
-22.6
-17
-12.3
µA
VRES=2V;
LVS1=50µA
C1 Comparator Threshold
VRESC1
1.55
1.6
1.65
V
C2 Comparator Threshold
VRESC2
1.25
1.3
1.35
V
C3 Comparator Threshold
VRESC3
0.32
0.375
0.46
V
6.3.3.4
Lamp Voltage Sense (LVS1, LVS2)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Source Current before Start Up
ILVSsource
-8
-5
-2
µA
11 < VVCC < 13V
VLVS = 0V
Threshold for enabling Lamp
Monitoring
VLVSenable
1.5
2.3
3.0
V
11 < VVCC < 13V
Sink Current Threshold for Lamp
Detection
ILVSsink
9
15
26
µA
VLVS > VVCC
Positive EOL Current Threshold
ILVSpEOLAC
185
215
250
µA
T > 0°C, AC input
Negative EOL Current Threshold
ILVSnEOLAC
-250
-215
-185
µA
T > 0°C, AC input
EOL Current Threshold
ILVSEOLDC
+/-145
+/-175
+/-210
µA
T > 0°C, DC input
Maximum Ratio between positive and
negative Current Amplitude1)
ROLVS1MAX
ROLVS2MAX
1.1
1.2
1.3
ILVSsourpeak=150µA
ILVSsinkpeak=
increasing
Minimum Ratio between positive and
negative Current Amplitude1)
ROLVS1MIN
ROLVS2MIN
0.75
0.85
0.95
ILVSsinkpeak=150µA
ILVSsourcepeak=
increasing
Positive Clamping Voltage
ILVSclmp
-
VVCC +
1V
-
V
ILVS = 300µA
1)
RO
I
(n + 1)
LVS sin kpeak
= -------------------------------------------------------LVS
I
(n)
LVSsourcepeak
Datasheet Version 1.2
RO
26
I
(n + 2)
LVSsource
= -------------------------------------------------------LVS
I
(n + 1)
LVS sin kp eak
February 2006
ICB1FL02G
Electrical Characteristics
6.3.3.5
Inverter Low Side Gate Drive (LSGD)
Parameter
Symbol
Limit Values
min.
LSGD Low Voltage
LSGD High Voltage
VLSGDlow
VLSGDhigh
typ.
Unit
Test Condition
max.
0.4
0.7
1.0
V
ILSGD = 5mA
0.5
0.8
1.2
V
ILSGD = 20mA
-0.3
0.1
0.4
V
ILSGD = -20mA
10.0
10.8
11.6
V
IPFCGD = -20mA
9.0
—
—
V
IPFCGD = -1mA
VVCC = VVCCoff +
0.3V
8.5
—
—
V
IPFCGD = -5mA
VVCC = VVCCoff +
0.3V
LSGD Voltage Active Shut Down
VLSGDsd
0.5
0.8
1.2
V
IHSGD = 20mA
VHSVCC = 5V
LSGD Peak Source Current
ILSGDsource
—
50
—
mA
Rload = 10Ω +
CLoad = 1nF1)
LSGD Peak Sink Current
ILSGDsink
—
-300
—
mA
Rload = 10Ω +
CLoad = 1nF1)
LSGD Rise Time
2V < VLSGD < 8V
tLSGDrise
110
220
400
ns
Rload = 10Ω +
CLoad = 1nF
LSGD Fall Time
8V > VLSGD > 2V
tLSGDfall
20
35
60
ns
Rload = 10Ω +
CLoad = 1nF
1)
The parameter is not subject to production test - verified by design/characterization
Datasheet Version 1.2
27
February 2006
ICB1FL02G
Electrical Characteristics
6.3.3.6
Inverter High Side Gate Drive (HSGD)
Parameter
Symbol
Limit Values
min.
HSGD Low Voltage
HSGD High Voltage
VHSGDlow
VHSGDhigh
typ.
Unit
Test Condition
max.
0.02
0.05
0.1
V
IHSGD = 5mA
0.5
1.1
2.5
V
IHSGD = 100mA
-0.4
-0.2
-0.05
V
IHSGD = -20mA
9.5
10.5
11.0
V
IHSGD = -20mA
7.8
—
—
V
IHSGD = -1mA
VHSVCC = VHSVCCoff
+ 0.3V
0.05
0.22
0.50
V
IHSGD = 20mA
VHSVCC = 5V
HSGD Voltage Active Shut Down
VHSGDsd
HSGD Peak Source Current
IHSGDsource
—
50
—
mA
Rload = 10Ω +
CLoad = 1nF1)
HSGD Peak Sink Current
IHSGDsink
—
-300
—
mA
Rload = 10Ω +
CLoad = 1nF1)
HSGD Rise Time
2V < VHSGD < 8V
tHSGDrise
140
220
300
ns
Rload = 10Ω +
CLoad = 1nF
HSGD Fall Time
8V > VHSGD > 2V
tHSGDfall
20
35
70
ns
Rload = 10Ω +
CLoad = 1nF
1)
The parameter is not subject to production test - verified by design/characterization
Datasheet Version 1.2
28
February 2006
ICB1FL02G
Application Examples
7
Application Examples
7.1
Operating Behaviour of a Ballast for a single Fluorescent Lamp
After turning on the mains switch the peak value of the rectified AC input voltage is available at C02 and smoothing
capacitor C10 (Fig. 17). Via R11 and R12 the supply voltage increases at bypass capacitors C12 and C13. At a
level of 10,5V a source current out of pin RES is sensing the existence of the low-side filament of the fluorescent
lamp. Fed from the BUS voltage a current is detected at pin LVS1 via R31...R35, when the high-side filament is
connected. The current fed into pin LVS1 is used to charge C12 via internal clamping diode. The IC changes into
active mode when Vcc level achieves the turn-on threshold of 14V and both filaments are detected. If not required
the pin LVS2 can be disabled by connecting to GND.
The active IC is sensing the BUS voltage level via R14, R15. Gate drives are disabled when open loop or
overvoltage are detected. If BUS voltage level is within the allowed range, the low-side Gate drive is starting with
the first pulse of the 125kHz softstart frequency. Only few cycles are required to charge the bootstrap capacitor
C14 via D6, R30 and Q3. Without R30 there is a risk of overcurrent shut down by exceeding the 1,6V threshold
at pin LSCS. The power supply is generated by a charge pump C16, D7 and D8. In normal operation C16 is
charged and discharged via C17 from the current forced by the resonance inductor L2 during the deadtime of the
inverter producing a zero voltage switching (ZVS) operation. Run frequency, preheating frequency and preheating
time are set by resistors R21, R22 and R23.
Q2
LVS1
PFCZCD
R14
C02
C10
R12
PFCCS
G ND
C03
D9
R18 R19
K1
K2
L2
C17
HSGND
LSGD
C14
LSCS
C15
R29
C13
K3
C16 C18
K4
D7
D6
L22
C11 R20
R21 R22 R23
C20
Q3
R27
D8
R30
C12
N3
HSVCC
RES
C04
PFCVS
C21
R26
RTPH
PFCGD
R16
ICB1FL02G
R15
Q1
RFPH
R11
PE
Figure 17
R34 R35
HSGD
K02
K03
L21
R33
N2
N1
R13
180V..
C01
270V
AC
R32
D5
LVS2
L1
RFRU N
L0
VC C
K01 F1
R31
D11
C05
D1...4
C19
C22
R36
D10
R24 R25
Application circuit of a Ballast for a single Fluorescent Lamp with voltage mode Preheating.
During run mode the lamp voltage is sensed via R31...R33 in order to detect an abnormal increasing of lamp
voltage or an rectifier effect that can occur at end-of-life conditions of the lamp. At the pin RES there is also
detected a non-ZVS operation, classified into Capmode1 and Capmode2. This will be done by the capacitive
divider C18, C19, that transfers the divided AC-part of the inverter output voltage to pin RES. Dependent on the
shape of the signal two different time windows can be started at abnormal conditions in order to protect the ballast.
Zener diode D10 limits voltage transients at pin RES that can occur during removal of the lamp.
Voltage mode preheating is done by two separate windings on the resonant inductor L2. The bandpass filters L21,
C21 and L22, C22 are designed to pass preheating current at preheating frequency only and to block any current
during run mode. Ignition is provided by shifting the operating frequency towards the resonant frequency of L2
and C20. The voltage level during ignition is limited by the current sensed at Shunt resistors R24, R25 with a level
of 0,8V at pin LSCS. Overcurrents that exceed a voltage level of 1,6V for longer than 400ns will disable the IC at
any time and change into fault mode.
The PFC preconverter with L1, Q1 and D5 is starting with a fixed frequent operation and change over to a critical
conduction mode (CritCM) as soon as the level at pin PFCZCD is sufficient to trigger the operation. During light
load the operation mode changes into discontinuous conduction mode (DCM). Compensation of the voltage
control loop is completely integrated with a digital filter and error amplifier. PFC overcurrent is sensed by R18,
R19, Bus overvoltage and undervoltage at pin PFCVS. A bypass diode D11 between the DC side of the mains
rectifier and BUS capacitor is recommended in order to avoid an overload of the PFC MOSFET Q1.
Datasheet Version 1.2
29
February 2006
ICB1FL02G
Application Examples
7.2
Design Equations of a Ballast Application
Subsequent the design equations are listed:
Start-up resistors R11, R12:
R
11
+R
V
INMIN
200V
= ------------------------- = ----------------- = 1, 33MΩ
12
I
150µA
VCCqu2
Selected value: R11= 470k; R12= 470k
Current limitation resistor R13 of PFC zero current detector (PFCZCD).
The additional factor 2 is used in order to keep away from limit value.
R
V
⋅N
⋅2
BUS
SEC
410V ⋅ 13 ⋅ 2
= ----------------------------------------------------------- = --------------------------------- = 20, 8kΩ
13
I
⋅N
⋅1
4mA ⋅ 128 ⋅ 1
PFCZCD
PRIM
Selected value: R13= 33k.
PFC Voltage sense resistor R20:
R
V
REF
2, 50V
≤ ------------------------------------------ = ------------------------------- = 10kΩ
20 100 ⋅ I
100 ⋅ 2, 5µA
PFCBIAS
Selected value: R20= 10k.
PFC Voltage sense resistors R14, R15:
R
14
+R
15
V
–V
BUS
REF
410V – ( 2, 5V )
= --------------------------------------- ⋅ R
= -------------------------------------- ⋅ 10k = 1630kΩ
20
V
2, 5V
REF
Selected values: R14= 820k; R15= 820k
Low pass capacitor C11:
Selected corner frequency fC1= 10kHz.
C
1 ⋅ (R + R + R )
20
14
15
1 ⋅ ( 10k + 820k + 820k )
= --------------------------------------------------------------------------- = --------------------------------------------------------------------------------------- = 1, 60nF
11
2⋅π⋅f
⋅ R ⋅ (R + R )
2 ⋅ π ⋅ 10kHz ⋅ 10k ⋅ ( 820k + 820k )
C1 20
14
15
Selected value C3= 2,2nF
PFC Shunt resistors R18, R19:
R ⋅R
V
⋅η⋅V
⋅ 2
18 19
PFCCSOFF
INACMIN
1V ⋅ 0, 95 ⋅ 180V ⋅ 2
-------------------------- = ---------------------------------------------------------------------------------------------- = ------------------------------------------------------ = 1, 1 Ω
R +R
4⋅P
4 ⋅ 55W
18
19
OUTPFC
Selected values: R18= 2,2Ohm; R19= 2,2Ohm
Datasheet Version 1.2
30
February 2006
ICB1FL02G
Application Examples
Set resistor R21 for run frequency, at a projected run frequency of 45kHz:
R
= R
21
8
8
5 ⋅ 10 ⋅ ΩHz
5 ⋅ 10 ⋅ ΩHz
= --------------------------------- = --------------------------------- = 11, 1kΩ
FRUN
f
45kHz
RUN
Selected value: R21= 11,0k
Set resistor R22 for preheating frequency, at a projected preheating frequency of 105kHz:
R
22
= R
FPH
R
FRUN
11, 0k
= --------------------------------------------- = ------------------------------------------------- = 8, 4kΩ
f
⋅R
105kHz ⋅ 11, 0k
PH FRUN
---------------------------------------- – 1
------------------------------------ – 1
8
8
5 ⋅ 10 ⋅ ΩHz
5 ⋅ 10 ⋅ ΩHz
Selected value: R22= 8,2k
Set resistor R23 for preheating time, at a projected preheating time of 900ms:
R
23
= R
T [ ms ]
PH
900ms
= -------------------------------------- = -------------------------------------- = 8, 93kΩ
TPH
( 112ms ) ⁄ ( kΩ )
( 112ms ) ⁄ ( kΩ )
Selected value: R23= 8,2k
Gate drive resistors R16, R26, R27 are recommended to be equal or higher than 10Ohm.
Shunt resistors R24, R25:
The selected lamp type 54W-T5 requires an ignition voltage of VIGN= 800V peak. In our application example the
resonant inductor is evaluated to L2= 1,46mH and the resonant capacitor C20= 4,7nF. With this inputs we can
calculate the ignition frequency fIGN :
f
IGN
V
⋅2
BUS
1 ± -----------------------π⋅V
IGN
---------------------------------------- =
2
4⋅π ⋅L ⋅C
2 20
=
410V ⋅ 2
1 ± --------------------π ⋅ 800V
------------------------------------------------------------- = 69759Hz
2
4 ⋅ π ⋅ 1, 46mH ⋅ 4, 7nF
The second solution of this equation (with the minus sign) leads to a result of 50163Hz, which is on the capacitive
side of the resonant rise. This value is no solution, because the operating frequency approaches from the higher
frequency level.
In the next step we can calculate the current through the resonant capacitor C20 when reaching a voltage level
of 800V peak.
I
C20
= V
IGN
⋅2⋅π⋅f
IGN
⋅C
20
= 800V ⋅ 2 ⋅ π ⋅ 69759Hz ⋅ 4, 7nF = 1, 65A
Finally the resistors R24, R25 can be calculated from IC20 and the current limitation threshold during ignition
mode.
R ⋅R
V
24 25
LSCSLIMIT
0, 8V
-------------------------- = --------------------------------------- = ---------------- = 0, 485Ω
R +R
I
1, 65A
24
25
C20
Selected values are R24= 0,82Ohm; R25= 0,82Ohm.
Datasheet Version 1.2
31
February 2006
ICB1FL02G
Application Examples
Lamp voltage sense resistors R31, R32, R33:
The selected lamp type 54W-T5 has a typical run voltage of 167V peak. We decide to set the EOL-thresholds at
a level of 1,5 times the run voltage level (= 250,5V peak).
R
+R
31
32
+R
V
LEOL
250, 5V
= --------------------------- = ------------------- = 1165kΩ
33
I
215µA
LVSEOL
Selected values: R31= 390k; R32= 390k; R33= 390k (=1170k).
Current source resistors R34, R35 for detection of high-side filament:
R
34
+R
V
INMIN
200V
= --------------------------------------------- – ( R + R + R ) = -------------- – ( 1170k ) = 6522kΩ
35
31
32
33
I
26µA
LVSSINKMAX
Selected values: R34= 2,2M; R35= 2,2M;
Current limitation resistor R30 for floating bootstrap capacitor C14:
A factor of 2 is provided in order to keep current level significant below LSCS turn-off threshold.
R
2⋅V
R ⋅R
CCON
24 25
2 ⋅ 14V 0, 82 ⋅ 0, 82
≥ ---------------------------------- ⋅ -------------------------- = ------------------ ⋅ ------------------------------ = 7, 18Ω
30 V
R +R
1, 6V 0, 82 + 0, 82
LSCSOVC 24
25
Selected value: R30= 10Ohm.
Low-side filament sense resistor R36:
For a single lamp ballast
R
V
RESC1MIN
1, 55V
≤ ------------------------------------- = -------------------- = 57, 4kΩ
36
I
27, 0µA
RES3MIN
Selected value: R36= 56k
V
1, 65V
RESC1MAX
≥ --------------------------------------- = -------------------- = 109, 3kΩ
I
15, 1µA
RES3MAX
Selected values in a topology with 2 lamps in parallel: R36A= 110k; R36B= 110k.
R
36A
Low pass filter capacitor C19:
Capacitor C19 provides a low pass filter together with resistor R36 in order to suppress AC voltage drop at the
low-side filament. When we estimate an AC voltage of 10V peak-to-peak at low-side filament during run mode at
fRUN= 40kHz, we need a suppression of at least a factor FLP= 100 (-40dB).
C
19
=
2
–1
F
LP
-------------------------------------------------- =
(2 ⋅ π ⋅ f
⋅R )
RUN 36
2
100 – 1
--------------------------------------------------- = 7, 1nF
( 2 ⋅ π ⋅ 40kHz ⋅ 56k )
Selected value for better ripple suppression: C19= 22nF.
Datasheet Version 1.2
32
February 2006
ICB1FL02G
Application Examples
Detection of capacitive mode operation via C18:
The DC level at pin RES is set by R36 and the source current IRES3. The preferred AC level is in the range between
∆VACRES= 1,5V to 2,0V at a ∆VBUS= 410V.
C
= C
18
∆V
ACRES
2V
⋅ ----------------------------- = 22nF ⋅ ------------- = 107pF
19 ∆V
410V
BUS
Selected value: C18= 82pF.
Bandpass filters L21/C21 and L22/C22 can be used in order to conduct filament currents preferred at preheating
frequency and to suppress these currents during run mode.
Inductor L1 of the boost converter:
The inductivity of the boost inductor typically is designed to operate within a specified voltage range above a
minimum frequency in order to get an easier RFI suppression. It is well known, that in critical conduction mode
(CritCM) there is a minimum operating frequency at low input voltages and another minimum at maximum input
voltage. In state-of-the-art CritCM PFC controllers we use the lowest value out of these two criterias:
At minimum AC input voltage:
2
(V
⋅ 2) ⋅ (V
– (V
⋅ 2)) ⋅ η
INACMIN
BUS
INACMIN
L = -----------------------------------------------------------------------------------------------------------------------------------------------A
4⋅F
⋅P
⋅V
MIN OUTPFC
BUS
L
2
( 180V ⋅ 2 ) ⋅ ( 410V – ( 180V ⋅ 2 ) ) ⋅ 0, 95
= ------------------------------------------------------------------------------------------------------------- = 3, 89mH
A
4 ⋅ 25kHz ⋅ 60W ⋅ 410V
At maximum AC input voltage
2
(V
⋅ 2) ⋅ (V
– (V
⋅ 2)) ⋅ η
INACMAX
BUS
INACMAX
L = ----------------------------------------------------------------------------------------------------------------------------------------------------B
4⋅F
⋅P
⋅V
MIN OUTPFC
BUS
L
2
( 270V ⋅ 2 ) ⋅ ( 410V – ( 270V ⋅ 2 ) ) ⋅ 0, 95
= ------------------------------------------------------------------------------------------------------------- = 1, 58mH
B
4 ⋅ 25kHz ⋅ 60 W ⋅ 410V
With the new control principle for the PFC preconverter we have a third criteria that covers the maximum on-time
tPFCOM-MAX= 23,5µs:
L
L
(V
⋅ 2) ⋅ T
⋅η
INACMIN
ONMAX
= ------------------------------------------------------------------------------------------C
4⋅P
OUTPFC
C
( 180 ⋅ 2 ) ⋅ 23, 5µs ⋅ 0, 95
= ----------------------------------------------------------------- = 6, 03mH
4 ⋅ 60 W
With the assumed conditions the lowest value out of LA, LB, LC is 1,58mH.
Selected value: L1= 1,58mH.
Datasheet Version 1.2
33
February 2006
ICB1FL02G
Application Examples
Bill of material for the application circuit of figure 17 and the design equations standing ahead. This design was
used as an evaluation board.
Table 1
Bill of Material for a FL-Ballast of a 54W-T5 Lamp
F1
Fuse 1A fast
C17
150nF/630V
IC1
ICB1FL02G
C18
82pF/2KV
Q1
SPP03N60C3 (600V/1,4Ω)
C19
22nF/63V
Q2
SPP03N60C3 (600V/1,4Ω)
C20
4,7nF/1600V DC
Q3
SPP03N60C3 (600V/1,4Ω)
C21
22nF/400V
D1...D4
B250C1000
C22
22nF/400V
D5
MUR160
D6
MUR160
R11
470k
D7
UF4003
R12
470k
D8
UF4003
R13
33k
D9
BZX79C16
R14
820k
D10
BZX79C4V7
D11
1N4007
R15
820k
L0
2x68mH/0,65A
R16
22
L1
1,58mH; EFD25/13/9
R18
2,2
Np/Ns= 128/13
R19
2,2
1,46mH; EFD25/13/9
R20
10k
Np/Ns= 153/4
R21
11,0k (45,5kHz)
L21
100µH;
R22
8,2k (106,4kHz)
L22
100µH;
R23
8,2k (918ms)
C01
220nF/X2/275V AC
R24
0,82
C02
220nF/X2/275V AC
R25
0,82
C03
3,3nF/Y1/400V AC
R26
22
C10
10µF/450V DC
R27
22
C11
2,2nF/63V
R30
10
C12
470nF/63V
R31
390k
C13
470nF/63V
R32
390k
C14
100nF/63V
R33
390k
C15
150nF/630V
R34
2,2M
C16
1nF/1kV
R35
2,2M
R36
56k
L2
Datasheet Version 1.2
34
February 2006
ICB1FL02G
Application Examples
7.3
Multilamp Ballast Topologies
90 ...
270 VAC
LVS2
PFCZCD
LVS1
How to use ICB1FL02G in multi-lamp topologies is demonstrated in the subsequent figures. In figure 18 we see
an application for a single lamp with current mode preheating. Compared with figure 17 the difference is the
connection of the resonant capacitor in series with the filaments. In respect of operating behaviour the current
mode preheating cannot be designed with same variation of operating parameters: the preheating current is
typically lower and lamp voltage during preheating higher than in topologies with voltage mode preheating.
ICB1FL02G
HSGD
Figure 18
LSGD
LSCS
RF PH
RF RU N
VCC
GN D
PFCCS
HSGND
RES
PFCVS
RT PH
PFCGD
HSVCC
Application Circuit of a Ballast for a single Fluorescent Lamp with current mode Preheating.
PFCZCD
LVS1
90 ...
270 VAC
LVS2
A topology for two lamps is shown in figure 19. Both lamps including their individual resonant circuit are operating
in parallel at the same inverter output. Such a topology can be done with voltage mode preheating in the same
way. As the control IC is designed to operate such a 2-lamp topology without restrictions in respect to the
monitoring functions, the IC-specific effort is to activate the second lamp voltage sense (LVS2) and an additional
resistor at pin RES in order to sense the lamp removal of the second low-side filament.
HSGND
LSGD
Figure 19
LSCS
RF PH
RF RU N
VCC
GND
PFCCS
RES
PFCVS
RT PH
PFCGD
ICB1FL02G
HSGD
HSVCC
Application circuit of a Ballast for two Fluorescent Lamps in parallel with current mode Preheating.
Beside a topology with paralleled lamps it is possible of course to use two lamps in series. In this way we come
to a 4-lamp topology shown in figure 20. The lamp voltage is sensed of each of the two series connections. The
lamp removal is detected on the high-side filaments of the high-side lamps and on the low-side filaments of the
Datasheet Version 1.2
35
February 2006
ICB1FL02G
Package Outlines
90 ...
270 VAC
LVS2
PFCZCD
LVS1
low-side lamps. In this way ICB1LB02G supports multi-lamp topologies with all required monitoring functions with
a low number of external components.
RES
RTPH
LSCS
Application circuit of a Ballast for four Fluorescent Lamps with voltage mode Preheating.
Package Outlines
1.27
0.35 +0.15 2)
0.2 20x
20
1
0.1
0.4
8° MAX.
7.6 -0.2 1)
+0 .09
0.35 x 45°
0.23
0.2 -0.1
PG-DSO-18-1
(Plastic Dual Small Outline)
2.65 MAX.
8
LSGD
2.45 -0.2
Figure 20
VC C
G ND
PFCCS
HSGND
RFPH
PFCVS
RFR UN
PFCGD
ICB1FL02G
HSGD
HSVCC
+0.8
10.3 ±0.3
11
12.8 -0.2 1)
10
Index Marking
1)
2)
Figure 21
Does not include plastic or metal protrusions of 0.15 max per side
Does not include dambar protrusion of 0.05 max per side
Package dimensions and mechanical data (Dimensions in mm).
Datasheet Version 1.2
36
February 2006
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere
Anstrengungen
gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Dazu
gehört
eine
bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit
den
entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualität zu
beweisen.
Wir werden Sie überzeugen.
http://www.infineon.com
Published by Infineon Technologies AG
Quality takes on an all encompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.