E2U0010-28-81 This version: Aug. 1998 MSM6996H/6996V/6997H/6997V/6998/6999 Previous version: Nov. 1996 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ¡ Semiconductor Single Chip CODEC GENERAL DESCRIPTION The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 Hz. FEATURES • Compliance with ITU-T companding Law MSM6996H/MSM6996V/MSM6998 : A-law MSM6997H/MSM6997V/MSM6999 : m-law • Capable of independent operation of transmission and reception • Transmission clock in the range of 64 kHz to 2048 kHz • Adjustable transmit gain • 600 W drive for analog output MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive MSM6998/MSM6999 Push-pull drive • Built-in analog loop back fanction MSM6996V/MSM6997V • Built-in reference voltage source • Low Power Dissipation (60 mW to 70 mW Typ.) • Package options : 16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS) (Product name : MSM6996VRS/MSM6997VRS) (Product name : MSM6998RS/MSM6999RS) 16-pin cer DIP (DIP16-G-300-2.54-1) (Product name : MSM6996HAS/MSM6997HAS) (Product name : MSM6996VAS/MSM6997VAS) (Product name : MSM6998AS/MSM6999AS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K) (Product name : MSM6996VGS-K/MSM6997VGS-K) (Product name : MSM6998GS-K/MSM6999GS-K) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V MSM6997H/V AIN+ AIN– GSX SAMPLE + Pre Filter – 5th LPF COMP 3rd HPF Auto Zero VDD VSS AG DG Voltage REF. C Ladder SAR Transmit PLL XSYNC Transmit Controller XCLOCK PCMOUT T.PWD R.PWD *2 TMC C Ladder – AOUT Receive Controller 5th LPF + Receive PLL *1 PDN/BS PCMIN RCLOCK RSYNC * 1 BS : Only MSM6997H/V * 2 Only MSM6996V, MSM6997V MSM6998, MSM6999 AIN+ AIN– GSX + Pre Filter – SAMPLE 5th LPF COMP 3rd HPF Auto Zero VDD VSS AG DG Voltage REF. C Ladder SAR Transmit PLL XSYNC Transmit Controller XCLOCK PCMOUT T.PWD R.PWD AOUT– + – R AOUT+ – + C Ladder R 5th LPF Receive Controller Receive PLL *3 PDN/BS PCMIN RCLOCK RSYNC *3 BS : Only MSM6999 2/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PIN CONFIGURATION (TOP VIEW) AIN+ 1 16 VSS AIN+ 1 16 VSS AIN+ 1 16 VSS AIN– 2 15 PCMOUT AIN– 2 15 PCMOUT AIN– 2 15 PCMOUT GSX 3 14 PDN/BS GSX 3 14 PDN/BS GSX 3 14 PDN/BS AG 4 13 DG AG 4 13 DG AG 4 13 DG AOUT 5 12 XSYNC AOUT 5 12 XSYNC AOUT+ 5 12 XSYNC NC 6 11 RSYNC TMC 6 11 RSYNC AOUT– 6 11 RSYNC VDD 7 10 XCLOCK VDD 7 10 XCLOCK PCMIN 8 9 RCLOCK PCMIN 8 VDD 7 10 XCLOCK 9 RCLOCK PCMIN 8 9 RCLOCK NC : No connect pin 16-Pin Plastic DIP 16-Pin Plastic DIP 16-Pin Plastic DIP MSM6996VRS MSM6997VRS MSM6998RS MSM6999RS MSM6996HRS MSM6997HRS AIN+ 1 16 VSS AIN+ 1 16 VSS AIN+ 1 16 VSS AIN– 2 15 PCMOUT AIN– 2 15 PCMOUT AIN– 2 15 PCMOUT GSX 3 14 PDN/BS GSX 3 14 PDN/BS GSX 3 14 PDN/BS AG 4 13 DG AG 4 13 DG AG 4 13 DG AOUT 5 12 XSYNC AOUT 5 12 XSYNC AOUT+ 5 12 XSYNC NC 6 11 RSYNC TMC 6 11 RSYNC AOUT– 6 11 RSYNC VDD 7 10 XCLOCK VDD 7 PCMIN 8 VDD 7 10 XCLOCK 9 RCLOCK PCMIN 8 9 RCLOCK 10 XCLOCK 9 RCLOCK PCMIN 8 NC : No connect pin 16-Pin Cer DIP 16-Pin Cer DIP 16-Pin Cer DIP MSM6996VAS MSM6997VAS MSM6998AS MSM6999AS MSM6996HAS MSM6997HAS 3/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 AIN+ 1 24 VSS AIN+ 1 24 VSS AIN– 2 23 PCMOUT AIN– 2 23 PCMOUT GSX 3 22 PDN/BS GSX 3 22 PDN/BS AG 4 21 DG AG 4 21 DG AG 5 20 NC AG 5 20 NC NC 6 19 NC NC 6 19 NC NC 7 18 NC NC 7 18 NC AOUT 8 17 NC AOUT 8 17 NC NC 9 16 XSYNC NC 9 16 XSYNC NC 10 15 RSYNC TMC 10 15 RSYNC VDD 11 14 XCLOCK VDD 11 14 XCLOCK PCMIN 12 13 RCLOCK PCMIN 12 13 RCLOCK NC : No connect pin NC : No connect pin 24-Pin Plastic SOP 24-Pin Plastic SOP MSM6996HGS-K MSM6997HGS-K MSM6996VGS-K MSM6997VGS-K AIN+ 1 24 VSS AIN– 2 23 PCMOUT GSX 3 22 PDN/BS AG 4 21 DG AG 5 20 NC NC 6 19 NC NC 7 18 NC AOUT+ 8 17 NC NC 9 16 XSYNC AOUT– 10 15 RSYNC VDD 11 14 XCLOCK PCMIN 12 13 RCLOCK NC : No connect pin 24-Pin Plastic SOP MSM6998GS-K MSM6999GS-K 4/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX These three pins are used for the transmit level adjustment. AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit amplifier. AIN– is an inverting analog input pin which is connected to the inverting input of the transmit amplifier. GSX is a transmit amplifier output pin. Adjustment can be done by following method. Analog Input C1 AIN+ + AIN– R1 R2 R3 RC Active Filter – GSX Gain = 1 + R2 R3 < 10 AG Notes: 1. R2 + R3 > 10 kW 2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should provide for DC blocking. In this case, cut-off frequency of HPF, composed by R1 and C1, should be less than 30 Hz. 3. R1 should be less than 20 kW AG AG is an analog ground. AG is connected to the analog system ground. AOUT AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V. The output voltage range is 5 VPP. This output can drive the 600 W resistor. AOUT+, AOUT– Analog output for the MSM6998 and MSM6999. The output signal amplitudes are 5 VPP. The AOUT– output is inverted to the AOUT+ output. These outputs can drive a 600 W impedance. VDD VDD is the positive power supply. The voltage supplied to this pin should be +5 V ±5%. 5/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PCMIN PCM signal input. The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous signal RSYNC and clock signal RCLOCK. The data rate of PCM signal ranges from 64 kbps to 2048 kbps. The PCM signal is read at the falling edge of the clock signal and latched into the internal register when finished to read eight bits data. The top of the PCM data is specified by RSYNC pulse timing. RCLOCK Receive clock pulse input. The frequency of this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin. This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing. PCMIN RCLOCK MSD 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 D8 8 9 RSYNC 9 Clocks are required XCLOCK Transmit clock input. The PCM output data rate from the PCMOUT pin is set by this clock frequency. The applicable clock frequencies range from 64 kHz to 2048 kHz. This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing. PCMOUT XCLOCK MSD 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 D8 8 9 XSYNC 9 Clocks are required 6/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. The whole timing signal in the receive section are synchronize by this synchronizing signal. This signal must be synchronize in phase with RCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics of receive section. However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz ±2 kHz, with no guarantee of adherence to the electrical characteristics in this specification as a catalogue value. Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. All transmit timing signals are triggered to synchronize with this signal. This signal should be synchronized in phase with XCLOCK pulse. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics of transmit section. Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state. DG Ground of digital signal. This pin is electrically separated from the AG pin in this device. The DG pin must be connected to the AG pin on the printed circuit board to make common to the AG pin. PDN/BS Power down signal input. When this input is held at low level more than 1 ms, the device is put into the power-down mode. PCMOUT PCM signal output. The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse, according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily possible at this pin. The code companding law and output code format depend on ITU-T Recommendation G.711, and for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by inverting the even bits of signals. PCMIN/PCMOUT Input/Output Level MSM6996 (A-law) MSM6997 (m-law) MSM6998 (A-law) MSM6999 (m-law) +Full scale 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 +0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 –0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 –Full scale 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 7/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 TMC Control signal input for mode selection. This pin select the normal operating mode or analog loop-back mode. TMC Input AIN Mode > 2.0 V Normal operation < 0.8 V Analog loop-back TRANSMIT BPF + – AOUT RECV LPF + – AD PCMOUT DA PCMIN AG Signal flow in normal operating mode Signal flow in analog loop-back mode VSS Negative voltage power supply. The range of power supply voltage is –5 V ±5%. 8/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ABSOLUTE MAXIMUM RATINGS Rating Unit — 0 to 7 V — –7 to 0 V VAIN — VDD –0.3 to VDD + 0.3 V Digital Input Voltage VDIN — –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Parameter Power Supply Voltage Analog Input Voltage Symbol Condition VDD VSS RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Condition Min. Typ. Max. Unit VDD — 4.75 5 5.25 V VSS — –5.25 –5 –4.75 V Operating Temperature Ta — 0 25 70 °C Analog Input Voltage VAIN Connect AIN– and GSX — — 5 VP-P Input High Voltage VIH XSYNC, XCLOCK, PCMIN, 2.0 — VDD V Input Low Voltage VIL RSYNC, RCLOCK, TMC, PDN/BS 0 — 0.8 V Clock Frequency fC XCLOCK, RCLOCK 64 — 2048 kHz Sync Pulse Frequency fS XSYNC, RSYNC — 8 — kHz Clock Duty Ratio DL XCLOCK, RCLOCK 40 50 60 % Digital Input Rise Time tIr XSYNC, XCLOCK, PCMIN, — — 50 ns tIf RSYNC, RCLOCK (Fig. 1) — — 50 ns tXS XCLOCKÆXSYNC (Fig. 2) 50 — — ns Digital Input Fall Time Transmit Sync Timing Receive Sync Timing tSX XSYNCÆXCLOCK (Fig. 2) 100 — — ns tRS RCLOCKÆRSYNC (Fig. 2) 50 — — ns tSR RSYNCÆRCLOCK (Fig. 2) 100 — — ns Transmit Sync Pulse Width tWX — 1/fc — — ms Receive Sync Pulse Width tWR — 1/fc — — ms PCMIN Set-up Time tDS — 100 — — ns PCMIN Hold Time tDH — 100 — — ns BS Set-up Time * tBS — 200 — — ns BS Hold Time * tBH — 200 — — ns AOUT, AOUT+, AOUT– 600 — — W GSK 10 — — kW — — — 100 pF 1 — — kW pF Analog Output Load RAL CAL Digital Output Load Allowable Analog Input Offset Voltage RDL — CDL VIO — — 100 Transmit gain stage, Gain = 1 –200 — +200 Transmit gain stage, Gain = 10 –20 — +20 mV * : The value for the MSM6997 and MSM6999 9/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70˚C) Parameter Power Supply Current (Operating) Symbol IDD1 ISS1 Condition XCLOCK, RCLOCK 2048 kHz * * Min. Typ. — 7.0 Max. 12 14 12 6.5 — — 3.0 — — 1.5 — — V V 14 IDD2 (Stand-by) ISS2 Input High Voltage VIH 2.2 Input Low Voltage VIL — — 0.8 IIH — < 0.5 2.0 — < 0.2 0.5 — 0.1 0.4 Input Leakage Current Output Low Voltage IIL — VOL mA — Power Supply Current — Unit mA mA V Output Leakage Current IOH — <5 10 mA Analog Output Offset Voltage VOFF –150 0 +150 mV Input Capacitance CIN — — 5 — pF Analog Input Resistance RIN fIN < 3.4 kHz — 1 — MW * : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999 10/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 AC Characteristics (VDD = +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70°C) Condition Parameter Transmit Frequency Response Receive Frequency Response Symbol Freq. Level (Hz) (dBm0) Ratio *1 Receive Signal to Noise Ratio *1 Transmit Gain Tracking Max. 60 20 — — LOSS T2 300 –0.15 — +0.25 LOSS T3 820 LOSS T4 2020 LOSS T5 LOSS T6 0 Reference –0.15 — +0.25 3000 –0.15 — +0.25 3400 0 — 0.8 –0.1 — +0.2 LOSS R1 300 LOSS R2 820 LOSS R3 2020 LOSS R4 LOSS R5 — +0.2 3000 –0.1 — +0.2 3400 0 — 0.8 0 3 36 — — SD T2 1020 0 36 — — SD T3 or –30 36 — — SD T4 820 –40 31 — — SD T5 –45 26 — — SD R1 3 36 — — SD R2 1020 0 36 — — SD R3 or –30 36 — — SD R4 820 –40 31 — — SD R5 –45 26 — — GT T1 3 –0.2 — +0.2 GT T2 1020 –10 GT T3 or –40 –0.2 — +0.2 GT T4 820 –50 –0.4 — +0.4 –55 –0.8 — +0.8 3 –0.2 — +0.2 GT R1 –10 GT R3 or –40 –0.2 — +0.2 GT R4 820 –50 –0.4 — +0.4 –55 –0.8 — +0.8 GT R5 dB dB dB dB Reference 1020 GT R2 Unit Reference –0.1 GT T5 Receive Gain Tracking Typ. LOSS T1 SD T1 Transmit Signal to Noise Min. dB Reference dB Note: *1 The measurement is taken with P-message filter 11/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 AC Characteristics (Continued) (VDD = +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70°C) Condition Symbol Parameter Freq. Level (Hz) (dBm0) Min. Typ. Max. Idle Channel Transmit NIDL T — — — — –75 Noise *1 Receive NIDL R — — — — –75 Transmit AV T 1020 or 820 0 –0.5 0 +0.5 Receive AV R 1020 or 820 0 –0.5 0 +0.5 0 — — 0.52 Absolute Gain *2 Absolute Delay Time Transmit Group Delay Time *3 — tGD T1 500 — — 0.75 tGD T2 600 — — 0.35 tGD T3 1000 — — 0.125 tGD T4 2600 — — 0.125 tGD T5 2800 — — 0.75 tGD R1 500 — — 0.75 — — 0.35 — — 0.125 0 dB ms ms 600 tGD R3 1000 tGD R4 2600 — — 0.125 tGD R5 2800 — — 0.75 T to R CR T 1020 or 820 — — 66 R to T CR R 1020 or 820 — — 66 S 300 to 3400 0 — — –30 dBmO –4 — — –35 dBmO 0 30 — — dB — 30 — 200 — 30 — mVp-p — 30 — — 30 — Out-of-Band Spurious Intermodulation Distortion Discrimination IMD 1 DIS 0 — fa = 470 fb = 320 4.6 kHz to 72 kHz VDD Noise Rejection Transmit PPSR T Ratio Receive PPSR R 0 to 300 VSS Noise Rejection Transmit NPSR T Ratio Receive NPSR R kHz tSD Digital Output Delay Time Digital Output Fall Time dBmOp tGD R2 Receive Group Delay Time *3 Crosstalk Attenuation tD Unit 50 150 300 tXD1 RDL = 2 kW 50 100 300 tXD2 CDL = 100 pF 50 100 300 tXD3 50 180 300 tDO — 20 100 ms dB dB ns ns Notes: *1 The measurement is taken with P-message filter *2 MSM6996/MSM6998 0 dB = 1.231 Vrms MSM6997/MSM6999 0 dB = 1.227 Vrms *3 Reference : 1800 Hz 12/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 TIMING DIAGRAM Wave Time Measurement Level 2.4 V 2.4 V 1.4 V 1.4 V 0.4 V 0.4 V tWX tWR tIr tIf tDOf Note: Timing between signal waves is judged at 1.4 V Figure 1 Basic Timing XCLOCK 1 2 3 tXS tSX 4 5 6 7 8 9 10 1/fC ,,, XSYNC PCMOUT Note 1): RCLOCK tWX tXD1 tXD2 MSD tSD tXD3 D2 D3 D4 D5 D6 D7 D8 8 9 Transmitter Section When tXS £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tSD. 1 2 3 4 5 6 7 10 tRS tSR RSYNC PCMIN tWR MSD Receiver Section tDS tDH D2 D3 D4 D5 D6 D7 D8 Invalid Data Note 2): Note 3): Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be asynchronous mutually. The threshold level is 1.4 V. Figure 2 13/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 Timing for 7 bits Decode (Specified for MSM6997/6999) ,,,, RSYNC PCMIN 12 34 5678 12 34 5678 12 34 5678 12 34 5678 9 12 34 5678 9 12 34 5678 9 RCLOCK ,,,, Allowable Range BS tBS tBH Disable Decoder Operation 8 Bits Decode 7 Bits Decode 8 Bits Decode Figure 3 ~ RSYNC 125 ms ~ Timing for Bit-steal Function Setting more than 10ms ~ ~ ~ ~ PCMIN RCLK PDN/BS more than 10ms Notes: Follow these procedures when the Bit-steal function is used: 1. Set the RSYNC pin to OFF ("L") after the PDN/BS pin is set at "H" for 10ms or more. 2. Set the RSYNC to ON after a pulse is input at the PDN/BS pin. 3. The Bit-steal function starts to operate. 14/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 APPLICATION CIRCUIT Basic Circuit PCM OUT IN XTAL 2.048 MHz ANALOG IN OUT 2 kW +5 V OUT 10 M IN GSX AIN– AIN+ AOUT PDN/BS 4049 4049 CLOCK X R SYNC X R DG VSS VDD AG +5 V 16 6 Q4 14 Q4 + – 10 mF – + 10 mF M4520RS R E C 15 10 9 +5 V R 8 7 E C 2 1 DG Note 1 Power Down 1 : NOR 0 : Power Down 0V –5 V +5 V Notes: 1. Insert diode for preventing from Latch-Up at turn on Power. Recommended Diode Specification. • High Speed Switching • Allowerable Power dissipation 250 mW to 300 mW • Forward Voltage Drop < 1.3 V (at 100 mA) 2. AG and DG must be connected in the printed circuit board mounted this device, for preventing from Latch-Up. 15/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 Example of Multi-Channel Connections (8ch) +5 V 74161(1) 2 1 7 10 9 512 kHz +5 V CK CLR EP ET LO QA QB QC QD CO 14 13 12 11 15 74161(2) 2 1 7 10 9 +5 V CK QA 14 CLR QB 13 EP ET LO 9 CK QA QB QC QD +5 V QE 9 CLR QF 1 QG A 2 B QH 3 4 5 6 10 11 12 13 1 kW PCM XC OUT XS No.1 RC PCM RS IN No.4 No.5 No.6 No.7 Multiple PCM No.2 74164 No.3 No.8 Example of Multi-Channel Timing 74161(1) QC Output 74161(2) QB Output QA 74164 Output QB QC QH Multiple PCM 7 8 No.1 MSD 2 3 4 5 6 7 8 No.1 2 3 4 5 6 7 8 LSD 512K CLK 16/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 Transmit and Receive Level Adjustment (MSM6996H/V, MSM6997H/V) a. Transformer of turns ratio 1 : 1 1:1 4WS 600 W 1 AIN+ 2 AIN– 3 GSX 600 W AG 1:1 R1 20 kW 600 W 5 4WR 600 W AOUT 600 W Attenuator When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +7.17 + LT (dBm) 4 WR maximum output level = +1.15 – LT (dBm) LT : Transformer loss b. Transformer of turns ratio 1 : 2 2:1 4WS 600 W 300 W 2:1 AG 1 AIN+ 2 AIN– 3 GSX R1 20 kW 300 W 5 4WR 600 W AOUT When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +10.18 + LT (dBm) 4 WR maximum output level = +4.16 – LT (dBm) LT : Transformer loss 300 W Attenuator Transmit and Receive Level Adjustment (MSM6998, MSM6999) 1:1 4WS 600 W 600 W AG 1:1 4WR 600 W 1 AIN+ 2 AIN– 3 GSX R1 20 kW 300 W 5 AOUT+ 300 W 6 AOUT– When R1 is open and the attenuator is set at 0 dB, 4 WS maximum input level = +7.17 + LT (dBm) 4 WR maximum output level = +7.17 – LT (dBm) LT : Transformer loss 600 W Attenuator 17/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connected to the system ground with low impedance. • Mount the device directly on the board when mounted on printed circuit board. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V and the voltage on the VSS pin more than +0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 18/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PACKAGE DIMENSIONS (Unit : mm) DIP16-P-300-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.99 TYP. 19/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 (Unit : mm) DIP16-G-300-2.54 9 1 8 7.50MAX 16 7.62 20.00MAX 0.80TYP 2.54 4.10±0.40 5.10MAX 2.54MIN 1.50±0.10 0.51MIN 1.00±0.10 0.50±0.10 SEATING PLANE +0.1 0.25-0 5 .05 ° 15 0~ 0.25 M 20/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/21