E2U0016-28-81 ¡ Semiconductor MSM7566/7567 ¡ Semiconductor This version: Aug. 1998 MSM7566/7567 Previous version: Nov. 1996 Single Rail CODEC GENERAL DESCRIPTION The MSM7566 and MSM7567 are single-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filter for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices are optimized for telephone terminals in digital wireless systems. The MSM7566 and MSM7567 use newly-designed operational amplifiers to maintain small current deviations caused by power voltage fluctuations. The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B. The analog output signal, which is of a differential type, directly drives a handset receiver. FEATURES • Single power supply: +2.7 V to +3.8 V • Low power consumption Operating mode: 15 mW Typ. 24 mW Max. VDD = 3.0 V Power save mode: 6 mW Typ. 18 mW Max. VDD = 3.0 V Power down mode: 0.03 mW Typ. 0.2 mW Max. VDD = 3.0 V • ITU-T Companding law MSM7566: m-law MSM7567: A-law • Transmission characteristics comply with ITU-T G.714 • Built-in PLL eliminates a master clock • Serial data rate: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz • Adjustable transmit gain • Adjustable receive gain • Built-in reference voltage supply • Built-in analog loop back test mode • Differential type analog output. Directly drives a piezoelectric type receiver equivalent to 1.2 kW +55 nF • Analog output amplifiers can operate in the power save mode • Pin-for-pin compatible with the MSM7541 and the MSM7542 • Package options: 20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7566RS) (Product name : MSM7567RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7566GS-K) (Product name : MSM7567GS-K) 26-pin plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product name : MSM7566TS-K) (Product name : MSM7567TS-K) 1/19 ¡ Semiconductor MSM7566/7567 BLOCK DIAGRAM AIN+ AIN– + – RC Active BPF (8th) GSX AD Conv. Transmit Controller Auto Zero PLL PCMOUT XSYNC BCLOCK TMC RTIM VFRO – + SG SG Power Down PWI AOUT– – + LPF (5th) DA Conv. Receive Controller RSYNC PCMIN PDN VDD AG DG PWD Logic SG SG AOUT+ – + SG Voltage Ref. Signal Ground SGC SG 2/19 ¡ Semiconductor MSM7566/7567 PIN CONFIGURATION (TOP VIEW) SG 1 20 SGC AOUT+ 2 19 AIN+ AOUT– 3 18 AIN– PWI 4 17 GSX VFRO 5 16 TMC VDD 6 DG 7 15 NC 14 AG SG 1 24 SGC SG 1 26 SGC AOUT+ 2 23 AIN+ AOUT+ 2 25 AIN+ AOUT– 3 22 AIN– AOUT– 3 24 AIN– NC 4 21 GSX PWI 4 23 GSX PWI 5 20 NC VFRO 5 22 TMC VFRO 6 NC 7 18 NC VDD 8 17 NC DG 9 16 AG PDN 10 RSYNC 11 PDN 8 RSYNC 9 13 BCLOCK PCMIN 12 12 XSYNC 19 TMC 15 BCLOCK 14 XSYNC 11 PCMOUT 18 NC DG 10 17 AG PDN 11 RSYNC 12 13 PCMOUT PCMIN 13 NC : No connect pin 24-Pin Plastic SOP PCMIN 10 VDD 9 16 BCLOCK 15 XSYNC 14 PCMOUT NC : No connect pin 26-Pin Plastic TSOP NC : No connect pin 20-Pin Plastic Skinny DIP 3/19 ¡ Semiconductor MSM7566/7567 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp and is used to adjust the level, as shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving and power down modes, the GSX output is at AG voltage. 1) Inverting input type C1 R2 Analog input R1 GSX AIN– AIN+ SG – + R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) Gain = R2/R1 £ 10 2) Non inverting input type C2 Analog input R5 R4 R3 AIN+ AIN– GSX C3 SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) C3 : 10 to 20 pF Gain = 1 + R4 / R3 £ 10 AG Note: In the non-inverting input type, connect a 10 pF to 20 pF capacitor between the GSX pin and the AG pin as illustrated in the figure above. This prevents the generation of distortion during high power supply voltage and high level signal (+3 to –3dBm0) input. In the inverting input type, eliminate the capacitor. AG Analog signal ground for digital signal circuits. This ground is separate from the digital signal ground (DG) in this device. The AG pin must be connected to the DG pin on the printed circuit board and then connected to the analog ground. 4/19 ¡ Semiconductor MSM7566/7567 VFRO Receive filter output. The output signal has an amplitude of 2.4 VPP above and below the signal ground voltage (SG) when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more. For driving a load of 20 kW or less, connect a resistor of 20 kW or more should be connected between the pins VFRO and PWI. When adding the frequency characteristics to the receive signal, refer to the application example. During power saving mode, the output of VFRO is at the voltage level of SG. During power down mode, the output is in a high impedance state. PWI, AOUT+, AOUT– PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to the AOUT– pin, and leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2 kW +55 nF, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. Refer to the application example. VI Receive Filter VFRO PWI AOUT– SG – + AOUT+ SG – + R6 R6 > 20 kW ZL ≥ 2.4 kW R7 Gain = VO/VI = 2 ¥ R7/R6 £ 2 VO ZL The other external signals can be output from AOUT+ and AOUT– during power saving, since these driver amplifiers are in the operational state. During power down mode, the output of AOUT+ and AOUT– is at the voltage level of SG through high impedance. The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The output load resistor has a minimum value of 1.2 kW. If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE. VDD Power supply for +2.7 V to +3.8 V. (Typically 3.0 V) PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLOCK signal. The data rate of the PCM signal is equal to the frequency of the BCLOCK signal. The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. 5/19 ¡ Semiconductor MSM7566/7567 BCLOCK Shift clock signal input for the PCMIN and PCMOUT signal. When the frequency of the SYNC pulse is at 8 kHz, the BCLOCK frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. Even if the RSYNC signal is not present, the device is not in power saving state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. TMC Control signal input for mode selection. This pin select the normal operating mode or the analog loop-back mode. In the analog loop-back mode, the receive filter output is connected to the transmit filter input and the digital signal input to the PCMIN pin is converted from a digital to an analog signal (D/ A conversion). Next, the analog signal is converted to a digital signal (A/D conversion) through the receive filter and transmit filter. The result is output to the PCMOUT pin. When in the analog loop-back mode, the VFRO pin outputs the SG level. (signal ground) TMC Input Mode < 0.16 ¥ VDD Normal operation > 0.45 ¥ VDD Analog loop-back 6/19 ¡ Semiconductor MSM7566/7567 DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLOCK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLOCK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down modes. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7567(A-law) outputs the character signal, inverting the even bits. PCMIN/PCM OUT Input/Output Level MSM7566 (m-law) MSD MSM7567 (A-law) MSD +Full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 –0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 –Full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 SG Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±200 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power saving or power down modes. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. During power saving and power down modes, the output of this pin is at the voltage level of SG with an output resistance of about 500 kW. 7/19 ¡ Semiconductor MSM7566/7567 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — 0 to 7 V — –0.3 to VDD + 0.3 V Digital Input Voltage Storage Temperature VDIN — –0.3 to VDD + 0.3 V TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Condition Voltage must be fixed — Min. Typ. Max. Unit 2.7 3.0 3.8 V –30 +25 +85 °C — — 1.4 VPP 0.45 ¥ VDD — VDD V 0 — 0.16 ¥ VDD V Analog Input Voltage VAIN Input High Voltage VIH Input Low Voltage VIL Clock Frequency FC BCLOCK Sync Pulse Frequency FS XSYNC, RSYNC 6.0 8.0 10.0 Clock Duty Ratio DC BCLOCK 40 50 60 % Digital Input Rise Time tIr XSYNC, RSYNC, BCLOCK, — — 50 ns Connect AIN– and GSX XSYNC, RSYNC, BCLOCK, PCMIN, PDN, TMC 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, kHz 1536, 1544, 200 kHz tIf PCMIN, PDN, TMC — — 50 ns tXS BCLOCKÆXSYNC, See Timing Diagram 100 — — ns tSX XSYNCÆBCLOCK, See Timing Diagram 100 — — ns tRS BCLOCKÆRSYNC, See Timing Diagram 100 — — ns tSR RSYNCÆBCLOCK, See Timing Diagram 100 — — ns Sync Pulse Width tWS XSYNC, RSYNC 1 BCLK — 100 ms PCMIN Set-up Time tDS — 100 — — ns tDH — 100 — — ns RDL Pull-up resistor 0.5 — — kW Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time PCMIN Hold Time Digital Output Load CDL Analog Input Allowable DC Offset Voff Allowable Jitter Width — — — — 100 pF Transmit gain stage, Gain = 1 –100 — +100 mV Transmit gain stage, Gain = 10 –10 — +10 mV XSYNC, RSYNC, BCLOCK — — 1.0 ms 8/19 ¡ Semiconductor MSM7566/7567 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol IDD1 IDD4 Power Supply Current Min. Typ. Max. Unit VDD = 3.8 V — 13.0 17.0 mA VDD = 3.0 V — 5.0 8.0 mA — 2.0 6.0 mA — 0.01 0.05 mA — VDD V Condition Operating mode Power-save mode, PDN = 1, IDD2 XSYNC or BCLOCK Æ OFF IDD3 Power-down mode, PDN = 0 0.45 ¥ Input High Voltage VIH — Input Low Voltage VIL — 0.0 — High Level Input Leakage Current IIH — — — 2.0 mA Low Level Input Leakage Current IIL — — — 0.5 mA Digital Output Low Voltage VOL Pull-up resistance > 500 W VDD 0.16 ¥ VDD V 0.0 0.2 0.4 V Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF 9/19 ¡ Semiconductor MSM7566/7567 Transmit Analog Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Input Resistance RINX AIN+, AIN– 10 — — MW Output Load Resistance RLGX GSX with respect to SG 20 — — kW Output Load Capacitance CLGX — — 50 pF Output Amplitude VOGX –0.7 — +0.7 V Offset Voltage VOSGX –20 — +20 mV Gain = 1 Receive Analog Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Input Resistance Symbol Output Load Capacitance Min. Typ. Max. Unit 10 — — MW 20 — — kW 1.2 — — kW VFRO — — 100 pF AOUT+, AOUT– — — 50 pF –1.0 — +1.0 V –1.3 — +1.3 V –100 — +100 mV –100 — +100 mV RINPW PWI RLVF Output Load Resistance Condition RLAO CLVF CLAO VOVF Output Amplitude VOAO VFRO with respect to SG AOUT+, AOUT– (each) with respect to SG VFRO, RL = 20 kW with respect to SG AOUT+, AOUT–, RL = 1.2 kW with respect to SG VOSVF VFRO with respect to SG Offset Voltage VOSAO AOUT+, AOUT–, Gain = 1 with respect to SG 10/19 ¡ Semiconductor MSM7566/7567 AC Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Transmit Frequency Response Receive Frequency Response Loss T1 Freq. (Hz) 60 Loss T2 300 Loss T3 1020 Loss T4 2020 Loss T5 Loss T6 Symbol Unit 20 26 — dB –0.15 +0.1 +0.20 dB Reference 0 dB dB 3000 –0.15 +0.08 +0.20 dB 3400 0 0.3 0.80 dB Loss R1 300 –0.15 –0.07 +0.20 Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 Reference 0 +0.03 +0.20 dB 3000 –0.15 +0.06 +0.20 dB 3400 0.0 0.4 0.80 dB SD T1 3 35 43 — SD T2 0 35 42 — 39 — SD T4 –30 1020 –40 35 *2 *1 *2 29 31.0 27.5 — –45 SD R1 3 36 43 — SD R2 0 36 41 — 41 — –30 1020 –40 SD R5 –45 GT T1 3 GT T3 24 31.5 SD T5 SD R4 36 *2 *1 *2 30 25 –0.3 –10 1020 26 34.5 33.5 30.5 27.5 –0.03 — dB — +0.3 Reference –0.3 +0.10 +0.3 GT T4 –50 –0.6 +0.15 +0.6 GT T5 –55 –1.2 +0.20 +1.2 GT R1 3 –0.3 0 +0.3 –10 1020 dB — –40 GT R3 dB dB –0.15 GT R2 Receive Gain Tracking Max. +0.20 GT T2 Transmit Gain Tracking Typ. 0 SD R3 Receive Signal to Distortion Ratio Min. –0.15 SD T3 Transmit Signal to Distortion Ratio Level Condition (dBm0) dB Reference –40 –0.3 –0.15 +0.3 GT R4 –50 –0.6 –0.25 +0.6 GT R5 –55 –1.2 –0.35 +1.2 dB *1 Psophometric filter is used *2 Upper specified for the MSM7566, lower for the MSM7567 11/19 ¡ Semiconductor MSM7566/7567 AC Characteristics (Continued) (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Idle Channel Noise Symbol Freq. (Hz) Nidle T — Nidle R — Level Condition (dBm0) AIN = SG — *1 — AV T (Deviation of Temperature and Power) Max. — –73 –70 — –78 –75 0.338 0.35 0.362 0.483 0.50 0.518 AV Tt *4 1020 0 –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.60 ms — 0.19 0.75 — 0.11 0.35 — 0.02 0.125 — 0.05 0.125 — 0.07 0.75 — 0.00 0.75 — 0.00 0.35 — 0.00 0.125 — 0.09 0.125 VDD = 2.7 V to 3.8 V Ta = –30 AV Rt Unit dBmOp Vrms Ta = 25°C AV R Absolute Level Typ. *1 *3 VDD = 3.0 V Absolute Level (Initial Difference) Min. to 85°C *4 A to A Absolute Delay Td 1020 0 BCLOCK = 64 kHz Transmit Group Delay Receive Group Delay Crosstalk Attenuation *1 *2 *3 *4 *5 tgd T1 500 tgd T2 600 tgd T3 1000 tgd T4 2600 tgd T5 2800 tgd R1 500 tgd R2 600 tgd R3 1000 tgd R4 2600 tgd R5 2800 CR T CR R 1020 *5 0 *5 0 0 — 0.12 0.75 TRANS Æ RECV 75 79 — RECV Æ TRANS 75 82 — ms ms dB Psophometric filter is used Upper is specified for the MSM7566, lower for the MSM7567 Input "0" code to PCMIN AVR is defined at VFRO output Minimum value of the group delay distortion 12/19 ¡ Semiconductor MSM7566/7567 AC Characteristics (Continued) (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Freq. Level Condition (Hz) (dBm0) 4.6 kHz to 0 to DIS 0 72 kHz 4000 Hz Symbol Min. Typ. Max. Unit 30 32 — dB — –37.5 –35 dBmO — –52 –35 dBmO –1.0 — +1.0 dB — 30 — dB tSD 50 — 200 tXD1 50 — 200 50 — 200 50 — 200 S IMD 300 to 0 3400 fa = 470 –4 fb = 320 4.6 kHz to 100 kHz 2fa – fb TMC = 1 D-to-D Mode Gain — 1020 0 PCMIN to PCMOUT Power Supply Noise Rejection Ratio Digital Output Delay Time PSR T 0 to PSR R 50 kHz tXD2 50 mVPP *6 CL = 100 pF + 1 LSTTL tXD3 ns *6 The measurement under idle channel noise 13/19 , , ¡ Semiconductor MSM7566/7567 TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLOCK 1 2 tXS XSYNC 4 5 6 7 8 9 10 11 9 10 11 tSX tWS tXD1 PCMOUT 3 tSD MSD D2 tXD2 D3 D4 D5 D6 tXD3 D8 D7 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. Receive Timing BCLOCK 1 tRS RSYNC 2 3 4 6 7 8 tSR tWS tDS PCMIN 5 MSD D2 tDH D3 D4 D5 D6 D7 D8 14/19 ¡ Semiconductor MSM7566/7567 APPLICATION CIRCUIT Analog interface Digital interface +3.0 V MSM7566/7567 0.1 mF AIN+ Analog input PCMOUT 100 kW PCM signal output XSYNC 8 kHz SYNC signal input AIN– 20 kW RSYNC GSX SG BCLOCK BCLOCK input PCMIN PCM data input To AG 10 pF Analog output AOUT– PDN Power Down control input PWI TMC Analog loop-back control input VFRO 20 kW or more 51 kW SGC 0.1 mF 0V +3.0 V AG 10 mF 1 mF + DG VDD 0 to 10 W FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT Microphone amp M Transmit frequency characteristic Adjustment determined with C1, C2, R1, R2. R1 AIN– C1 C2 R2 GSX AIN+ SG AOUT+ C4 R4 AOUT– Receive frequency characteristic Adjustment determined with C3, C4, R3, R4. PWI VFRO R3 C3 R5 C5 Additional input signal Note: The additional input signal can be output from AOUT– and AOUT+, since the output of VFRO is unknown during power saving mode and the output of the AOUT– and AOUT+ is in the operational state. 15/19 ¡ Semiconductor MSM7566/7567 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 16/19 ¡ Semiconductor MSM7566/7567 PACKAGE DIMENSIONS (Unit : mm) DIP20-P-300-2.54-S1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.49 TYP. 17/19 ¡ Semiconductor MSM7566/7567 (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM7566/7567 (Unit : mm) TSOPII26/20-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19