E2U0013-28-81 ¡ Semiconductor MSM7508B/7509B ¡ Semiconductor This version: Aug. 1998 MSM7508B/7509B Previous version: Nov. 1996 Single Rail CODEC GENERAL DESCRIPTION The MSM7508B and MSM7509B are single-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices are optimized for telephone terminals in ISDN and digital wireless systems. The MSM7508B/MSM7509B are the transmission-clocks extended versions of the MSM7508/ MSM7509. It is recommended to use the MSM7508/MSM7509 for the transmission clocks of 64, 128, 256kHz. FEATURES • Single power supply: +5 V ±5% • Low power consumption Operating mode: 17.5 mW Typ. 37 mW Max. Power down mode: 1.5 mW Typ. 3 mW Max. • ITU-T Companding law MSM7508B: m-law MSM7509B: A-law • Built-in PLL eliminates a master clock • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz • Adjustable transmit gain • Built-in reference voltage supply • Package options: 16-pin plastic DIP (DIP16-P-300-2.54-W1) (Product name : MSM7508BRS) (Product name : MSM7509BRS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7508BGS-K) (Product name : MSM7509BGS-K) 28-pin plastic QFJ (PLCC) (QFJ28-P-S450-1.27) (Product name : MSM7508BJS) (Product name : MSM7509BJS) Note: The product names are indicated in PIN CONFIGURATION. 1/17 ¡ Semiconductor MSM7508B/7509B BLOCK DIAGRAM AIN+ AIN– + – RC Active BPF (8th) GSX SGC SG Signal Ground AD Conv. Transmit Controller Auto Zero TPLL RPLL Voltage Ref. LPF (5th) AOUT + – PCMOUT XSYNC BCLOCK PWD DA Conv. PWD Logic Receive Controller RSYNC PCMIN PDN VDD AG DG 2/17 ¡ Semiconductor MSM7508B/7509B PIN CONFIGURATION (TOP VIEW) SGC 1 16 AIN+ SGC 1 24 AIN+ SG 2 15 AIN– NC 2 23 AIN– AOUT 3 14 GSX SG 3 22 NC VDD 4 13 NC NC 4 21 GSX DG 5 12 AG AOUT 5 20 NC 11 BCLOCK VDD 6 19 NC RSYNC 7 10 XSYNC DG 7 18 AG PCMIN 8 9 PCMOUT NC 8 17 NC NC 9 16 BCLOCK PDN 6 NC : No connect pin PDN 10 15 NC 16-Pin Plastic DIP RSYNC 11 14 XSYNC PCMIN 12 13 PCMOUT 24-Pin Plastic SOP 26 GSX 27 AIN– 28 AIN+ 1 SGC 2 SG 3 NC 4 AOUT NC : No connect pin 22 NC NC 9 21 NC NC 10 20 NC DG 11 19 AG BCLOCK 18 NC 8 XSYNC 17 23 NC PCMOUT 16 NC 7 NC 15 24 NC PCMIN 14 NC 6 RSYNC 13 25 NC PDN 12 VDD 5 NC : No connect pin 28-Pin Plastic QFJ (PLCC) 3/17 ¡ Semiconductor MSM7508B/7509B PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp and is used to adjust the level, as shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving and power down modes, the GSX output is in a high impedance state. 1) Inverting input type C1 R2 Analog input R1 GSX AIN– AIN+ SG – + R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) Gain = R2/R1 £ 10 2) Non inverting input type C2 AIN+ AIN– GSX Analog input R5 R4 R3 SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) Gain = 1 + R4 / R3 £ 10 AG Analog signal ground. AOUT Analog output. The output signal amplitude is a maximum of 2.4 VPP above and below the signal ground voltage level (VDD/2). The output load resistance is a minimum of 20 kW. During power saving or power down mode, the output of AOUT is at the voltage level of signal ground. 4/17 ¡ Semiconductor MSM7508B/7509B VDD Power supply for +5 V. PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLOCK signal. The data rate of the PCM signal is equal to the frequency of the BCLOCK signal. The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLOCK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 5/17 ¡ Semiconductor MSM7508B/7509B DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLOCK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLOCK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down modes. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7509B (A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT Input/Output Level MSM7508B (m-law) MSD MSM7509B (A-law) MSD +Full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 –0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 –Full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 SG Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±300 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power saving or power down modes. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. 6/17 ¡ Semiconductor MSM7508B/7509B ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD — 0 to 7 V Analog Input Voltage VAIN — –0.3 to VDD + 0.3 V Digital Input Voltage VDIN — –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Analog Input Voltage VAIN Input High Voltage VIH Input Low Voltage VIL Condition Voltage must be fixed — Connect AIN– and GSX XSYNC, RSYNC, BCLOCK, PCMIN, PDN Min. Typ. Max. Unit 4.75 5.0 5.25 V –10 +25 +70 °C — — 2.4 VPP 2.2 — VDD V 0 — 0.8 V 64, 128, 256, 512, 1024, Clock Frequency FC BCLOCK 2048, 96, 192, 384, 768, kHz 1536, 1544, 200 Sync Pulse Frequency FS XSYNC, RSYNC 7.0 8.0 10.0 Clock Duty Ratio DC BCLOCK 40 50 60 % Digital Input Rise Time tIr XSYNC, RSYNC, BCLOCK, — — 50 ns Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time tIf PCMIN, PDN — — 50 ns tXS BCLOCKÆXSYNC, See Timing Diagram 100 — — ns tSX XSYNCÆBCLOCK, See Timing Diagram 100 — — ns tRS BCLOCKÆRSYNC, See Timing Diagram 100 — — ns 100 — — ns 1 BCLK — 100 ms — 100 — — ns — 100 — — ns AOUT 20 — — kW GSX 20 — — kW CAL AOUT, GSX — — 100 pF RDL Pull-up resistor 0.5 — — kW CDL — — — 100 pF Transmit gain stage, Gain = 1 –100 — +100 mV Transmit gain stage, Gain = 10 –10 — +10 mV XSYNC, RSYNC, BCLOCK — — 500 ns tSR RSYNCÆBCLOCK, See Timing Diagram tWS XSYNC, RSYNC PCMIN Set-up Time tDS PCMIN Hold Time tDH Sync Pulse Width Analog Output Load Digital Output Load kHz RAL Analog Input Allowable DC Offset Voff Allowable Jitter Width — 7/17 ¡ Semiconductor MSM7508B/7509B ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Power Supply Current Min. Typ. Max. Unit IDD1 Operating mode — 3.5 7.0 mA IDD2 Power-down mode, PDN = 0 — 0.3 0.5 mA — 0.8 1.2 mA Symbol IDD3 Condition Power-save mode, PDN = 1, SYNC Æ OFF Input High Voltage VIH — 2.2 — VDD V Input Low Voltage VIL — 0.0 — 0.8 V High Level Input Leakage Current IIH — — — 2.0 mA Low Level Input Leakage Current IIL — — — 0.5 mA Digital Output Low Voltage VOL 0.0 0.2 0.4 V — — 10 mA –100 — +100 mV — 5 — pF — 10 — MW Digital Output Leakage Current Pull-up resistance > 500 W — IO Analog Output Offset Veltage VOFF Input Capacitance CIN Analog Input Resistance RIN AOUT with respect to SG — AIN+, AIN– 8/17 ¡ Semiconductor MSM7508B/7509B AC Characteristics (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Transmit Frequency Response Receive Frequency Response Loss T1 Freq. (Hz) 60 Loss T2 300 Loss T3 1020 Loss T4 2020 Loss T5 Loss T6 Symbol Receive Signal to Distortion Ratio Min. Unit 20 26 — dB +0.07 +0.20 dB Reference 0 dB –0.04 +0.20 dB 3000 –0.15 +0.06 +0.20 dB 3400 0 0.40 0.80 dB Loss R1 300 –0.15 –0.03 +0.20 Loss R2 1020 Loss R3 2020 –0.15 –0.02 +0.20 dB Loss R4 3000 –0.15 +0.15 +0.20 dB Loss R5 3400 0.0 0.56 0.80 dB Reference 0 3 35 43 — SD T2 0 35 41 — –30 35 38 — SD T4 1020 –40 28 30.0 *1 29.5 *2 25.0 — SD T5 –45 SD R1 3 36 43 — SD R2 0 36 41 — SD R3 –30 36 40 — –40 30 SD R4 1020 23 SD R5 –45 GT T1 3 GT T3 *2 33.5 32 25 30 24 27 –0.2 +0.01 — — +0.2 –0.2 0.0 +0.2 GT T4 –50 –0.4 –0.03 +0.4 GT T5 –55 –1.2 +0.15 +1.2 GT R1 3 –0.2 0 +0.2 GT R2 –10 dB Reference –40 –0.2 –0.06 +0.2 GT R4 –50 –0.4 –0.20 +0.4 GT R5 –55 –0.8 –0.27 +0.8 1020 dB — –40 GT R3 dB Reference –10 1020 24.5 dB dB SD T1 GT T2 Receive Gain Tracking Max. –0.15 *1 Transmit Gain Tracking Typ. –0.15 SD T3 Transmit Signal to Distortion Ratio Level Condition (dBm0) dB *1 Psophometric filter is used *2 Upper is specified for the MSM7508B, lower for the MSM7509B 9/17 ¡ Semiconductor MSM7508B/7509B AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Idle Channel Noise Symbol Freq. (Hz) Level Condition (dBm0) AIN = SG — *1 *2 Nidle T — Nidle R — — 1020 0 *2 *3 AV T Absolute Level (Initial Difference) Min. — Typ. Max. –72.5 –70 –70.5 –69 — –76.5 –74 0.5671 0.6007 0.6363 0.5671 0.6007 0.6363 — — 0.60 — 0.19 0.75 — 0.11 0.35 — 0.02 0.125 Unit dBmOp Vrms AV R A to A Absolute Delay Td 1020 tgd T1 500 0 BCLOCK ms = 64 kHz Transmit Group Delay Receive Group Delay Crosstalk Attenuation *1 *2 *3 *4 *4 tgd T2 600 tgd T3 1000 tgd T4 2600 — 0.05 0.125 tgd T5 2800 — 0.07 0.75 tgd R1 500 tgd R2 600 tgd R3 1000 tgd R4 2600 tgd R5 2800 CR T CR R 1020 0 *4 0 0 — 0.00 0.75 — 0.00 0.35 — 0.00 0.125 — 0.09 0.125 — 0.12 0.75 TRANS Æ RECV 75 85 — RECV Æ TRANS 70 77 — ms ms dB Psophometric filter is used Upper is specified for the MSM7508B, lower for the MSM7509B MSM7508B: All "0" code to PCMIN, MSM7509B: "11010101" to PCMIN Minimum value of the group delay distortion 10/17 ¡ Semiconductor MSM7508B/7509B AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Digital Output Delay Time Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz Symbol S IMD 300 to 0 3400 fa = 470 4.6 kHz to 100 kHz Min. Typ. Max. Unit 30 32 — dB — –37.5 –35 dBmO –4 2fa – fb — –52 –35 dBmO 50 mVPP *5 — 30 — dB tSD 50 — 200 tXD1 50 — 200 50 — 200 50 — 200 fb = 320 PSR T 0 kHz to PSR R 50 kHz tXD2 CL = 100 pF + 1 LSTTL tXD3 ns *5 The measurement under idle channel noise 11/17 , , ¡ Semiconductor MSM7508B/7509B TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLOCK 1 2 tXS XSYNC 4 5 6 7 8 9 10 11 9 10 11 tSX tWS tXD1 PCMOUT 3 tSD MSD D2 tXD2 D3 D4 D5 D6 tXD3 D8 D7 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. Receive Timing BCLOCK 1 tRS RSYNC 2 3 4 6 7 8 tSR tWS tDS PCMIN 5 MSD D2 tDH D3 D4 D5 D6 D7 D8 12/17 ¡ Semiconductor MSM7508B/7509B APPLICATION CIRCUIT MSM7508B/7509B Analog input AIN– PCMOUT 1 kW +5 V Digital interface PCM signal output GSX Analog output AOUT PCMIN AIN+ BCLOCK PCM data input PCM shift clock input SG 0.1 mF XSYNC 8 kHz SYNC signal input SGC AG DG 0V – 10 mF + +5 V 0 to 20W 1 mF VDD RSYNC PDN Power Down control input "1" = Operation "0" = Power down The analog output signal has an amplitude of ±1.2 V above and below the offset voltage level of VDD/2. 13/17 ¡ Semiconductor MSM7508B/7509B RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 14/17 ¡ Semiconductor MSM7508B/7509B PACKAGE DIMENSIONS (Unit : mm) DIP16-P-300-2.54-W1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.00 TYP. 15/17 ¡ Semiconductor MSM7508B/7509B (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM7508B/7509B (Unit : mm) QFJ28-P-S450-1.27 Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 1.00 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17