PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT16841T PI74FCT162841T 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS 20-Bit Transparent Latch 2 Product Features: Common Features: • PI74FCT16841T and PI74FCT162841T are high-speed, low power devices with high current drive • VCC = 5V ±10% • Hysteresis on all inputs • Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) PI74FCT16841T Features: • High output drive: IOH = –32 mA; IOL = 64 mA • Power off disable outputs permit “live insertion” • Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C PI74FCT162841T Features: • Balanced output drivers: ±24 mA • Reduced system switching noise • Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C Product Description: Pericom Semiconductor’s PI74FCT series of logic circuits are produced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16841T and PI74FCT162841T are 20-bit wide transparent latches designed to provide temporary storage of data and can be used as I/O ports, memory address latches, and bus drivers. The Output Enable and Latch Enable controls allow the devices to be operated as two 10-bit latches or one 20-bit latch. Signal pins are arranged in a flow-through organization for ease of layout and hysteresis is designed into all inputs to improve noise margin. The output buffers on the PI74FCT16841T and PI74FCT162841T are especially designed for driving high-capacitance loads and low impedance backplanes and include a Power-Off Disable function allowing “live insertion” of boards when the devices are used as backplane drivers. The PI74FCT162841T has ±24 mA balanced output drivers. It is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. This eliminates the need for external terminating resistors for most interface applications. 3 4 5 6 7 8 9 Logic Block Diagram 1OE 2OE 1LE 2LE 1D1 1 D C 2D1 1Q1 10 11 D C 2Q1 12 13 To 9 other channels To 9 other channels 14 15 1 PS2078A 01/15/95 PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Configuration 1OE Product Pin Description 1 Q2 1 2 3 56 55 54 GND 1 Q3 4 5 53 52 VCC 1 Q5 1 Q6 1 Q7 6 7 8 9 10 51 50 49 48 47 GND 1 Q8 1 Q9 1Q10 2 Q1 11 12 13 14 15 2 Q2 16 17 18 19 20 46 45 44 56-PIN V56 43 A56 42 41 40 39 38 37 21 22 23 24 25 36 35 34 33 32 2D6 26 27 28 31 30 29 2D9 1 Q1 1 Q4 2 Q3 GND 2 Q4 2 Q5 2 Q6 VCC 2 Q7 2 Q8 GND 2 Q9 2Q10 2OE Pin Name xDx xLE xOE xQx 1LE 1D1 1D2 GND 1D3 Description Data Inputs Latch Enable Input (Active LOW) Output Enable Input (Active LOW) 3-State Outputs 1D4 VCC 1D5 1D6 1D7 GND Truth Table(1) 1D8 Inputs 1D9 1D10 2D1 2D2 2D3 GND 2D4 2D5 1. VCC 2D7 2D8 GND 2. Outputs xDx xLE xOE xQx H L X X H H L X L L L H H L Q(2) Z H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance Output level before xLE HIGH-to-LOW Transition. 2D10 2LE 2 PS2078A 01/15/95 PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................................... –65°C to +150°C Ambient Temperature with Power Applied .................................... –40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ........... –0.5V to +7.0V DC Input Voltage ............................................................................ –0.5V to +7.0V DC Output Current ..................................................................................... 120 mA Power Dissipation ..........................................................................................1.0W 1 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%) Test Conditions(1) Parameters Description VIH VIL IIH IIL IOZH IOZL VIK IOS IO VH Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current High Impedance Output Current Clamp Diode Voltage Short Circuit Current Output Drive Current Input Hysteresis Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VCC = Max. VCC = Min., IIN = –18 mA VCC = Max.(3), VOUT = GND VCC = Max.(3), VOUT = 2.5V Min. Typ(2) Max. Units 0.8 1 –1 1 –1 –1.2 –200 –180 V V µA µA µA µA V mA mA mV 2.0 VIN = VCC VIN = GND VOUT = 2.7V VOUT = 0.5V –0.7 –140 –80 –50 100 2 3 4 5 6 7 PI74FCT16841T Output Drive Characteristics (Over the Operating Range) Test Conditions(1) Parameters Description VOH Output HIGH Voltage VOL IOFF Output LOW Voltage Power Down Disable VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL VCC = 0V, VIN or VOUT ≤ 4.5V IOH = –3.0 mA IOH = –15.0 mA IOH = –32.0 mA IOL = 64 mA 8 Min. Typ(2) 2.5 2.4 2.0 — 3.5 3.5 3.0 0.2 — 0.55 ±100 V µA Min. Typ(2) Max. Units 11 2.4 3.3 0.3 115 –115 0.55 150 –150 V V mA mA 12 Max. Units V 9 10 PI74FCT162841T Output Drive Characteristics (Over the Operating Range) Test Conditions(1) Parameters Description VOH VOL IODL IODH Output HIGH Voltage Output LOW Voltage Output LOW Current Output HIGH Current VCC = Min., VIN = VIH or VIL IOH = –24.0 mA VCC = Min., VIN = VIH or VIL IOL = 24 mA VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) 60 –60 13 Capacitance (TA = 25°C, f = 1 MHz) Parameters(4) CIN COUT Description Test Conditions Typ Max. Units Input Capacitance Output Capacitance VIN = 0V VOUT = 0V 4.5 5.5 6 8 pF pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. 3 PS2078A 01/15/95 14 15 PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Test Conditions(1) Parameters Description Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 500 µA ∆ICC Supply Current per Input @ TTL HIGH VCC = Max. VIN = 3.4V(3) 0.5 2.5 mA ICCD Supply Current per Input per MHz(4) VCC = Max., Outputs Open OE = GND; LE = Vcc One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND 0.15 0.25 mA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND; LE = Vcc fI = 5 MHZ One Bit Toggling VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND; LE = Vcc Eight Bits Toggling fI = 2.5 MHZ 50% Duty Cycle VIN = VCC VIN = GND 1.7 4.0(5) mA VIN = 3.4V VIN = GND 2.0 5.0(5) VIN = VCC VIN = GND 3.2 6.5(5) VIN = 3.4V VIN = GND 5.2 14.5(5) Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + FINI) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 4 PS2078A 01/15/95 PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 PI74FCT16841 Switching Characteristics over Operating Range Parameters t PLH t PHL tPLH tPHL tPZH tPZL t PHZ t PLZ tSU tH tW tSK(O) (1) 16841AT 16841BT 16841CT 16841DT 16841ET Com. Com. Com. Com. Com. 2 Description Conditions Min Max Min Max Min Max Min Max Min Max Unit Propagation Delay XDX to XQX (LE = HIGH) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(4) RL = 500Ω CL = 5 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω 1.5 9.0 1.5 6.5 1.5 5.5 1.5 4.2 1.5 3.4 ns 1.5 13.0 1.5 13.0 1.5 13.0 1.5 13.0 1.5 7.5 ns 1.5 12.0 1.5 8.0 1.5 6.4 1.5 4.0 1.5 3.7 ns 1.5 16.0 1.5 15.5 1.5 15.0 1.5 8.0 1.5 7.5 ns 1.5 11.5 1.5 8.0 1.5 6.5 1.5 4.8 1.5 4.4 ns 1.5 23.0 1.5 14.0 1.5 12.0 1.5 9.0 1.5 9.0 ns 1.5 7.0 1.5 6.0 1.5 5.7 1.5 4.0 1.5 4.0 ns 1.5 8.0 1.5 7.0 1.5 6.0 1.5 5.4 1.5 4.0 ns 2.5 — 2.5 — 2.5 — 1.0 — 1.0 — ns 2.5 — 2.5 — 2.5 — 1.0 — 1.0 — ns 7 4.0 — — 0.5 4.0 — — 0.5 4.0 — — 0.5 4.0 — — 0.5 3.0 — — 0.5 ns ns 8 Propagation Delay XLE to XQX Output Enable Time XOE to XQX Output Disable Time(3) XOE to XQX Setup Time HIGH or LOW, XDX to XLE Hold Time HIGH or LOW, XDX to XLE xLE Pulse Width HIGH(3) Output Skew(4) Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 3 4 5 6 9 10 11 12 13 14 15 5 PS2078A 01/15/95 PI74FCT16841T/162841T 20-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT16841 Switching Characteristics over Operating Range Parameters t PLH t PHL tPLH tPHL tPZH tPZL t PHZ t PLZ tSU tH tW tSK(O) (1) 162841AT 162841BT 162841CT 162841DT 162841ET Com. Com. Com. Com. Com. Description Conditions Min Max Min Max Min Max Min Max Min Max Unit Propagation Delay XDX to XQX (LE = HIGH) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(4) RL = 500Ω CL = 5 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω 1.5 9.0 1.5 6.5 1.5 5.5 1.5 4.2 1.5 3.4 ns 1.5 13.0 1.5 13.0 1.5 13.0 1.5 13.0 1.5 7.5 ns 1.5 12.0 1.5 8.0 1.5 6.4 1.5 4.0 1.5 3.7 ns 1.5 16.0 1.5 15.5 1.5 15.0 1.5 8.0 1.5 7.5 ns 1.5 11.5 1.5 8.0 1.5 6.5 1.5 4.8 1.5 4.4 ns 1.5 23.0 1.5 14.0 1.5 12.0 1.5 9.0 1.5 9.0 ns 1.5 7.0 1.5 6.0 1.5 5.7 1.5 4.0 1.5 4.0 ns 1.5 8.0 1.5 7.0 1.5 6.0 1.5 5.4 1.5 4.0 ns 2.5 — 2.5 — 2.5 — 1.0 — 1.0 — ns 2.5 — 2.5 — 2.5 — 1.0 — 1.0 — ns 4.0 — — 0.5 4.0 — — 0.5 4.0 — — 0.5 4.0 — — 0.5 3.0 — — 0.5 ns ns Propagation Delay XLE to XQX Output Enable Time XOE to XQX Output Disable Time(3) XOE to XQX Setup Time HIGH or LOW, XDX to XLE Hold Time HIGH or LOW, XDX to XLE xLE Pulse Width HIGH(3) Output Skew(4) Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 6 PS2078A 01/15/95