ETC PI74FCT162373TV

PI74FCT16373/162373/162H373T
PI74FCT16373T
16-BIT
TRANSPARENT LATCHES
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PI74FCT162373T
PI74FCT162H373T
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Fast CMOS 16-Bit
Transparent Latches
Product Features
Product Description
Common Features:
• PI74FCT16373T, PI74FCT162373T, and
PI74FCT162H373T are high-speed,
low power devices with high current drive.
• Vcc = 5V ±10%
• Hysteresis on all inputs
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
PI74FCT16373T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162373T Features:
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H373T Features:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
Pericom Semiconductor’s PI74FCT series of logic circuits are produced using the Company’s advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
The PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
The PI74FCT16373T output buffers are designed with a Power-Off
disable allowing “live insertion” of boards when used as backplane
drivers.
The PI74FCT162373T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H373T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1OE
2OE
1LE
2LE
1D0
2D0
D
D
1O0
2O0
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
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PS2033A 03/11/96
PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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Product Pin Description
Pin Name
xOE
xLE
xDx
xOx
GND
VCC
Note:
Truth Table
Inputs(1)
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs (Active HIGH)
Inputs(1)
3-State Outputs
Ground
Power
XDX
XOE
H
L
X
L
L
H
xLE
H
H
X
Outputs(1)
xOx
H
L
Z
Note 1
H = High Voltage Level
X = Don’t Care
L = Low Voltage Level
Z = High Impedance
1. For the PI74FCT162H373T, these pins have “Bus
Hold.” All other pins are standard, outputs, or I/Os.
Product Pin Configuration
1OE
1
48
1LE
1O0
2
47
1D0
1O1
3
46
1D1
GND
4
45
GND
1O2
5
44
1D2
1O3
6
43
1D3
VCC
7
42
VCC
1O4
8
41
1D4
1O5
9
40
1D5
GND
10
39
GND
1O6
11
38
1D6
1O7
12
37
1D7
2O0
13
36
2D0
2O1
14
35
2D1
GND
15
34
GND
2O2
16
33
2D2
2O3
17
32
2D3
VCC
18
31
VCC
2O4
19
30
2D4
2O5
20
29
2D5
GND
21
28
GND
2O6
22
27
2D6
2O7
23
26
2D7
2OE
24
25
2LE
48-Pin
A,V
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PS2033A 03/11/96
PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ......................................................... –65°C to +150°C
Ambient Temperature with Power Applied ......................... –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .. –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) –0.5V to +7.0V
DC Input Voltage ................................................................. –0.5V to +7.0V
DC Output Current ........................................................................... 120 mA
Power Dissipation ................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description
VIH
VIL
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IBHH
IBHL
IOZH(5)
IOZL(5)
VIK
IOS
IO
VH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input LOW Current
Input LOW Current
Input LOW Current
Input LOW Current
Bus Hold
Sustain Current
High Impedance
Output Current
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input , VCC = Max.
Standard I/O, VCC = Max.
Bus Hold Input(4), VCC = Max.
Bus Hold I/O(4), VCC = Max.
Standard Input , VCC = Min.
Standard I/O, VCC = Min.
Bus Hold Input(4), VCC = Min.
Bus Hold I/O(4), VCC = Min.
Bus Hold Input(4), VCC = Min.
VCC = Max.
VCC = Max.
VCC = Min., IIN = –18 mA
VCC = Max.(3), VOUT = GND
VCC = Max.(3), VOUT = 2.5V
Min.
Typ(2)
2.0
VIN = VCC
VIN = VCC
VIN = VCC
VIN = VCC
VIN = GND
VIN = GND
VIN = GND
VIN = GND
VIN = 2.0V
VIN = 0.8V
VOUT = 2.7V
VOUT = 0.5V
–50
+50
–80
–50
–0.7
–140
100
Max.
Units
0.8
1
1
±100
±100
–1
–1
±100
±100
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
1
–1
–1.2
–200
–180
µA
µA
V
mA
mA
mV
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
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PS2033A 03/11/96
PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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PI74FCT16373T Output Drive Characteristics (Over the Operating Range)
Parameters Description
Test Conditions(1)
VOH
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL
VOL
IOFF
Output LOW Voltage
Power Down Disable
VCC = Min., VIN = VIH or VIL
VCC = 0V, VIN or VOUT ≤ 4.5V
IOH = –3.0 mA
IOH = –15.0 mA
IOH = –32.0 mA
IOL = 64 mA
Min.
Typ(2)
2.5
2.4
2.0
3.5
3.5
3.0
0.2
—
0.55
±100
V
µA
Min.
Typ(2)
Max.
Units
2.4
3.3
0.3
115
–115
0.55
150
–150
V
V
mA
mA
—
Max.
Units
V
PI74FCT162373T/162H373T Output Drive Characteristics (Over the Operating Range)
Parameters Description
VOH
VOL
IODL
IODH
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
Test Conditions(1)
VCC = Min., VIN = VIH or VIL
IOH = –24.0 mA
VCC = Min., VIN = VIH or VIL
IOL = 24 mA
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
60
–60
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
CIN
COUT
Description
Test Conditions
Typ
Max.
Units
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
4.5
5.5
6
8
pF
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
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PS2033A 03/11/96
PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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Power Supply Characteristics
Parameters Description
Test Conditions(1)
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
0.1
500
µA
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = Max.
VIN = 3.4V(3)
0.5
1.5
mA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max.,
Outputs Open
XOE = GND, XLE = VCC
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
60
100
µA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fI = 10 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
One Bit Toggling
VIN = VCC
VIN = GND
0.6
1.5(5)
mA
VIN = 3.4V
VIN = GND
0.9
2.3(5)
VCC = Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
16 Bits Toggling
VIN = VCC
VIN = GND
2.4
4.5(5)
VIN = 3.4V
VIN = GND
6.4
16.5(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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PI74FCT16373T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
tSK(o)
16373T
16373AT
16373CT
16373DT
Com.
Com.
Com.
Com.
16373ET
Com.
Description
Conditions(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
xOE to xOx
Output Disable Time(3)
xOE to xOx
Setup Time HIGH
or LOW, XDX to XLE
Hold Time HIGH
or LOW, XDX to XLE
xLE Pulse Width
HIGH(3)
Output Skew(4)
CL = 50pF
RL = 500Ω
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
2.0
—
2.0
—
2.0
—
1.5
—
1.0
—
ns
1.5
—
1.5
—
1.5
—
1.0
—
1.0
—
ns
6.0
—
5.0
—
5.0
—
3.0
—
3.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
PI74FCT162373T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
tSK(o)
162373T
162373AT
162373CT
162373DT
162373ET
Com.
Com.
Com.
Com.
Com.
Description
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
xOE to xOx
Output Disable Time(3)
xOE to xOx
Setup Time HIGH
or LOW, XDX to XLE
Hold Time HIGH
or LOW, XDX to XLE
xLE Pulse Width
HIGH(3)
Output Skew(4)
CL = 50pF
RL = 500Ω
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
2.0
—
2.0
—
2.0
—
1.5
—
1.0
—
ns
1.5
—
1.5
—
1.5
—
1.0
—
1.0
—
ns
6.0
—
5.0
—
5.0
—
3.0
—
3.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
(1)
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction.
This parameter is guaranteed by design.
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PS2033A 03/11/96
PI74FCT16373/162373/162H373T
16-BIT
TRANSPARENT LATCHES
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PI74FCT162H373T Switching Characteristics over Operating Range
162H373T
162H373AT 162H373CT 162H373DT 162H373ET
Com.
Parameters
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
tSK(o)
Com.
Com.
Com.
Com.
Description
Conditions(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
xOE to xOx
Output Disable Time(3)
xOE to xOx
Setup Time HIGH
or LOW, XDX to XLE
Hold Time HIGH
or LOW, XDX to XLE
xLE Pulse Width
HIGH(3)
Output Skew(4)
CL = 50 pF
RL = 500Ω
1.5
8.0
1.5
5.2
1.5
4.2
1.5
3.8
1.5
3.4
ns
2.0
13.0
2.0
8.5
2.0
5.5
1.5
4.0
1.5
3.7
ns
1.5
12.0
1.5
6.5
1.5
5.5
1.5
4.8
1.5
4.4
ns
1.5
7.5
1.5
5.5
1.5
5.0
1.5
4.0
1.5
4.0
ns
2.0
—
2.0
—
2.0
—
1.5
—
1.0
—
ns
1.5
—
1.5
—
1.5
—
1.0
—
1.0
—
ns
6.0
—
5.0
—
5.0
—
3.0
—
3.0
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction.
This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS2033A 03/11/96