PS4066/PS4066A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Low-Cost, Quad, SPST, CMOS Analog Switches Features Description • • • • • • • • • • Low On-Resistance On-Resistance Matching Between Channels, 0.2Ω typ On-Resistance Flatness, <2Ω typ Low Off-Channel Leakage, <100pA @ +25oC TTL/CMOS Logic Compatible GND-to-V+ Analog Signal Dynamic Range Low Power Consumption (<12µW) Low Crosstalk: -86dB @ 1MHz Low Off-Isolation: -58dB @ 1 MHz Wide Bandwidth: > 100 MHz • Small QSOP-16 Package Saves Board Area The PS4066/PS4066A are improved SPST CMOS analog switches ideal for low-distortion audio switching. These high precision, medium voltage switches were designed to operate with single-supplies from +3V to 16V. They are fully specified with +12V, +5V, and +3V supplies. The PS4066/PS4066A has four normally open (NO) switches. Each switch conducts current equally well in either direction when on. In the off state each switch blocks voltages up to the power-supply rails. With +12V power supply, the PS4066/PS4066A guarantee <45Ω on-resistance. On-resistance matching between channels is within 2Ω (PS4066). On-resistance flatness is less than 4Ω (PS4066A) over the specified range. The PS4066A guarantees low leakage currents (<100pA @ 25oC, <6nA @ +85oC) and fast switching speeds (tON < 175ns). ESD sensitivity rating is >2,000V per MIL-STD 883, Method 3015.7 Applications • • • • • • Both devices are available in PDIP-14, narrow-body SOIC-14, and QSOP-16 packages. Available temperature ranges are: commercial (0oC to 70oC), and industrial (-40oC to +85oC). Instrumentation, ATE Sample-and-Holds Audio Switching and Routing Telecommunication Systems PBX, PABX Battery-Powered Systems For operation below 5V, the PI5A101/PI5A391/PI5A392 are also recommended. Functional Diagrams, Pin Configurations, and Truth Table Top View PDIP/SO Logic Switch 0 1 O FF ON N.C. = No Internal Connection Switches shown for logic “0” input 1 Top View QSOP PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings Thermal Information Voltages Referenced to GND V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V VIN, VCOM, VNC, VNO (Note 1) . . . . . . . . -2V to (V+) +2V or 30mA, whichever occurs first Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, COM, NO, NC (pulsed at 1ms, 10% duty cycle) . . . . . . . . . . . . . . . . 100mA ESD per Method 3015.7 . . . . . . . . . . . . . . . . . . . . . . >2000V Continuous Power Dissipation (TA= +70ºC) Plastic DIP (derate 10.5mW/ ºC above +70ºC) . . . . . . 800mW SO and QSOP (derate 8.7mW/ ºC above +70ºC) . . . . . 650mW Storage Temperature . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . +300ºC Note Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to 30mA. Caution: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Electrical Specifications - Single +12V Supply (V+ = 12V ±10%, GND = 0V, VINH = 4V, VINL = 0.8V) Parame te r Symbol Te mp. (°C) M in(1) Typ(2) M ax(1) Units Conditions Analog Switch Analog Signal Range(3) On Resistance VANALOG RON On- Resistance Match Between Channels(4) ∆RON On- Resistance Flatness(5) RFLAT(ON) NO or NC Off Leakage Current(6) COM Off Leakage Current(6) COM On Leakage Current(6) Full V+ = 12V, ICOM = 2mA, VNO = 10V PS4066 PS4066A V+ = 12V, ICOM = 2mA VNO = 10V 0 25 V+ 12 Full INO(OFF) 0.5 0.5 25 OR INC(OFF) ICOM(OFF) ICOM(ON) 2 Full PS4066 PS4066A PS4066 PS4066A V+ = 12V, VCOM = 0V, VNO = 10V PS4066 PS4066A V+ = 12V, VCOM = 10V, VNO = 10V 2 4 2 Ω 6 25 V+ = 12V, VCOM = 0V, VNO = 10V 45 55 Full V+ = 12V, ICOM = 2mA, VNO = 10V, 5V, 1V V 4 6 25 -1 - 0.1 1 0.1 Full -6 6 25 -1 - 0.1 1 0.1 Full -6 6 25 -2 - 0.2 2 0.2 Full - 12 12 PS8184A nA 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Specifications - Single +12V Supply (continued) (V+ = 12V ±10%, GND = 0V, VINH = 4V, VINL = 0.8V) Parame te r Symbol Conditions Te mp (°C) Input Current with Input Voltage High IINH IN =5V, all others = 0.8V Input Current with Input Voltage Low IINL M in(1) Typ(2) M ax(1) Units Logic Input - 0.5 0.005 0.5 - 0.5 0.005 0.5 45 100 Full IN = 0.8V, all others =5V µA D ynamic Turn- O n Time tON 25 VCOM = 10V, Figure 2 Full 150 25 17 Turn- O ff Time tOFF O n- Channel Bandwidth BW Signal = 0dbm Figure 4, 50Ω in and out 100 Q CL=1nF, VGEN = 0V, RGEN = 0Ω, Figure 3 2 O ff Isolation O IRR RL = 50Ω, CL= 5pF, f = 1 MHz, Figure 4 - 58 Crosstalk(8) XTALK RL = 50Ω, CL= 5pF, f = 1 MHz, Figure 5 NO Capacitance C(OFF) f =1 MHz, Figure 6 9 f =1 MHz, Figure 6 9 CCOM(ON) f =1MHz, Figure 7 22 Positive Supply Current I+ VIN = 0V or V+, all channels on or off Total Harmonic Distortion THD Charge Injection(3) CO M O ff Capacitance CO M O n Capacitance Full 75 ns 100 25 MHz 10 pC dB - 86 pF Supply -1 0.001 1 µA Full 0.03 % Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. ∆RΟΝ = ∆RΟΝ max - ∆RΟΝ min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25ºC. 7. Off Isolation = 20log10 [ VCOM / (VNO or VNO) ], VCOM = 0utput, VNC /VNO = input to off switch 8. Between any two switches. 3 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Specifications - Single +5V Supply (V+ = +5V ±10%, GND = 0V, VINH = 2.4V, VINL = 0.8V) Parame te r Symbol Conditions Te mp (°C) M in(1) Full 0 Typ(2) M ax(1) Units V+ V Analog Switch Analog Signal Range(3) VANALOG RON V+ = 4.5V, ICOM = - 1mA, VNO = 3.5V O n- Resistance MatchBetween Channels(4) ∆RON V+ =5V, ICOM = - 1mA, VNO = 3V O n- Resistance Flatness(3,5) RFLAT(ON) V+ = 5V, ICOM = - 1mA, VNO = 1V, 3V NO O ff Leakage Current(9) INO(OFF) On- Resistance CO M O ff Leakage Curren(9) CO M O n Leakage Current(6) ICOM(OFF) ICOM(ON) V+ = 5.5V, VCOM = 0V, VNO = 4.5V V+ = 5.5V, VCOM = 0V, VNO = 4.5V V+ = 5.5V, VCOM = 5V VNO = 4.5V PS4066 PS4066A PS4066 PS4066A PS4066 PS4066A 25 22 Full 75 100 25 0.3 Full 4 12 25 4 Full Ω 6 8 25 -1 - 0.1 1 0.1 Full -6 6 25 -1 - 0.1 1 0.1 Full -6 6 25 -2 - 0.2 2 0.2 Full - 12 12 nA D ynamic Turn- O n Time 25 tON VNO= 3V 65 Full 175 25 30 Turn- O ff Time tOFF On- Channel Bandwidth BW Signal = 0dBm, 50Ω in and out Figure 4 25 100 Q CL = 1nF, VGEN = 0V, RGEN = 0V, Figure 3 25 1 I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off Full Charge Injection(3) 125 Full 75 ns 125 MHz 10 pC 1 µA Supply Positive Supply Current 4 -1 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Specifications - Single +3V Supply (V+ = +2.7V to 3.3V, GND = 0V, VINH = 2.4V, VINL = 0.8V) Parame te r Symbol Conditions Te mp°C M in.(1) Typ(2) M ax.(1) Units V+ V Analog Switch Analog Signal Range(3) VANALOG Channel O n- Resistance RON V+ = 3V, ICOM = - 1mA, VNO = 1.5V tON V+ =3V, VNO = 1.5V 0 25 170 Full 225 Ω D ynamic Turn- O n- Time(3) Turn- O ff- Time(3) Charge Injection(3) 25 80 Full 230 25 t(OFF) V+ =3V, VNO = 1.5V Q CL = 1nF, VGEN = 0V, RGEN = 0V 25 I+ V+ = 3.3V, VIN = 0V or V+, all channels on or off Full 185 40 Full 150 ns 200 2 10 pC 0.001 1 µA Supply Positive Supply Current -1 Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. ∆RΟΝ = ∆RΟΝ max - ∆RΟΝ min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25ºC. 7. Off Isolation = 20log10 [ VCOM / (VNO or VNO) ], VCOM = 0utput, VNC /VNO = input to off switch 8. Between any two switches. 5 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Typical Operating Characteristics (TA = +25°C, unless otherwise noted) RON vs. VCOM & Supply Voltages RON vs. VCOM & Temperature Charge Injection vs. Analog Voltage Leakage Currents vs. VCOM 6 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Typical Operating Characteristics (TA = +25°C, unless otherwise noted) Input Switching Threshold vs. Supply Voltage VIN (V) Leakage Current Leakage Current vs. Temperature V + (V) Supply Current vs. VIN Switching Current vs. Switching Frequency I+ (mA) TON,TOFF(ns) Temperature (°C) V + (V) Switching Times vs. Temperature Supply Currents vs. Switching Frequency I + (mA) Starting Times (ns) VIN (V) Frequency (MHz) Temperature (°C) 7 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Applications Information Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence V+ on first, and then the logic inputs. If power-supply sequencing is not possible, add a small signal diode or current limiting resistor in series with the supply pin for overvoltage protection (Figure 1). Adding a diode reduces the analog signal range, but low switch resistance and low leakage characteristics are unaffected. Figure 1. Overvoltage protection is accomplished using an external blocking diode or a current limiting resistor . Test Circuits/Timing Diagrams Figure 2. Switching Times Figure 3. Charge Injection 8 PS8184A 10/15/98 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuits/Timing Diagrams (continued) Figure 5. Crosstalk Figure 4. Off Isolation, BW 10nF +12V V+ COM IN Capacitance Meter 0V NO f = 1kHz GND Figure 6. Channel-Off Capacitance Figure 7. Channel-On Capacitance Ordering Information Part Numbe r Te mpe rature - Range Package PS4066CPD 0ºC to + 70ºC 14 Plastic DIP PS4066CSD 0ºC to + 70ºC 14 Narrow SO PS4066CEE 0ºC to + 70ºC 16 Q SO P PS4066EPD - 40ºC to + 85ºC 14 Plastic DIP PS4066ESD - 40ºC to + 85ºC 14 Narrow SO PS4066ACPD 0ºC to + 70ºC 14 Plastic DIP PS4066ACSD 0ºC to + 70ºC 14 Narrow SO PS4066ACEE 0ºC to + 70ºC 16 Q SO P PS4066AEPD - 40ºC to + 85ºC 14 Plastic DIP PS4066AESD - 40ºC to + 85ºC 14 Narrow SO PS4066AEEE - 40ºC to + 85ºC 16 Q SOP Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 9 PS8184A 10/15/98