PAS202BCA PAS202BBA PAS202BCA SINGLE-CHIP CMOS VGA COLOR DIGITAL IMAGE SENSOR PAS202BBA SINGLE-CHIP CMOS VGA B&W DIGITAL IMAGE SENSOR General Description The PAS202BCA/PAS202BBA is a highly integrated CMOS active-pixel image sensor that has a VGA resolution of 644H x 484V. To have an excellent image quality, the PAS202BCA/PAS202BBA outputs 10-bit RGB raw data through a parallel data bus. It is available in color or monochrome and in 323-pin LCC. The PAS202BCA/PAS202BBA can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control. Features § VGA(644 x 484 pixels) resolution, ~1/4” Lens Key Specification Supply Voltage 3.3V + 10% § Bayer-RGB color filter array § On-chip 10-bit pipelined A/D converter Resolution § Output format: 10-bit parallel RGB raw data Array diagonal 644(H) x 484(V) 4.5mm (~1/4”Optic) § On-chip 9-bit background compensation DAC § On-chip programmable gain amplifier q 4-bit color gain amplifier(x3) q 5-bit global gain amplifier (x5) § Continuous variable frame time(1/2sec~1/30sec) § Continuous variable exposure time § I2C Interface Pixel Size Frame rate System clock Max. pixel rate 5.6µmX5.6µm ~30 fps Up to 48 MHz 12MHz Sensitivity 0.6V/Lux-sec(green) § Single 3.3V supply voltage PGA gain 29.5 dB max. § 100 mW low power dissipation Color filter § Digitally programmable registers RGB Bayer Pattern § 350 uW low power down dissipation ~ Frame time to 4 pxclk § Flash light timing Exposure Time § Mirror output Scan Mode Progressive S/N Ratio >42 dB Package 32 pins LCC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 1 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 1. Pin Assignment Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name Type Defintion VSSAY VLRST PXD9 PXD8 PXD7 PXD6 PXD5 VDDQ VSSQ VSSQ PXD4 PXD3 NC PXD2 PXD1 PXD0 SYSCLK PXCLK HSYNC VSYNC SCL SDA VDDD VSSD CSB VCM VRT VRB NC VSSA VDDA VDDAY GND BIAS Analog ground Fixed bias input voltage, 1.65V OUT OUT OUT OUT OUT PWR GND GND OUT OUT Digital data out Digital data out Digital data out Digital data out Digital data out Digital VDD, 3,3V Digital ground Digital ground Digital data out Digital data out Not connected Digital data out Digital data out Digital data out Master clock input Pixel clock output Horizontal synchronization signal Vertical synchronization signal I2C clock I2C data Digital VDD, 3.3V Digital ground Chip select (Low, active, chip disable if high) Analog voltage reference Analog voltage reference Analog voltage reference Not connected Analog ground Analog VDD, 3.3V Analog VDD, 3.3V OUT OUT OUT IN OUT OUT OUT IN I/O PWR GND IN BYPASS BYPASS BYPASS GND PWR PWR All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 2 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 2. Block Diagram Row Decoders dac[8:0] 9-bit +/-1V DAC Sensor Array CDS ckts Col. Decoders Color gain B,G,R 4-bits Global gain 5-bits X3 X5 cmd Timing & Digital Control 10-bit pipelined ADC Hsync PXCLK Register sets Pxo<9:0> Vsync SDA SCL SysClk I2C Interface Fig 2.1 – Block diagram of the PAS202BCA/PAS202BBA All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 3 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 3. Output Format 3.1. Pixel Array And Pixel Color Pattern The output image format of PAS202BCA/PAS202BBA is VGA (640x480 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. 13 dark pixel 540 dark pixel Row 485 Row 484 Dark pixel G R G B G G 13 dark pixel 13 dark pixel 13 R pixel 13 G pixel 13 B pixel R G B R 13 No filter pixel G B G R G 13 dark pixel R G B G R G R B G R G R Pixel array: 644(H) x 486(V) row lines B G Row 1 Row 0 B G G R G B G B R G B G G B G R Dark pixel 13 R pixel 540 dark pixel G B 13 G pixel 13 B pixel 13 dark pixel 644 13 dark pixel B G R G R B G 13 No filter pixel 13 dark pixel 13 dark pixel column lines Fig 3.1. Pixel array and pixel color pattern Note: 1. Pixel color pattern does not apply to monochrome sensor. 2. Pixel read-out proceeds from left to right, and from bottom row to top row. 3. Pixel array not drawn to scale. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 4 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 3.2 Output timing: Pixel per line is programmable, 772 pixels ~ 1156 pixels. 4+4 blank pixel for each line. ( See Fig 3.2. Fig 3.3) 1+1 Dark line for each frame.(See Fig 3.4. Fig 3.5 ) Dark line output format: Fig 3.6. line time (min)= 120+4+2+640+2+4 = 772 pixclks Hsync. xxx 120 pixclks xxxx Pixclk_a 2+640+2 pixels out x BGBG xxx xxxx 2+640+2 pixels out Note: "x" indicates don't care PXD[9:0] Fig 3.2. Inter-line timing (default) line time =4+644+4 pixclks Nov_by2*2-8 pixclks Hsync. Note: "x" indicates don't care PXD[9:0] x x x x x x x B Pixclk_a 2+640+2 pixels out G B G x x x x x x x x Nov_by2*2 pixclks 2+640+2 pixels out Fig 3.3. Inter-line timing (programmable) Frame time(min) (=486 lines) Vsync. 120 Pixclks Hsync. Dark 120 Pixclks Dark B,G,B,G... G,R,G,R... Dark Dark Valid frame data (484 lines) Fig 3.4. Inter-frame timing (default) All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 5 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC Frame time = lpf lines Vsync. Pixclks Dark Hsync. Dark Valid frame data (484 lines) Dark Dark Valid frame data (484 lines) Valid frame data (484 lines) Fig 3.5. Inter-frame timing (programmable) Row 0 Dark pixel 540 R G B 13 R pixel 13 G pixel 13 B pixel Dark pixel 13 No pixel filter 13dark 13dark 13 dark pixel pixel pixel 13 dark pixel 644 column lines Fig 3.6. Dark line output format All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 6 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 4. I2C Bus PAS202BCA/PAS202BBA supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz. 4.1 I2C bus overview § Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. § Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). § Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 4.1. § Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 4.2. § Both the master and slave can transmit and receive data from the bus. § Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. SDA SCL S P Start Condition Stop Condition Fig 4.1 Start and Stop Conditions All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 7 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC SDA DATA STABLE DATA CHANGE ALLOWED Fig 4.2 Valid Data SCL 4.2 Data Transfer Format 4.2.1 Master transmits data to slave (write cycle) § S : Start § A : Acknowledge by slave § P : Stop § RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle. § SUBADDRESS : The address values of PAS202BCA/PAS202BBA internal control registers (Please refer to PAS202BCA/PAS202BBA register description) 1ST BYTE S SLAVE ID (7 BIT) MSB 2ND BYTE RW A n BYTEs + A SUBADDRESS (8 BIT) A DATA A DATA A P LSB=0 During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCA/PAS202BBA) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS202BCA/PAS202BBA acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS202BCA/PAS202BBA control register (address was assigned by 2nd byte). After PAS202BCA/PAS202BBA issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS202BCA/PAS202BBA sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 8 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC registers value inside PAS202BCA/PAS202BBA can be programming via this way. (Please refer to Fig 4.3.) 4.2.2 Slave transmits data to master (read cycle) § The sub-address was taken from previous write cycle § The sub-address is automatically increment after each byte read § Am : Acknowledge by master § Note there is no acknowledgment from master after last byte read 1ST BYTE S 2ND BYTE SLAVE ADDRESS (7 BITS) RW A n BYTE DATA (8 BIT) Am DATA Am DATA 1 P NO ACK IN LAST BYTE During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS202BCA/PAS202BBA. The 8 bit data was read from PAS202BCA/PAS202BBA internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS202BCA/PAS202BBA place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS202BCA/PAS202BBA) must releases SDA line to master to generate STOP condition. (Please refer to Fig 4.3.) SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 P S Start Condition Address R/W ACK from Receiver Data ACK from Receiver Data ACK from Receiver Stop Condition Fig 4.3 Data Transfer Format All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 9 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 4.3 I2C Bus Timing SDA tf t HD;STA tf tLOW tr t BUF tr tSP tSU;DAT SCL S tHD;STA t HD;DAT tSU;STA tHIGH tSU;STO Sr P S Fig 4.4 I2C Bus Timing 4.4 I2C Bus Timing Specification STANDARD-MODE PARAMETER SCL clock frequency Hold tie (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I2C-bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) UNIT SYMBOL MIN. MAX. fscl tHD:STA 10 4.0 400 - kHz us tLOW tHIGH t SU;STA tHD;DAT t SU;DAT tr tf t SU;STO tBUF Cb VnL 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 0.1 VDD 3.45 N.D. N.D. 15 - us us us us ns ns(note1) ns(note1) us us pF V VnH 0.2 VDD - V Note 1: It depends on the "high" period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 10 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 5. Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Vdd DC supply voltage -0.5 3.8 V Vin DC input voltage 0.5 Vdd+0.5 V Vout DC output voltage -0.5 Vdd+0.5 V DC Electrical Characteristics (VDD=3.3V±10%, Ta=0°C~40°C ) Symbol Parameter Min. Typ. Max. 3.00 3.3 3.60 Unit Type :PWR VDD Analog and digital operating voltage IDD Operating Current Type :IN & I/O Reset and SYSCLK 30 V mA VIH Input voltage HIGH 2.0 VDD V VIL Input voltage LOW 0 0.8 V Cin Input capacitor 10 pF Ilkg Input leakage current 1.0 uA Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 20pf, 3.3volts VOH Output voltage HIGH VOL Output voltage LOW AC Operating Condition Symbol Vdd-0.2 Parameter fsysclk Master clock frequency fpxclk Pixel clock output frequency Min. V Typ. 8 0.2 V Max. Unit 48 MHz 12 MHz Sensor Characteristics Parameter Symbol Min. Typ. Max. Unit Photo response non-uniformity PRNU 1.7 % Saturation output voltage Vsat. 1.2 V Dark output voltage Vdark 53 mV/sec Dark signal non-uniformity DSNU 2.79 Lsb Sensitivity ( Red channel ) R 0.8 V/Lux-sec Sensitivity ( Green channel ) G 0.6 V/Lux-sec Sensitivity ( Blue channel ) B 0.6 V/Lux-sec Column non-uniformity Cnu 1.56 Note % All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 11 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC PXCLK Timing Specification @12M Hz Symbol tLOW tHIGH tr tf Cb Parameter Min. Typ. Max. Unit Low period of the PXCLK duty cycle 40% 50% 60% % High period of the PXCLK duty cycle 40% 50% 60% % Rise time signal Fall time signal 10 ns 10 ns Capacitive load for each bus line 15 pF PXCLK tf t LOW tr t HIGH 6. Package Inf ormation VRB 24 VRT 23 VCM VDDD 22 CSB SDA 21 VSSD SCL 6.1. Pin Connection Diagram 25 26 27 28 PXCLK 18 31 VDDA SYSCLK 17 32 VHRST PXD0 16 1 VSSAY PXD1 15 2 VLRST PXD2 14 3 PXD9 NC 13 4 PXD8 12 11 10 9 8 7 6 5 PXD7 VSSA PXD6 30 PXD5 19 VDDQ HSYNC VSSQ NC VSSQ 29 PXD4 20 PXD3 VSYNC -- Bottom View -- All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 12 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 6.2. Package Outline All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 13 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 6.3. Optical Center(Sensor Array Center)and Die/Package Center Offset All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 14 V1.2, May. 2002 PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC 7. Referencing Schematic PXD9 PXD8 PXD7 PXD6 PXD5 VDDD C2 5 PXD7 6 8 9 10 11 7 PXD5 VDDQ PXD6 VDDA VSSA 22 21 PAS202 NC 4 R1 3 300k 3.3V 2 1 L1 R2 300k 3.3UH 32 VDDD 31 30 29 C4 C3 0.1uF 0.1uF VDDA C13 C14 C15 C16 1uF 10uF 10uF 1uF 28 VSYNC VRB HSYNC VRT 20 VDDAY 27 VSYNC PXCLK VCM 19 PAS202BCA PAS202BBA SYSCLK 26 HSYNC VSSAY CSB 18 VLRST PXD0 25 17 PXCLK PXD8 PXD1 SCL SYSCLK VSSQ 16 VDDA PXD9 VSSD 15 PXD0 U1 PXD2 24 PXD1 NC PXD4 14 VDDD PXD2 SDA 13 23 PXD3 PXD3 PXD4 VSSQ 12 0.1uF SCL SDA C6 R3 VDDD 10uF R4 C11 4.7k 4.7k C10 C12 1uF 1uF 1uF C8 0.1uF S1 R5 L2 300k 3.3UH DGND AGND CSB NOTES on capacitors: 1.The 0.1uF caps for pin 8,23,31 and 32 MUST have trace lengths LESS than 5mm. 2.C10,C11,C6 for pins 26,27 and 28 MUST have trace lengths LESS than 5mm. Title pas202BXA-32P Size A Date: Document Number PAS202-32PINS-PP.opj BY Jeffery Tuesday, May 28, 2002 Sheet All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] Rev V1.0 1 of 15 V1.2, May. 2002 1