PAS6329 Specification PAS6329 CMOS VGA DIGITAL IMAGE SENSOR General Description The PAS6329 is a highly integrated CMOS active-pixel image sensor that has output of 640 x 480 pixels. It embedded the new FinePixel™ sensor technology to perform the excellent image quality. PAS6329 outputs 8-bit YUV/YCrCb 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in CSP-22L package. The PAS6329 can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register set, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control. Features Resolution: 640 x 480 pixels, 1/7” Lens Bayer-RGB color filter array Output format (parallel 8-bit): z YUV/YCrCb 4:2:2 z RGB565/555/444 I2CTM Interface Power dissipation: operating typical 25mA @ 2.8V (VGA YUV 30fps output, without loading), power-down typical 10uA @ 2.8V Automatic Background Compensation DSP function: z AEC & AGC z AWB z Gamma z Color matrix z Sharpness z De-noise z Color saturation z Defect compensation z Lens shading compensation z Decimation WOI & Sub-sampling Dummy line & pixel timing Output Hsync at Vsync Module size : 6.0mm * 6.0mm Key Specification Resolution 640 (H) x 480 (V) Pixel Size 3.15um * 3.15um Array diagonal 1/7” Lens Lens Chief Ray Angle 25 degree Color filter RGB Bayer Pattern Analog 2.8V typical I/O 2.8V typical Core 1.8V typical Power Max. input clock 52MHz Max. output clock 26MHz Max. Frame rate 30fps Scan Mode Exposure Time Progressive ~ Frame time to Line time Sensitivity 1500mV/Lux-Sec S/N Ratio 41dB Dynamic range 60dB Package CSP-22L All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 1 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 1. Pin Assignment Pin No. A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C4 C5 D1 D3 D4 D5 E1 E2 E3 E4 E5 Name SYSCLK PXCLK PXD1 PXD3 VSSD VDDD PXD0 PXD2 NC PXD4 DVDD28 PXD6 PXD5 AVDD28 SCL VSYNC PXD7 VREF VSSA CSB SDA HSYNC Type IN OUT OUT OUT GND PWR OUT OUT -OUT PWR OUT OUT PWR IN OUT OUT Ref GND IN I/O OUT Description External clock input Pixel clock output Digital pixel data [1] Digital pixel data [3] Digital ground Digital core power, 1.8V Digital pixel data [0], LSB Digital pixel data [2] -Digital pixel data [4] I/O power, 2.8V typical Digital pixel data [6] Digital pixel data [5] Analog power, 2.8V typical I2C clock input Vertical synchronization signal output Digital pixel data [7], MSB Voltage reference Analog ground Power down mode enable, active high I2C data Horizontal synchronization signal output All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 2 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 2. Specifications Absolute Maximum Ratings Operating Temperature Stable Image Temperature Ambient Storage Temperature Supply Voltage ( with respect to ground ) -30℃ ~ 85℃ 0℃ ~ 50℃ -40℃ ~ 125℃ 4.5V 3.0V 4.5V VDDA VDDD VDDIO All Input / Output Voltage ( with respect to ground ) Lead-free temperature, Surface-mount process ESD rating, Human Body model DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ ) Symbol Parameter Type : POWER VDDA DC supply voltage – Analog VDDD DC supply voltage – Digital core VDDIO DC supply voltage – I/O IDD Operating Current (VGA YUV 30fps / 2.8v) IPWDN Power Down Current (VGA YUV 30fps / 2.8v) Type : IN & I/O VIH Input Voltage HIGH VIL Input Voltage LOW -0.3V to VDDIO + 0.5V 245℃ 2000V Min. Typ. Max. Unit 2.6 2.8 1.8 2.8 25 10 3.0 V V V mA µA 2.6 3.0 VDDIO * 0.7 V VDDIO * 0.3 V Type : OUT & I/O VOH Output Voltage HIGH VOL Output Voltage LOW AC Operating Condition Symbol fsysclk tsysclk_dc Parameter System clock frequency System clock duty cycle VDDIO * 0.9 V VDDIO * 0.1 Min. 45 Typ. 24 Max. 55 V Unit MHz % Sensor Characteristics Parameter Sensitivity Signal to Noise Ratio Dynamic Range Typ. 1500 41 60 Unit mV/Lux-Sec dB dB All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 3 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 3. I2CTM Bus PAS6329 supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is “1000000” and supports receiving / transmitting speed as maximum 400KHz. I2C Bus Overview z Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. z Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). z Start and stop condition : A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Figure 2.1. z Valid data : The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 2.2. z Both the master and slave can transmit and receive data from the bus. z Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Figure 2.1 Start and Stop conditions Figure 2.2 Valid Data All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 4 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC Data Transfer Format Master transmits data to salve ( write cycle ) z S : Start. z A : Acknowledge by salve. z P : Stop. z RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 – Read cycle, RW = 0 – Write cycle. z SUBADDRESS : The address values of PAS6329 internal control registers. ( Please refer to PAS6329 register description ) During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6329 ) issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the PAS6329 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6329 control register ( address was assigned by 2nd byte ). After PAS6329 issues acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6329 sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS6329 can be programming via this way. Slave transmits data to master ( read cycle ) z The sub-address was taken from previous write cycle. z The sub-address is automatically increment after each byte read. z Am : Acknowledge by master. z Note there is no acknowledgment from master after last byte read. During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS6329. The 8 bits data was read from PAS6329 internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS6329 place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS6329 ) must releases SDA line to master to generate STOP condition. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 5 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 6 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC I2CTM Bus Timing I2CTM Bus Timing Specification Parameter Symbol Standard Mode Unit Min. Max fscl 10 400 KHz tHD:STA 4.0 - µs Low period of the SCL clock. tLOW 4.7 - µs High period of the SCL clock. tHIGH 0.75 - µs Set-up time for a repeated START condition. tSU;STA 4.7 - µs Data hold time. For I2C-bus device. tHD;DAT 0 3.45 µs Data set-up time. tSU;DAT 250 - ns Rise time of both SDA and SCL signals. tr 30 N.D. ns ( notel ) Fall time of both SDA and SCL signals. tf 30 N.D. ns ( notel ) tSU;STO 4.0 - µs Bus free time between a STOP and START. tBUF 4.7 - µs Capacitive load for each bus line. Cb 1 15 pF Noise margin at LOW level for each connected device. ( Including hysteresis ) VnL 0.1 VDD - V Noise margin at HIGH level for each connected device. ( including hysteresis ) VnH 0.2 VDD - V SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Set-up time for STOP condition. Note : It depends on the “high” period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 7 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 4. Registers Register Table Bank 0 0 0 0 0 0 0 0 Address Hex Dec 0 0 1 1 2 2 3 3 4 4 8 8 9 9 A 10 Register Name PartID[15:8] PartID[7:0] VersionID[3:0] SubID[3:0] R_AE_stage_indoor_Sel R_ne_clamp_by8[7:0] R_ISP_TestValueLo[7:0] R_ISP_TestValueHi[7:0] Bits Default Value [7:0] [7:0] [3:0] [3:0] [0] [7:0] [7:0] [7:0] 0x63 0x27 0x00 0x0a 0x0 0x50 0x00 0xff Part ID Part ID VersionID SubID AE indoor stage select 0:11 , 1:12 ne upper bound (clamp to R_ne_clamp_by8*8 ) ISP test mode low data value ISP test mode high data value ISP test mode data generation Bit[4] : defect test pixel insertion Bit[3:0] : 0:no test; 1:white; 2:black; 3:red; 4:green; 5:blue; 6:vertical&horizontal color bar; 7:random data; 8:vertical gray bar; 9:horizontal gray bar; 12-15: motion test; 0 C 12 R_ISP_TestMode[4:0] [4:0] 0x00 0 0 0 F 11 13 15 17 19 14 20 0 0 0 0 19 1A 1B 1C 25 26 27 28 [7:0] [7:0] [7:0] [7:4] [2:0] [7:0] [7:0] [7:0] [7:0] 0x90 0x64 0xf6 0 R_AWB_Window_X[7:0] R_AWB_Window_Y[7:0] R_lpf_min[7:0] R_ny_min[3:0] R_lpf_min[10:8] R_AWB_DGnR_LB_by2[7:0] R_AWB_DGnR_UB_by2[7:0] R_AWB_DGnB_LB_by2[7:0] R_AWB_DGnB_UB_by2[7:0] 0 1D 29 R_Y8bit_Saturate_Thd[7:0] [7:0] 0xfe 0 1E 30 R_Y8bit_Bright_Thd[7:0] [7:0] 0xc8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 3A 3B 3C 3D 3E 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 R_ISP_Gamma_EnH R_ISP_Y00 R_ISP_Y01 R_ISP_Y02 R_ISP_Y03 R_ISP_Y04 R_ISP_Y05 R_ISP_Y06 R_ISP_Y07 R_ISP_Y08 R_ISP_Y09 R_ISP_Y10 R_ISP_Y11 R_ISP_Y12 R_ISP_Y13 R_ISP_Y14 R_Ycap_Very_dark_16X_steps[5:0] R_Ycap_Very_dark_8X_steps[5:0] R_Ycap_Very_dark_4X_steps[5:0] R_Ycap_Very_dark_2X_steps[5:0] R_AE_HIST_BackLight[2:0] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [5:0] [5:0] [5:0] [5:0] [2:0] 0x01 0x0d 0x19 0x2f 0x53 0x62 0x6f 0x7c 0x87 0x9a 0xaa 0xb8 0xc5 0xd8 0xe8 0xf5 0x20 0x18 0x10 0x08 0x00 0x21 0x30 0x49 0x3a 0x78 Notes AWB window width (by4) AWB window height (by4) Lpf minimum value for AE Ny minimum value for AE Lpf minimum value for AE AWB digital gain lower bound for R AWB digital gain upper bound for B AWB digital gain lower bound for B AWB digital gain upper bound for R Ycap_Very_Saturate =(Ycap8bit[7:0] >= R_Y8bit_Saturate_Thd); Ycap_Very_bright_2X =(Ycap8bit[7:0] >= R_Y8bit_Bright_Thd); ISP gamma correction enable ISP Gamma Y0 ISP Gamma Y1 ISP Gamma Y2 ISP Gamma Y3 ISP Gamma Y4 ISP Gamma Y5 ISP Gamma Y6 ISP Gamma Y7 ISP Gamma Y8 ISP Gamma Y9 ISP Gamma Y10 ISP Gamma Y11 ISP Gamma Y12 ISP Gamma Y13 ISP Gamma Y14 Step change when Ycap < Ytar/16 Step change when Ycap < Ytar/8 Step change when Ycap < Ytar/4 Step change when Ycap < Ytar/2 AE histogram backlight, 0~7 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 8 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 0 0 0 3F 40 41 63 64 65 0 42 66 0 43 67 0 46 70 R_AE_HIST_Step_V[4:0] R_AE_HIST_HStart[7:0] R_AE_HIST_VStart[7:0] R_AE_HIST_LCS_OFFSET[2:0] R_AE_HIST_PCS_OFFSET[4:0] R_AE_LumaEstimation_mode R_AE_Hist2Avg_POWER_SEL R_AG_delay_EnH R_DG_delay_EnH R_AWB_DGn_delay_EnH R_AWB_ShowActivePix R_AWB_CountThd 0 47 [4:0] [7:0] [7:0] [7:5] [4:0] [4] [0] [0] [1] [4] [7] 0x0C 0x58 0x44 0x02 0x01 0x00 0x00 0x10 [6:4] 71 0x34 R_AWB_Speed [1:0] Distance of two vertical AE histgram sample points Horizontal start point location of AE histgram sample points Vertical start point location of AE histgram sample points Reserved Reserved 0= histogram based, 1=block-based 0=8, 1=9 AG gain delay for one frame AG DGn delay for one frame AWB gain delay for one frame AWB test mode to show active region AWB pixel in region count threshold 0: 0; 1: AWB_Window_PixCnt>>8; 2: AWB_Window_PixCnt>>7; 3: AWB_Window_PixCnt>>6; 4: AWB_Window_PixCnt>>5; 5: AWB_Window_PixCnt>>4; 6: AWB_Window_PixCnt>>3; 7: AWB_Window_PixCnt>>2; AWB adjust speed. The more, the slower 0: 1 x; 1: 1/2 x; 2: 1/4 x; 3: 1/8 x; 0 0 0 0 49 4A 4B 4C 73 74 75 76 R_AWB_SumRatio_B R_AWB_SumRatio_R R_AWB_CThdL R_AWB_CThdH [7:0] [7:0] [7:0] [7:0] 0x80 0x80 0x42 0x05 AWB B sum ratio = 128/X AWB R sum ratio = 128/X AWB Cthd LB AWB Cthd HB 0 4D 77 R_AWB_CbThdL[7:0] [7:0] 0x64 AWB region test Cb Low threshold -128 ~ +127 (2's complement) 0 4E 78 R_AWB_CrThdL[7:0] [7:0] 0x87 AWB region test Cr Low threshold -128 ~ +127 (2's complement) 0 4F 79 R_AWB_CbCrThdL[7:0] [7:0] 0x00 AWB region test Cb+Cr Low threshold -128 ~ +127 (2's complement) 0 50 80 R_AWB_CbThdH[7:0] [7:0] 0x75 AWB region test Cb High threshold -128 ~ +127 (2's complement) 0 51 81 R_AWB_CrThdH[7:0] [7:0] 0x96 AWB region test Cr High threshold -128 ~ +127 (2's complement) 0 52 82 R_AWB_CbCrThdH[7:0] [7:0] 0xff AWB region test Cb+Cr High threshold -128 ~ +127 (2's complement) 0 0 0 0 0 0 0 53 54 56 57 58 59 5A 83 84 86 87 88 89 90 R_Ylow R_Yhigh R_AE_stage_YlowLL_thd[4:0] R_AWB_LockRange__In[3:0] R_AWB_LockRange_Out[5:0] R_AWB_LockRange__In_LL[5:0] R_AWB_LockRange_Out_LL[5:0] [7:0] [7:0] [4:0] [3:0] [5:0] [5:0] [5:0] 0x1e 0xff 0x12 0x02 0x04 0x04 0x06 Low bound of “light-pixel”Y in AWB High bound of “light-pixel”Y in AWB (AE stage >= thd) --> use AWB Lockrange_LL AWB Lockrange In (NL) AWB Lockrange Out (NL) AWB Lockrange In (LL) AWB Lockrange Out (LL) 0 5B 91 R_AWB_MinStep_th[2:0] [2:0] 0x00 AWB mininum step size 0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128 0 0 5C 5F 92 95 63 99 0 0 0 64 65 66 100 101 102 [4:0] [7:0] [5] [4] [7:0] [7:4] [4] 0x0C 0x14 0 R_AE_HIST_Step_H[4:0] R_AE_LockRange_Out_LB[7:0] R_ISP_EnH ISP_EnH_update R_AE_LockRange_Out_UB[7:0] R_AE_LockRange__In[3:0] R_AE_EnH 0x20 0x14 0x41 0x00 Distance of two horizontal AE histgram sample points AE Lockrange Out LB ISP enable Flag: ISP enable is sync by vsync AE Lockrange Out UB AE Lockrange In AE enable All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 9 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 0 0 0 0 0 0 67 68 6B 6C 6D 6F 103 104 107 108 109 111 0 70 112 0 72 114 0 0 0 0 0 73 74 76 79 7B 115 116 118 121 123 0 0 0 0 0 0 0 0 81 84 86 8E 8F 90 91 92 R_TGWr_buf_EnH [1] 0x01 Enable I2C buffer for TG when AE on R_freq_60 [0] 0x01 Set de-flicker frequency 0/1: 50/60Hz [7:0] [6:0] [4:0] [4:0] [7:0] [7:0] [2:0] [6:4] [0] [4] [7:0] [7:0] [7:0] [7:0] [7:0] 0x97 0x31 0x07 0x1c 0x3f 0x82 0x00 0x00 0x00 0x01 0xbe 0x9c 0x5e 0x16 0x04 Input_frequency/2048 Input_frequency/2048 Minimum AE stage Maximum AE stage (AE_maxStage<=31) AG_stage upper bound at max AE_stage 0~255, Target luminance of AE Frame wait-state for AE adjust Frame wait-state for AWB adjust Auto-white balance enable AWB gain reset AWB Balance gain R AWB Balance gain B Reserved ISP Hsize Offset ISP Vsize Offset R_SysClk_freq[7:0] R_SysClk_freq[14:8] R_AE_minStage[4:0] R_AE_maxStage[4:0] R_AG_stage_UB R_Ytar8bit R_AE_wait_state R_AWB_wait_state R_AWB_EnH R_AWB_Gain_rst R_AWB_BalGain_R[7:0] R_AWB_BalGain_B[7:0] R_AWB_HCT_WeightThd[7:0] R_ISP_HOffset[7:0] R_ISP_VOffset[7:0] R_AE_Speed [5:4] 0x00 AE speed, the more, the slower 0: 1 x; 1: 1/2 x; 2: 1/4 x; 3: 1/8 x; R_AE_MinStep_th[1:0] [1:0] 0x00 AE Minimun step threshold select 0: 16; 1:32; 2:64; 3:128; R_AE_StageChg_Saturate R_AE_StageChg_Bright2X R_AE_chg_wait R_ImgEffect_c0 R_ImgEffect_c1 R_ImgEffect_c2 R_ImgEffect_c3 [5:0] [5:0] [2:0] [7:0] [7:0] [7:0] [7:0] 0x20 0x10 0x00 0x00 0x00 0x00 0x00 AE StageChg when (Average Lumiance > saturate threshold) AE StageChg when (Average Lumiance > 2*Target Lumiance) AE wait state when AE change Texp Image Effect parameter 0 (ISP_UpdateFlag=1, update) Image Effect parameter 1 (ISP_UpdateFlag=1, update) Image Effect parameter 2 (ISP_UpdateFlag=1, update) Image Effect parameter 3 (ISP_UpdateFlag=1, update) [3:0] 0x00 Image Effect mode 0: monochrome; 1: negative; 2: x-ray; 3: Sepia / Cold / Warm / Sunset; 6: Solarize; 10: Pixelate; (ISP_UpdateFlag=1, update) [0] 0x00 Image effect enable (ISP_UpdateFlag=1, update) [3:0] [4] [4] 0x00 0x00 0x01 Senclk output deley select Sensor clock output inversion Lens shading enable 129 132 134 142 143 144 145 146 0 93 147 R_ImgEffectMode 0 94 148 R_ISP_ImgEffect_En 0 95 149 0 97 151 R_SENCLK_delay[3:0] R_SENCLK_Inv R_Shading_EnH 0 99 153 R_OffsetX_R[6:0] [6:0] 0x00 Horizontal distances between shading center and sensor array center of R-channel, MSB:sign bit, -63~+63 0 9A 154 R_OffsetY_R[6:0] [6:0] 0x00 Vertical distances between shading center and sensor array center of R-channel, MSB:sign bit, -63~+63 0 9B 155 R_OffsetX_G[6:0] [6:0] 0x00 Horizontal distances between shading center and sensor array center of G-channel, MSB:sign bit, -63~+63 0 9C 156 R_OffsetY_G[6:0] [6:0] 0x00 Vertical distances between shading center and sensor array center of G-channel, MSB:sign bit, -63~+63 0 9D 157 R_OffsetX_B[6:0] [6:0] 0x00 Horizontal distances between shading center and sensor array center of B-channel, MSB:sign bit, -63~+63 0 9E 158 R_OffsetY_B[6:0] [6:0] 0x00 Vertical distances between shading center and sensor array center of B-channel, MSB:sign bit, -63~+63 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 10 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9F A0 A1 A2 A3 A4 A5 A6 A7 AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 159 160 161 162 163 164 165 166 167 174 175 176 177 178 179 180 181 182 183 184 0 B9 185 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BA BB BB BC BD BE BF C0 C1 C2 C3 CC CD CE CF D0 D1 D4 186 187 187 188 189 190 191 192 193 194 195 204 205 206 207 208 209 212 0 D5 213 0 0 0 0 0 0 0 DE E0 E1 E2 E3 E6 EB 222 224 225 226 227 230 235 0 ED 237 0 EE 238 R_LSC_R1[6:0] R_LSC_G1[6:0] R_LSC_B1[6:0] R_LSC_R2[6:0] R_LSC_G2[6:0] R_LSC_B2[6:0] R_LSFT_1[2:0] R_LSFT_2[1:0] R_LSFT_3[2:0] AWB_Valid__PixCnt_vs[15:8] AWB_Valid__PixCnt_vs[7:0] Total_Gain[14:8] Total_Gain[7:0] AWB_Sum_R[15:8] AWB_Sum_R[7:0] AWB_Sum_G[15:8] AWB_Sum_G[7:0] AWB_Sum_B[15:8] AWB_Sum_B[7:0] LineCnt_Sensor[7:0] LineCnt_Sensor[9:8] FrameCnt[2:0] Ycap8bit AWB_EnH_vs AE_EnH_vs AG_stage[7:0] AE_stage[4:0] Reg_lpf[7:0] Reg_lpf[13:8] Reg_ny [7:0] Reg_ny [10:8] Reg_ne[7:0] Reg_ne[12:8] DGn_R_vs[7:0] DGn_R_vs[8] DGn_G_vs[7:0] DGn_G_vs[8] DGn_B_vs[7:0] DGn_B_vs[8] reg_FG_stage_6329[7:0] reg_cgh_6329[1:0] reg_DG_6329[3:0] AE_Already_Locked_vs R_ISP_HSize[7:0] R_ISP_HSize[9:8] R_ISP_VSize[7:0] R_ISP_Vsize[9:8] R_ISP_FastUpdate R_SwTristate ISP_Update ISP_FrameSkip RegBank_SWRstn Sensor_IF_SWRstn ISP_Top1_SWRstn ISP_Top2_SWRstn AE_AWB_SWRstn [6:0] [6:0] [6:0] [6:0] [6:0] [6:0] [2:0] [1:0] [2:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [1:0] [6:4] [7:0] [6] [7] [7:0] [4:0] [7:0] [5:0] [7:0] [2:0] [7:0] [4:0] [7:0] [0] [7:0] [0] [7:0] [0] [7:0] [1:0] [7:4] [0] [7:0] [1:0] [7:0] [1:0] [0] [0] [0] [4] [0] [1] [2] [3] [4] 0x00 0x00 0x00 0x50 0x50 0x50 0x04 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x02 0xe0 0x01 0x00 0x0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Quartic parameter of R-channel Quartic parameter of G-channel Quartic parameter of B-channel Square parameter of R-channel Square parameter of G-channel Square parameter of B-channel Reserved Reserved Reserved AWB valid pixel cnt (by8) AWB valid pixel cnt (by8) Total gain (FG * GG, 7.8 format) Total gain (FG * GG, 7.8 format) AWB Sum R AWB Sum R AWB Sum G AWB Sum G AWB Sum B AWB Sum B Line counter Line counter Frame counter (0~7) Y sum report AWB enable sync by vsync AE enable sync by vysnc AG Stage AE Stage Line Per Frame Register Line Per Frame Register Ny Register Ny Register Ne Register Ne Register R Digital Gain sync by vsync R Digital Gain sync by vsync G Digital Gain sync by vsync G Digital Gain sync by vsync B Digital Gain sync by vsync B Digital Gain sync by vsync AE computed Front gain AE computed CGH AE computed DG 1=locked, 0=not locked ISP output Horizontal size, (before skip function) ISP output Horizontal size, (before skip function) ISP output Vertical size, (before skip function) ISP output Vertical size, (before skip function) ISP Fast Update mode Sw Tristate ISP_UpdateFlag (ISP_UpdateFlag=1, update) SW reset for RegBank0, RegBank1 SW reset for Sensor interface SW reset for ISP_Top1 SW reset for ISP_Top2 SW reset for AE_AWB All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 11 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC Other_SWRstn [5] 0x00 SW reset for Others R_RegBankSel [2:0] 0x00 Register Bank Select 0: ISP1 Register Bank (default); 1: Sensor Register Bank; 2: ISP2 Register Bank; [0] [4] [3:0] [7:0] [7:0] 0x00 0x00 0x07 0x50 0x40 ISP2_UpdateFlag Auto contrast enable Contrast strength, 0~15 Contrast strength UB Contrast strength LB 1 EF 239 2 0 0 2 B 11 2 2 C D 12 13 ISP2_Update R_AUTO_Contrast_EnH R_AUTO_Contrast_Strength R_AUTO_Contrast_UB R_AUTO_Contrast_LB 2 18 24 R_Curve_Y3[7:0] [7:0] 0x6f ISP tone curve Y3: Before Histogram, real value=R_Curve_Y3[7:0]<<2 2 19 25 R_Curve_Y6[7:0] [7:0] 0xa5 ISP tone curve Y6: Before Histogram, real value=R_Curve_Y6[7:0]<<2 2 2 26 27 38 39 2 2A 42 2 2 2 2 2 2 2C 2D 2E 2F 30 35 44 45 46 47 48 53 2 36 54 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 37 3E 3F 40 41 42 43 44 45 46 47 55 56 57 58 59 5A 5B 5C 55 62 63 64 65 66 67 68 69 70 71 85 86 87 88 89 90 91 92 R_DefectThd_NL[4:0] R_DefectThd_LL[4:0] R_FlatRatio[3:0] R_Flat_En R_ISP_Edge_En0 R_Edge_UB[7:0] R_Edge_LB[7:0] R_EdgeThdLB[7:0] R_AE_stage_LL[4:0] R_AE_stage_NL[4:0] R_Gamma_Strength_NL[4:0] R_Gamma_Strength_Delta[4:0] R_Manual_Gamma_Strength R_Gamma_Strength_LL[4:0] R_CCMbSign[5:0] R_CCMb0_0[7:0] R_CCMb0_1[7:0] R_CCMb0_2[7:0] R_CCMb1_0[7:0] R_CCMb1_1[7:0] R_CCMb1_2[7:0] R_CCMb2_0[7:0] R_CCMb2_1[7:0] R_CCMb2_2[7:0] R_Manual_EdgeRatio R_EdgeRatio_Delta[4:0] R_EdgeRatio_LL[4:0] R_EdgeRatio_NL[4:0] R_Manual_Edge_th R_Edge_th_Delta[4:0] R_Edge_th_LL[7:0] R_Edge_th_NL[7:0] [4:0] [4:0] [3:0] [6] [7] [7:0] [7:0] [7:0] [4:0] [4:0] [4:0] [4:0] [5] [4:0] [5:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4] [4:0] [4:0] [4:0] [4] [4:0] [7:0] [7:0] 0x0c 0x0c 0x08 0x01 0x01 0x20 0x19 0x10 0x13 0x11 0x10 0x08 0x00 0x08 0x33 0x26 0x4b 0x0f 0x18 0x52 0x6a 0x6a 0x68 0x02 0x00 0x08 0x04 0x0a 0x00 0x08 0x0a 0x08 Defect test threshold @ Normal Light Defect test threshold @ Low Light ISP edge enhancement flat ratio ISP edge enhancement flat enable ISP edge enhancement enable ISP edge enhancement value upper bound ISP edge enhancement value lower bound ISP edgethd LB AE_stage > R_AE_stage_LL =>Low Light AE_stage < R_AE_stage_NL =>Normal Light Gamma Strength @ NL Increment when AE/AG stage change Fix setting to NL Gamma Strength @ LL CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient CCM matrix coefficient Fix setting to normal light Increment when AE/AG state change Edge ratio @Low Light Edge ratio @Normal Light Fix setting to normal light Increment when AE/AG state change Edge threshold @ Low Light Edge threshold @ Normal Light [0] 0x01 1: fast change, +-Delta; 0: slow change, +-(1/Delta); R_Saturation_2X R_Manual_Saturation R_Saturation_Delta[4:0] R_Saturation_LL[4:0] R_Saturation_NL[4:0] [1] [4] [4:0] [4:0] [4:0] 0x00 0x00 0x01 0x0b 0x16 Color Saturation double Fix setting to normal light Increment when AE/AG state change Color Saturation @ Low Light Color Saturation @ Normal Light R_Shading_CP_R_Fast [0] 0x00 1: fast change, +-Delta; 0: slow change, +-(1/Delta); R_Manual_Shading_CP [4] 0x00 Manual Shading percentage R_Saturation_Fast 2 5D 93 2 2 2 5E 5F 60 94 95 96 2 61 97 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 12 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 2 62 98 2 63 99 2 2 2 2 2 2 2 2 2 2 2 2 2 2 64 65 66 69 6A 9B 9C 9D 9E 9F A0 A1 A2 A4 100 101 102 105 106 155 156 157 158 159 160 161 162 164 2 2 2 B2 BF C0 R_Shading_CP_R_Delta[4:0] R_Shading_CP_R_NL[3:0] R_Shading_CP_R_LL[3:0] R_Contrast_En R_Contrast_Str[7:0] R_Contrast_CP[7:0] R_Brightness_LL[7:0] R_Brightness_NL[7:0] R_ISP_WOI_HSize[9:8] R_ISP_WOI_HSize[7:0] R_ISP_WOI_VSize[9:8] R_ISP_WOI_VSize[7:0] R_ISP_WOI_HOffset[9:8] R_ISP_WOI_HOffset[7:0] R_ISP_WOI_VOffset[9:8] R_ISP_WOI_VOffset[7:0] R_ScalingFIFO_Out_NP[4:0] [4:0] [3:0] [7:4] [0] [7:0] [7:0] [7:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [4:0] 0x02 0x0f 0x00 0x01 0x40 0x82 0x00 0x00 0x02 0x80 0x01 0xe0 0x00 0x00 0x00 0x00 0x02 Increment when AE/AG state change Shading compensation percentage @Normal Light Shading compensation percentage @Low Light Contrast Enable Contrast Strength (ISP2_UpdateFlag=1, update) Contrast CP (ISP2_UpdateFlag=1, update) Brightness @ Low Light Brightness @ Normal Light (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) (ISP2_UpdateFlag=1, update) R_EncDecimationNo_X[3:0] [3:0] 0x00 ISP decimation no in X-direction (ISP_Zoom_UpdateFlag=1, update) R_EncDecimationNo_Y[3:0] [7:4] 0x00 ISP decimation no in Y-direction (ISP_Zoom_UpdateFlag=1, update) R_UV_Swap R_YC_Swap R_RGB565_mode[3:0] [1] [2] [3:0] 0x00 0x01 0x00 U V Swap Y C Swap RGB565_mode 178 191 192 2 C1 193 2 C2 194 R_Format_Sel [5:4] 0x00 Output Data format select 0:YUV; 1:RGB565; 2:RGB555; 3:RGB444; (ISP2_UpdateFlag=1, update) R_Vsync_INV R_Hsync_INV R_Pxclk_INV R_Pxclk_Gated_InHVSync R_SenVsync_En R_HsyncInVsync R_PxclkO_dly R_HsyncO_dly [0] [1] [2] [3] [4] [5] [6:4] [2:0] 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 Vsync inverse Hsync inverse Pxclk inverse Gate PXCLK in hsync/vsync Reserved hsync toggle when vsync high Pxclk Delay Cell Select Hsync Delay Cell Select All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 13 V1.0, 2011/03/03 AVDD28 DVDD28 SCL PXD2 PXD0 D3 D1 B3 C1 B2 B1 SCL AVDD28 PXD2 DVDD28 PXD0 VDDD PXD1 PXCLK DGND PAS6329LT CSP-22L AGND VREF E1 VSYNC PXD7 PXD6 PXD5 NC PXD4 PXD5 PXD6 PXD7 VSYNC C4 D5 D4 PXD4 C5 B4 B5 note : AGND 0.1uF C3 AVDD28 VREF 4.7uF C5 AGND AVDD28 DGND VDDD AGND DVDD28 AGND 0.1uF C4 CSB SCL SDA PXD0 PXD1 PXD2 PXD3 PXD4 PXD5 PXD6 PXD7 HSY NC VSY NC PXCLK SY SCLK 24-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CON1 All capacitors must be close to the sensor as passible Sensor reset pin, "RSTN", low active Sensor power-down pin, "CSB", high active AGND, analog ground DGND, digital ground DVDD28 = 2.8V typical, VDDD = 1.8V, AVDD28 = 2.8V typical, DGND 0.1uF 0.1uF DGND C2 C1 VDDD PAS6329 VREF VSSA E2 VDDD PXD3 E3 CSB CSB E4 SDA SDA U1 SYSCLK A1 SYSCLK A2 PXCLK A3 PXD1 A4 PXD3 A5 VSSD HSYNC E5 PixArt Imaging Inc. E-mail: [email protected] HSYNC DVDD28 PixArt Imaging Inc. CMOS Image Sensor IC 5. Reference Circuit Schematic All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14 V1.0, 2011/03/03 PixArt Imaging Inc. PAS6329 CMOS Image Sensor IC 6. Package Information *Note The formation of image is the result formed by package Top view(A1 : left-up) and general Lens(invert and mirror the image). All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 15 V1.0, 2011/03/03