(Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock FEATURES • • • • • • • • • • • • DESCRIPTION Advanced One Time Programmable (OTP) PLL design Programmable PLL or direct oscillation operation Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) Output Frequency up to o 65MHz @ 1.8V operation o 9/MHz @ 2.5V operation o 125MHz @ 3.3V operation Reference Input Frequency: 1MHz to 200MHz Accepts >0.1V reference signal input voltage Low current consumption, <10µA when PDB is activated One programmable I/O pin can be configured as Output Enable (OE), Frequency Switching (FSEL), or Power Down (PDB) input. Disabled outputs programmable as HiZ or Active Low. Single 1.8V, 2.5V, or 3.3V ± 10% power supply Operating temperature range from 0°C to 70°C Available in 6-pin SOT23 & DFN GREEN/RoHS Compliant packages The PL611s-27 is a general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL product family. Designed to fit in a small 6-pin DFN, or 6-pin SOT package for high performance applications, the PL611s-27 offers very low phase noise, jitter, and power consumption, while offering 2 clock outputs. The Frequency Switching (FSEL) capability of PL611s-27 allows for programming two sets of frequencies, while the power down feature of PL611s-27, when activated, allows the IC to consume less than 10µA of power. PL611s-27’s programming flexibility allows generating any output using a Reference input signal. PACKAGE PIN CONFIGURATION 6 5 4 OE, PDB, FSEL VDD CLK0 1 GND 2 FIN 3 PL611s-27 1 2 3 PL611s-27 FIN CLK1 GND CLK1 6 CLK0 5 VDD 4 OE, PDB, FSEL DFNDFN-6L SOT23 SOT2323-6L (2.0mmx1 mmx1.3mmx0 mmx0.6mm) mm) (3.0mmx3 mmx3.0mmx1 mmx1.35mm 35mm) mm) BLOCK DIAGRAM FIN F ref R-counter (8-Bit) M-counter (11-Bit) Phase Detector Charge Pump Fvco= Fref * (2 * M / R) P-counter (5-Bit) Programmable Function Loop Filter VCO Fout=FVCO/(2*P) Programming Logic CLK1 CLK0 OE, PDB, FSEL 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 1 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock KEY PROGRAMMING PARAMETERS CLK Output Frequency Programmable Input/Output Output Drive Strength FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Three optional drive strengths to choose from: One output pin can be configured as: • Low: 4mA • Std: 8mA (default) • High: 16mA • • • • OE - input PDB - input FSEL – input HiZ or Active Low disabled state PACKAGE PIN ASSIGNMENT Name Pin Assignment DFN SOT Pin# Pin # Type Description CLK1 2 1 O Programmable Clock Output GND FIN 3 1 2 3 P I GND connection Reference input pin This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down (PDB) input or Frequency Switching (FSEL) input. This pin has an internal 60KΩ pull up resistor. OE, PDB, FSEL VDD CLK0 6 4 5 4 I 5 6 P O The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. State OE PDB FSEL 0 Disable CLK Power Down Mode Frequency ‘2’ 1 (default) Normal mode Normal mode Frequency ‘1’ VDD connection Programmable Clock Output OE AND PDB FUNCTION DESCRIPTION OE PDB Osc. PLL CLK0 CLK1 1 N/A On On On On 0 N/A N/A N/A 1 0 On On Off Off On Off HiZ or Active Low On HiZ or Active Low On On HiZ or Active Low Note: HiZ or Active Low states are programmable functions and will be set per request. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 2 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock FUNCTIONAL DESCRIPTION PL611s-27 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-27 accepts a reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 55MHz. This flexible design allows the PL611s-27 to deliver any PLL generated frequency, F REF (Ref Clk) frequency or F REF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-27 are mentioned below: PLL Programming Output Enable (OE) The PLL in the PL611s-27 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60kΩ pull up resistor giving a default condition of logic “1”. Clock Output (CLK0) Power-Down Control (PDB) CLK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF (Ref Clk Frequency) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. The Power Down (PDB) feature allows the user to put the PL611s-27 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10µA of power. The PDB pin incorporates a 60kΩ pull up resistor giving a default condition of logic “1”. Clock Output (CLK1) The PDB feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. The CLK1 feature allows the PL611s-27 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference (Ref Clk) Frequency FREF / 2 CLK0 CLK0 / 2 The OE feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-27 to switch between two pre-programmed outputs allowing the device “On the Fly” frequency switching. The FSEL pin incorporates a 60kΩ pull up resistor giving a default condition of logic “1”. When using the OE function CLK1 will remain “Always On” and will not be disabled when OE is pulled low. When using the PDB function CLK1 will be disabled along with CLK0. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 3 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD - 0.5 7 V Input Voltage Range VI - 0.5 V DD + 0.5 V Output Voltage Range VO - 0.5 V DD + 0.5 V 260 °C Supply Voltage Range Soldering Temperature (Green package) 10 Data Retention @ 85°C Storage Temperature TS Ambient Operating Temperature* Year -65 150 °C -40 85 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS CONDITIONS MIN. TYP. @ V DD =3.3V Input (FIN) Frequency @ V DD =2.5V MAX. UNITS 200 1 166 @ V DD =1.8V MHz 133 Input (FIN) Signal Amplitude Internally AC coupled (High Frequency) 0.9 V DD Vpp Input (FIN) Signal Amplitude Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz 0.1 VDD V pp @ V DD =3.3V 125 MHz @ V DD =2.5V 90 MHz @ V DD =1.8V 65 MHz At power-up (after V DD increases over 1.62V) 2 ms OE Function; Ta=25º C, 15pF Load 10 ns PDB Function; Ta=25º C, 15pF Load 2 ms Output Frequency Settling Time Output Enable Time Output Rise Time 15pF Load, 10/90% V DD , High Drive, 3.3V 1.2 1.7 ns Output Fall Time 15pF Load, 90/10% V DD , High Drive, 3.3V 1.2 1.7 ns Duty Cycle V DD /2 50 55 % Period Jitter,Pk-to-Pk* With capacitive decoupling between V DD and (measured from 10,000 samples) GND. * Note: Jitter performance depends on the programming parameters. 45 70 ps 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 4 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock DC SPECIFICATIONS PARAMETERS Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Stand By Current, with Loaded Outputs SYMBOL I DD I DD I DD I DD CONDITIONS MIN. @ V DD =3.3V, 27MHz, load=15pF @ V DD =2.5V, 27MHz, load=15pF @ V DD =1.8V, 27MHz, load=15pF When PDB=0 Operating Voltage V DD 1.62 Output Low Voltage V OL I OL = +4mA Standard Drive Output High Voltage V OH I OH = -4mA Standard Drive Output Current, Low Drive I OSD Output Current, Standard Drive Output Current, High Drive TYP. MAX. UNITS 5.5 mA 3.8 mA 1.8* mA <10 µA 3.63 V 0.4 V V DD – 0.4 V V OL = 0.4V, V OH = 2.4V 4 mA I OSD V OL = 0.4V, V OH = 2.4V 8 mA I OHD V OL = 0.4V, V OH = 2.4V 16 mA * Note: Please contact PhaseLink, if super low-power is required. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 5 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock LAYOUT RECOMMENDATIONS DFN-6L Evaluation Board The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Multiple VDD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1µF for designs using crystals < 50MHz and 0.01µF for designs using crystals > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 Ω ) 50Ω line Series Resistor Use value to match output buffer impedance to 50 Ω trace. Typical value 30 Ω 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 6 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load . Crystal Cst XIN XOUT 1 Cpt 8 Cpt CST – Series Capacitor, used to lower circuit load to match crystal load . Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors , Used to raise the circuit load to match the crystal load. Lowers frequency offset . 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 7 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 C b e L DFN-6L D1 Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e D Pin 6 ID Chamfer E E1 L Pin1 Dot A A1 A3 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 8 (Preliminary) PL611s-27 1.8V to 3.3V PicoPLL TM Programmable Clock ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL611s-27-XXX X X X PART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L T=SOT23-6L † NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I = INDUSTRIAL Part/Order Number Marking† PL611s-27-XXXGC-R PL611s-27-XXXTC-R XXX 27XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SOT23 (Tape and Reel) Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information. PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 9