PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) FEATURES • • 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50uW. Available outputs: PECL, LVDS, or CMOS. Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16 pin (TSSOP or SOIC) VDD 1 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GND SEL3^ 4 13 CLKC SEL2^ 5 12 VDD OE 6 11 CLKT VCON 7 10 GND GND 8 9 GND PLL 520-1x • • • • • PIN CONFIGURATION DESCRIPTION The PLL520-17/-18/-19 family of VCXO IC’s is specifically designed to pull high frequency fundamental crystals. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. ^: Internal pull-up OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-18 PLL520-17 PLL520-19 BLOCK DIAGRAM OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled OE input: Logical states defined by PECL levels for PLL520-18 Logical states defined by CMOS levels for PLL520-17/-19 SEL OE VCON XIN XOUT Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) Q Q PLL by-pass PLL520-17/-18/-19 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PIN DESCRIPTIONS Name Number Type XIN XOUT OE VCON GND 2 3 6 7 8,9, 10, 14 I I I I P CLKT 11 O CLKC 13 O SEL 4,5,15,16 I VDD 1, 12 P Description Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Output enable. See Output Enable Logic Levels on page 1. Voltage control input. Ground. True output PECL (PLL520-18) or LVDS (PLL520-19). No Connect for CMOS (PLL520-17). Complementary output PECL (PLL520-18) or LVDS (PLL520-19). CMOS output for (PLL520-17). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. FREQUENCY SELECTION TABLE Pin #4 SEL3 Pin #5 SEL2 Pin #15 SEL1 Pin #16 SEL0 Selected Multiplier 0 0 1 1 Fin x 8 1 0 1 1 Fin x 4 1 1 1 0 Fin x 2 1 1 1 1 No multiplication All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS CX+ CXC0 65MHz to 130MHz (VDD=3.3V) Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency γ OF MIN. MAX. 120 2 2 2 300 200 Fund. UNITS pF MHz 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL CONDITIONS T VCXOSTB From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V VCON = 0 to 3.3V VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW MIN. TYP. MAX. UNITS 10 ms 200* ppm ±100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB ppm pF % ppm/V kΩ kHz 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD CONDITIONS MIN. TYP. PECL/LVDS/CMOS V DD @ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) 2.97 45 45 45 50 50 50 ±50 MAX. UNITS 100/80/40 mA 3.63 55 55 55 V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 5. Jitter Specifications PARAMETERS CONDITIONS MIN. 77.76MHz 155.52MHz 622.08MHz 77.76MHz 155.52MHz 622.08MHz Integrated 12 kHz to 20 MHz at 77.76MHz Integrated 12 kHz to 20 MHz at 155.52MHz Integrated 12 kHz to 20 MHz at 622.08MHz Period jitter RMS Period jitter peak-to-peak Integrated jitter RMS TYP. MAX. 2.5 4 5 24 29 32 0.5 1.5 1.5 UNITS ps ps ps 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 77.76MHz 155.52MHz 622.08MHz -75 -75 -75 -95 -95 -95 -125 -120 -115 -145 -125 -118 -155 -123 -115 dBc/Hz Phase Noise relative to carrier Note: Phase Noise measured at VCON = 0V 7. CMOS Output Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD R L = 100 Ω (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. V OH V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS V DD – 1.620 V V 11. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time CONDITIONS tr tf MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit TYP. MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew OUT OUT VDD 50Ω 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tF tR PACKAGE INFORMATION 16 PIN Narrow SOIC, TSSOP ( mm ) SOIC TSSOP Symbol Min. Max. Min. A 1.35 1.75 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 9.80 10.00 4.90 5.10 E 3.80 4.00 4.30 H 5.80 6.20 L 0.40 1.27 e 1.27 BSC E H Max. D 4.50 6.40 BSC 0.45 0.75 0.65 BSC A A 1 C e B L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL520-17/-18/-19 Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-1x O C TEMPERATURE C=COMMERCIAL I=INDUSTRAL PART NUMBER PACKAGE TYPE O=TSSOP S=SOIC Order Number Marking Package Option PLL520-17OC PLL520-17OC-R PLL520-17SC PLL520-17SC-R P520-17OC P520-17OC P520-17SC P520-17SC TSSOP – Tube TSSOP – Tape & Reel SOIC – Tube SOIC – Tape & Reel PLL520-18OC PLL520-18OC-R PLL520-18SC PLL520-18SC-R P520-18OC P520-18OC P520-18SC P520-18SC TSSOP – Tube TSSOP – Tape & Reel SOIC – Tube SOIC – Tape & Reel PLL520-19OC PLL520-19OC-R PLL520-19SC PLL520-19SC-R P520-19OC P520-19OC P520-19SC P520-19SC TSSOP – Tube TSSOP – Tape & Reel SOIC – Tube SOIC – Tape & Reel PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7