Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) FEATURES • • • • • • • 65 mil 750kHz to 400MHz output range. Low phase noise output (@ 10kHz frequency offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for 106.25MHz, -125dBc/Hz for 155.52MHz). Selectable CMOS, PECL and LVDS output. 12 to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (+/-190 ppm) 3.3V operation. Available in DIE (65 mil x 62 mil). 25 BLOCK DIAGRAM VCO Divider Charge Pump XIN XOUT Reference Divider XTAL OSC VARICAP VCON Phase Detector 21 22 (1550,1475) 20 19 18 17 16 15 14 28 13 29 12 11 30 10 31 9 1 2 3 4 5 6 7 8 (0,0) X The PLL502-10 is a monolithic low jitter and low phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC Die, with CMOS, LVDS and PECL output, covering the 750kHz to 400MHz output range. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The same die can be used as a VCXO with output frequencies ranging from F XIN / 16 to F XIN x 16 thanks to frequency selector pads. This makes the PLL502-10 ideal as a universal die for applications ranging from ADSL to SONET. SEL 23 27 Y DESCRIPTIONS 24 26 62 mil • • DIE CONFIGURATION + Loop Filter VCO OE CLKBAR CLK DIE SPECIFICATIONS Name Value Size Reverse side 62 x 65 mil GND Pad dimensions 80 micron x 80 micron Thickness 10 mil OUTPUT SELECTION AND ENABLE Pad #18 OUTSEL1 0 0 1 1 Pad #25 OUTSEL0 0 1 0 OE_SELECT (Pad #9) OE_CTRL (Pad #30) 0 (Default) 1 0 1 (Default) 0 1 (Default) 1 Selected Output High Drive CMOS Standard CMOS PECL LVDS State Output enabled Tri-state Tri-state Output enabled Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “0” Logical states defined by CMOS levels if OE_SELECT is “1” 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 1 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) FREQUENCY SELECTION TABLE Pad #28 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Pad #29 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Pad #19 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pad #20 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Multiplier Reserved Reserved Reserved Reserved Reserved Reserved Fin / 8 Fin x 2 Reserved Fin / 2 Fin / 16 Fin x 4 Fin / 4 Fin x 8 Fin x 16 No multiplication All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 2 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 7 V Input Voltage, dc VI V SS -0.5 V DD +0.5 V Output Voltage, dc VO V SS -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C 260 °C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL F XIN C L (xtal) CONDITIONS MIN. Parallel Fundamental Mode TYP. 12 at VCON = 1.65V MAX. UNITS 25 MHz 9.5 pF C 0 /C 1 (xtal) AT cut 250 - RE AT cut 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB CONDITIONS MIN. From power valid TYP. MAX. 10 UNITS ms VCXO Tuning Range F XIN = 12 - 25MHz; XTAL C 0 /C 1 < 250 380 ppm CLK output pullability 0V ≤ VCON ≤ 3.3V ±190 ppm Linearity 5 VCXO Tuning Characteristic 115 VCON input impedance VCON modulation BW 10 % ppm/V 2000 kΩ 25 kHz 0V ≤ VCON ≤ 3.3V, -3dB Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 3 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD CONDITIONS PECL/LVDS/CMOS MIN. MAX. Fout < 24MHz 25/25/15 24MHz < Fout < 96MHz 65/45/30 96MHz < Fout < 400MHz 100/80/40 3.13 @ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) Output Clock Duty Cycle TYP. 45 45 45 mA 3.47 V 55 55 55 % 50 50 50 ±50 Short Circuit Current UNITS mA 5. Jitter specifications PARAMETERS Period jitter RMS CONDITIONS FREQUENCY With capacitive decoupling between VDD and GND. MIN. TYP. 19.44MHz 5 77.76MHz 8 155.52MHz 9 Accumulated jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 155.52MHz TBM Integrated jitter RMS Integrated 12 kHz to 20 MHz 155.52MHz 3 MAX. UNITS ps ps 4 ps 6. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz 19.44MHz -60 -90 -112 -140 -150 106.25MHz -60 -90 -112 -127 -125 155.52MHz -60 -90 -112 -125 -123 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 4 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VOS VDIFF RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% V DIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 5 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 10. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew VDD 50Ω OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 6 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) PAD ASSIGNMENT Pad # Name X (µ µ m) Y (µ µ m) 1 GND 248 109 2 GND 361 109 3 GND 473 109 4 GND 587 109 5 GND 702 109 6 N/C 874 109 7 GND 1042 109 8 GNDBUF 1171 109 9 OE_SELECT 1400 125 10 LVDS 1400 259 11 PECL 1400 476 12 VDDBUF 1400 616 13 VDDBUF 1400 716 14 PECLB 1400 871 15 LVDSB 1400 1089 16 CMOS 1400 1227 17 GNDBUF 1389 1365 18 OUTSEL1 1232 1365 19 SEL1 1042 1365 20 SEL0 854 1365 21 VDD 659 1365 22 VDD 559 1365 23 VDD 459 1365 24 VDD 358 1365 25 OUTSEL0 194 1365 26 XIN 109 1223 27 XOUT 109 1017 28 SEL3 109 858 29 SEL2 109 646 30 OE_CTRL 109 397 31 VCON 109 181 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 7 Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL502-10 D C PART NUMBER TEMPERATURATRE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE D=DIE PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 8