PLL PLL602-30

PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
DIE CONFIGURATION
26
XOUT
27
SEL3
28
SEL2
29
OE_CTRL
30
N/C
31
VDD
VDD
VDD
VDD
SEL0^
SEL1^
OUTSEL1^
25
24
23
22
21
20
19
18
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
GNDBUF
16
CMOS
15
LVDSB
14
PECLB
13
12
VDDBUF
VDDBUF
11
PECL
10
LVDS
9
3
4
5
6
GND
GND
GND
N/C
7
OE_SEL^
8
GNDBUF
2
GND
1
X
OUTPUT SELECTION AND ENABLE
DIE SPECIFICATIONS
Name
(0,0)
Y
17
C502A
DESCRIPTION
The PLL602-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) XO IC
Die, with selectable CMOS, LVDS or PECL output,
covering the 750kHz to 800MHz output range, using
a low frequency crystal.
This makes the PLL602-30 ideal as a universal die
for applications ranging from low frequency to
SONET.
(1550,1475)
Die ID:
A1414-14E
GND
•
•
•
•
XIN
GND
•
•
750kHz to 800MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -123dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, 115dBc/Hz for 622.08MHz).
Selectable CMOS, PECL and LVDS output.
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
12MHz to 25MHz crystal input.
Output Enable selector.
3.3V operation.
Available in DIE (65 mil x 62 mil).
62 mil
•
•
OUTSEL0^
65 mil
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
PECL
1
1
LVDS
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
0 (Default)
0
1 (Default)
Selected Output
State
Output enabled
1
Tri-state
0
Tri-state
1 (Default)
Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
BLOCK DIAGRAM
VCO
Divider
SEL
XIN
XOUT
Reference
Divider
XTAL
OSC
Phase
Detector
Charge
Pump
+
Loop
Filter
VCO
CLKBAR
CLK
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
0
SEL2
(Pad #29)
0
SEL1
(Pad #19)
0
SEL0
(Pad #20)
0
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Fin x 32
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Fin / 8
0
1
1
1
Fin x 2
1
0
0
0
Reserved
1
0
0
1
Fin / 2
Selected Multiplier
Reserved
1
0
1
0
Fin / 16
1
0
1
1
Fin x 4
1
1
0
0
Fin / 4
1
1
0
1
Fin x 8
1
1
1
0
Fin x 16
1
1
1
1
No multiplication
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
MIN.
V DD
VI
VO
TS
TA
TJ
-0.5
-0.5
-65
-40
MAX.
UNITS
4.6
V DD +0.5
V DD +0.5
150
85
125
260
2
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
CONDITIONS
MIN.
F XIN
C L (xtal)
RE
Parallel Fundamental Mode
12
TYP.
MAX.
UNITS
25
MHz
pF
30
Ω
20
AT cut
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
3. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current,
Dynamic (with
Loaded Outputs)
I DD
Operating Voltage
V DD
CONDITIONS
PECL/LVDS/CMOS
MIN.
MAX.
50
50
50
25/25/15
65/45/30
100/80/40
3.63
55
55
55
Fout<24MHz
24MHz<Fout<96MHz
96MHz<Fout<700MHz
2.97
45
45
45
@ 50% V DD (CMOS)
@ 1.25V (LVDS)
@ V DD – 1.3V (PECL)
Output Clock
Duty Cycle
TYP.
Short Circuit
Current
±50
UNITS
mA
V
%
mA
4. Jitter Specifications
PARAMETERS
Period jitter RMS 1
Period jitter Peak-toPeak 1
Integrated jitter RMS 2
CONDITIONS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
FREQUENCY
MIN.
TYP.
19.44MHz
77.76MHz
2.1
3.5
106.25MHz
4.1
155.52MHz
4.3
622.08MHz
6.0
19.44MHz
77.76MHz
17
30
106.25MHz
28
155.52MHz
27
622.08MHz
40
155.52MHz
622.08MHz
2.6
2.5
MAX.
UNITS
ps
ps
4
4
ps
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
Phase Noise 2 relative
to carrier
(typical)
19.44MHz
106.25MHz
155.52MHz
622.08MHz
-80
-70
-60
-50
-108
-98
-90
-77
-132
-122
-115
-102
-142
-123
-125
-115
-142
-117
-119
-108
dBc/Hz
1) Jitter analyzer: Wavecrest SIA-3000
2) Phase Noise System: Agilent E5500
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
6. CMOS Electrical Characteristics
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I OH
I OL
I OH
I OL
CONDITIONS
V OH = V DD -0.4V, V DD =3.3V
V OL = 0.4V, V DD = 3.3V
V OH = V DD -0.4V, V DD =3.3V
V OL = 0.4V, V DD = 3.3V
MIN.
TYP.
30
30
10
10
MAX.
UNITS
mA
mA
mA
mA
0.3V ~ 3.0V with 15 pF load
2.4
0.3V ~ 3.0V with 15 pF load
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
Output Differential Voltage
V DD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
∆V OD
V OH
V OL
V OS
Power-off Leakage
I OXD
Output Short Circuit Current
I OSD
CONDITIONS
V OD
R L = 100 Ω
(see figure)
MIN.
TYP.
MAX.
UNITS
247
-50
355
454
50
1.6
0.9
1.125
0
∆V OS
V out = V DD or GND
V DD = 0V
1.4
1.1
1.2
3
1.375
25
mV
mV
V
V
V
mV
±1
±10
uA
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
0.2
0.7
1.0
ns
Differential Clock Fall Time
tf
R L = 100 Ω
C L = 10 pF
(see figure)
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50Ω
VOD
VDIFF
VOS
RL = 100Ω
50Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
VDIFF
80%
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN.
V OH
V OL
R L = 50 Ω to (V DD – 2V)
(see figure)
V DD – 1.025
MAX.
UNITS
V DD – 1.620
V
V
10. PECL Switching Characteristics
PARAMETERS
SYMBOL
Clock Rise Time
Clock Fall Time
CONDITIONS
tr
tf
@20/80% - PECL
@80/20% - PECL
PECL Levels Test Circuit
OUT
TYP.
MAX.
UNITS
0.6
0.5
1.5
1.5
ns
ns
PECL Output Skew
VDD
50Ω
MIN.
OUT
2.0V
50%
50Ω
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 6
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
PAD ASSIGNMENT
Pad #
Name
X (µm)
Y (µm)
Description
1
GND
248
109
Ground.
2
GND
361
109
Ground.
3
GND
473
109
Ground.
4
GND
587
109
Ground.
5
GND
702
109
Ground.
6
N/C
874
109
No Connection.
7
GND
1042
109
Ground.
8
GNDBUF
1171
109
Ground, buffer circuitry.
9
OE_SELECT
1400
125
Used to select between PECL or CMOS logic states for OE.
Internal pull up.
10
LVDS
1400
259
LVDS Output.
11
PECL
1400
476
PECL Output.
12
VDDBUF
1400
616
3.3V power supply, Buffer circuitry.
13
VDDBUF
1400
716
3.3V power supply, Buffer circuitry.
14
PECLB
1400
871
Complementary PECL Output.
15
LVDSB
1400
1089
Complementary LVDS Output.
16
CMOS
1400
1227
CMOS Output.
17
GNDBUF
1389
1365
Ground, buffer circuitry.
18
OUTSEL1
1232
1365
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
19
SEL1
1042
1365
Used to select multiplication factor. Internal pull up.
20
SEL0
854
1365
Used to select multiplication factor. Internal pull up.
21
VDD
659
1365
3.3V power supply.
22
VDD
559
1365
3.3V power supply.
23
VDD
459
1365
3.3V power supply.
24
VDD
358
1365
3.3V power supply.
25
OUTSEL0
194
1365
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
26
XIN
109
1223
Crystal input. See crystal specification page 3.
27
XOUT
109
1017
Crystal output. See crystal specification page 3.
28
SEL3
109
858
Used to select multiplication factor. Internal pull up.
29
SEL2
109
646
Used to select multiplication factor. Internal pull up.
30
OE_CTRL
109
397
Used to enable/disable the output(s). See Output Selection and
Enable table on page 1.
31
NC
109
181
No Connect
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 7
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-30 D C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
D=DIE
Order Number
Marking
Package Option
PLL602-30DC
PLL602-30DC
Die – Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 8